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https://github.com/u-boot/u-boot.git
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net: mediatek: add USXGMII support
This patch adds support for USXGMII of SoC. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
118855e859
commit
ba026ebe46
@ -105,6 +105,11 @@ struct mtk_eth_priv {
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struct regmap *infra_regmap;
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struct regmap *usxgmii_regmap;
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struct regmap *xfi_pextp_regmap;
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struct regmap *xfi_pll_regmap;
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struct regmap *toprgu_regmap;
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struct mii_dev *mdio_bus;
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int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
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int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
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@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk_eth_priv *priv)
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return 0;
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}
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static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
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{
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u16 lcl_adv = 0, rmt_adv = 0;
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u8 flowctrl;
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u32 mcr;
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mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
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mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
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if (priv->phydev->duplex) {
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if (priv->phydev->pause)
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rmt_adv = LPA_PAUSE_CAP;
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if (priv->phydev->asym_pause)
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rmt_adv |= LPA_PAUSE_ASYM;
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if (priv->phydev->advertising & ADVERTISED_Pause)
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lcl_adv |= ADVERTISE_PAUSE_CAP;
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if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
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lcl_adv |= ADVERTISE_PAUSE_ASYM;
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flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
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if (flowctrl & FLOW_CTRL_TX)
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mcr |= XGMAC_FORCE_TX_FC;
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if (flowctrl & FLOW_CTRL_RX)
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mcr |= XGMAC_FORCE_RX_FC;
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debug("rx pause %s, tx pause %s\n",
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flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
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flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
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}
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mcr &= ~(XGMAC_TRX_DISABLE);
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mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
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}
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static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
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{
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u16 lcl_adv = 0, rmt_adv = 0;
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@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_priv *priv)
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return 0;
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}
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if (!priv->force_mode)
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mtk_phy_link_adjust(priv);
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if (!priv->force_mode) {
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if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
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mtk_xphy_link_adjust(priv);
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else
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mtk_phy_link_adjust(priv);
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}
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debug("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
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SGMII_PHYA_PWD, 0);
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}
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static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
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{
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u32 val = 0;
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/* Add software workaround for USXGMII PLL TCL issue */
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regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
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RG_XFI_PLL_ANA_SWWA);
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regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
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val |= RG_XFI_PLL_EN;
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regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
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}
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static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
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{
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switch (priv->gmac_id) {
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case 1:
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regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
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regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
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regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
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regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
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regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
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break;
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case 2:
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regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
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regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
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regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
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regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
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regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
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break;
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}
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mdelay(10);
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}
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static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
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{
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regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
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regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
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regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
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ndelay(1020);
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regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
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ndelay(1020);
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regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
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regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
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regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
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regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
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regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
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regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
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regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
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regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
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regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
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regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
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regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
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regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
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regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
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regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
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regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
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regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
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regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
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regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
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regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
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regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
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regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
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regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
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regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
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regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
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ndelay(1020);
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regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
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regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
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regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
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regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
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regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
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regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
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regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
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regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
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regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
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regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
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regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
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regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
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regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
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udelay(150);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
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ndelay(1020);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
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udelay(15);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
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ndelay(1020);
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regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
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udelay(100);
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regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
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regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
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regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
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udelay(400);
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}
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static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
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{
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mtk_xfi_pll_enable(priv);
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mtk_usxgmii_reset(priv);
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mtk_usxgmii_setup_phya_an_10000(priv);
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}
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static void mtk_mac_init(struct mtk_eth_priv *priv)
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{
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int i, ge_mode = 0;
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@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
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}
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}
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static void mtk_xmac_init(struct mtk_eth_priv *priv)
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{
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u32 sts;
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switch (priv->phy_interface) {
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case PHY_INTERFACE_MODE_USXGMII:
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mtk_usxgmii_an_init(priv);
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break;
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default:
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break;
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}
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/* Set GMAC to the correct mode */
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mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
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SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
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0);
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if (priv->gmac_id == 1) {
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mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
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NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
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} else if (priv->gmac_id == 2) {
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sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
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sts |= XGMAC_FORCE_LINK;
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mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
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}
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/* Force GMAC link down */
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mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
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}
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static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
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{
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char *pkt_base = priv->pkt_pool;
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@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice *dev)
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ARCH_DMA_MINALIGN);
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/* Set MAC mode */
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mtk_mac_init(priv);
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if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
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mtk_xmac_init(priv);
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else
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mtk_mac_init(priv);
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/* Probe phy if switch is not specified */
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if (priv->sw == SW_NONE)
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@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
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}
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priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
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} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
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/* get corresponding usxgmii phandle */
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ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
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NULL, 0, 0, &args);
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if (ret)
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return ret;
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priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
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if (IS_ERR(priv->usxgmii_regmap))
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return PTR_ERR(priv->usxgmii_regmap);
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/* get corresponding xfi_pextp phandle */
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ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
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NULL, 0, 0, &args);
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if (ret)
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return ret;
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priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
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if (IS_ERR(priv->xfi_pextp_regmap))
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return PTR_ERR(priv->xfi_pextp_regmap);
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/* get corresponding xfi_pll phandle */
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ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
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NULL, 0, 0, &args);
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if (ret)
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return ret;
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priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
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if (IS_ERR(priv->xfi_pll_regmap))
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return PTR_ERR(priv->xfi_pll_regmap);
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/* get corresponding toprgu phandle */
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ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
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NULL, 0, 0, &args);
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if (ret)
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return ret;
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priv->toprgu_regmap = syscon_node_to_regmap(args.node);
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if (IS_ERR(priv->toprgu_regmap))
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return PTR_ERR(priv->toprgu_regmap);
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}
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/* check for switch first, otherwise phy will be used */
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@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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/* Top misc registers */
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#define TOPMISC_NETSYS_PCS_MUX 0x84
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#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
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#define MUX_G2_USXGMII_SEL BIT(1)
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#define MUX_HSGMII1_G1_SEL BIT(0)
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#define USB_PHY_SWITCH_REG 0x218
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#define QPHY_SEL_MASK 0x3
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#define SGMII_QPHY_SEL 0x2
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@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
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#define SGMSYS_GEN2_SPEED_V2 0x128
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#define SGMSYS_SPEED_2500 BIT(2)
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/* USXGMII subsystem config registers */
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/* Register to control USXGMII XFI PLL digital */
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#define XFI_PLL_DIG_GLB8 0x08
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#define RG_XFI_PLL_EN BIT(31)
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/* Register to control USXGMII XFI PLL analog */
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#define XFI_PLL_ANA_GLB8 0x108
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#define RG_XFI_PLL_ANA_SWWA 0x02283248
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/* Frame Engine Registers */
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#define FE_GLO_MISC_REG 0x124
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#define PDMA_VER_V2 BIT(4)
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@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
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#define TD_DM_DRVP_S 0
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#define TD_DM_DRVP_M 0x0f
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/* XGMAC Status Registers */
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#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C)
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#define XGMAC_FORCE_LINK BIT(15)
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/* XGMAC Registers */
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#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000))
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#define XGMAC_TRX_DISABLE 0xf
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#define XGMAC_FORCE_TX_FC BIT(5)
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#define XGMAC_FORCE_RX_FC BIT(4)
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/* MT7530 Registers */
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#define PCR_REG(p) (0x2004 + (p) * 0x100)
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