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fpga: zynqpl: Add support for zc7035

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Added support for zc7035

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu 2014-11-25 15:29:54 +05:30 committed by Michal Simek
parent e136eaeb4d
commit b9103809eb
2 changed files with 10 additions and 0 deletions
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4
board/xilinx/zynq/board.c
View File

@ -24,6 +24,7 @@ static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif #endif
@ -49,6 +50,9 @@ int board_init(void)
case XILINX_ZYNQ_7030: case XILINX_ZYNQ_7030:
fpga = fpga030; fpga = fpga030;
break; break;
case XILINX_ZYNQ_7035:
fpga = fpga035;
break;
case XILINX_ZYNQ_7045: case XILINX_ZYNQ_7045:
fpga = fpga045; fpga = fpga045;
break; break;

6
include/zynqpl.h
View File

@ -23,6 +23,7 @@ extern struct xilinx_fpga_op zynq_op;
#define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7035 0x12
#define XILINX_ZYNQ_7045 0x11 #define XILINX_ZYNQ_7045 0x11
#define XILINX_ZYNQ_7100 0x16 #define XILINX_ZYNQ_7100 0x16
@ -31,6 +32,7 @@ extern struct xilinx_fpga_op zynq_op;
#define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z035_SIZE 106571232/8
#define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8 #define XILINX_XC7Z100_SIZE 139330784/8
@ -51,6 +53,10 @@ extern struct xilinx_fpga_op zynq_op;
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z030" } "7z030" }
#define XILINX_XC7Z035_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z035" }
#define XILINX_XC7Z045_DESC(cookie) \ #define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z045" } "7z045" }