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gpio: add nexell driver
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - livetree API (dev_read_...) is used instead of fdt one (fdt...). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
This commit is contained in:
Stefan Bosch
Tom Rini
parent
95e9a8e2cb
commit
b8f748d6f2
@ -457,4 +457,13 @@ config MT7621_GPIO
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help
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Say yes here to support MediaTek MT7621 compatible GPIOs.
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config NX_GPIO
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bool "Nexell GPIO driver"
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depends on DM_GPIO
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help
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Support GPIO access on Nexell SoCs. The GPIOs are arranged into
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a number of banks (different for each SoC type) each with 32 GPIOs.
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The GPIOs for a device are defined in the device tree with one node
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for each bank.
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endmenu
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@ -64,4 +64,5 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
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obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
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obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
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obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
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obj-$(CONFIG_NX_GPIO) += nx_gpio.o
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obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
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250
drivers/gpio/nx_gpio.c
Normal file
250
drivers/gpio/nx_gpio.c
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@ -0,0 +1,250 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* DeokJin, Lee <truevirtue@nexell.co.kr>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct nx_gpio_regs {
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u32 data; /* Data register */
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u32 outputenb; /* Output Enable register */
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u32 detmode[2]; /* Detect Mode Register */
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u32 intenb; /* Interrupt Enable Register */
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u32 det; /* Event Detect Register */
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u32 pad; /* Pad Status Register */
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};
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struct nx_alive_gpio_regs {
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u32 pwrgate; /* Power Gating Register */
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u32 reserved0[28]; /* Reserved0 */
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u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
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u32 outputenb; /* Alive GPIO Output Enable Register */
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u32 outputenb_read; /* Alive GPIO Output Read Register */
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u32 reserved1[3]; /* Reserved1 */
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u32 pad_reset; /* Alive GPIO Output Reset Register */
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u32 data; /* Alive GPIO Output Register */
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u32 pad_read; /* Alive GPIO Pad Read Register */
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u32 reserved2[33]; /* Reserved2 */
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u32 pad; /* Alive GPIO Input Value Register */
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};
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struct nx_gpio_platdata {
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void *regs;
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int gpio_count;
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const char *bank_name;
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};
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static int nx_alive_gpio_is_check(struct udevice *dev)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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const char *bank_name = plat->bank_name;
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if (!strcmp(bank_name, "gpio_alv"))
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return 1;
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return 0;
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}
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static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_alive_gpio_regs *const regs = plat->regs;
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setbits_le32(®s->outputenb_reset, 1 << pin);
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return 0;
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}
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static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int pin,
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int val)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_alive_gpio_regs *const regs = plat->regs;
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if (val)
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setbits_le32(®s->data, 1 << pin);
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else
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setbits_le32(®s->pad_reset, 1 << pin);
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setbits_le32(®s->outputenb, 1 << pin);
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return 0;
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}
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static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_alive_gpio_regs *const regs = plat->regs;
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unsigned int mask = 1UL << pin;
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unsigned int value;
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value = (readl(®s->pad_read) & mask) >> pin;
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return value;
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}
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static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
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int val)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_alive_gpio_regs *const regs = plat->regs;
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if (val)
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setbits_le32(®s->data, 1 << pin);
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else
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clrbits_le32(®s->pad_reset, 1 << pin);
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return 0;
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}
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static int nx_alive_gpio_get_function(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_alive_gpio_regs *const regs = plat->regs;
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unsigned int mask = (1UL << pin);
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unsigned int output;
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output = readl(®s->outputenb_read) & mask;
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if (output)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int nx_gpio_direction_input(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_gpio_regs *const regs = plat->regs;
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if (nx_alive_gpio_is_check(dev))
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return nx_alive_gpio_direction_input(dev, pin);
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clrbits_le32(®s->outputenb, 1 << pin);
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return 0;
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}
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static int nx_gpio_direction_output(struct udevice *dev, unsigned int pin,
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int val)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_gpio_regs *const regs = plat->regs;
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if (nx_alive_gpio_is_check(dev))
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return nx_alive_gpio_direction_output(dev, pin, val);
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if (val)
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setbits_le32(®s->data, 1 << pin);
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else
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clrbits_le32(®s->data, 1 << pin);
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setbits_le32(®s->outputenb, 1 << pin);
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return 0;
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}
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static int nx_gpio_get_value(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_gpio_regs *const regs = plat->regs;
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unsigned int mask = 1UL << pin;
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unsigned int value;
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if (nx_alive_gpio_is_check(dev))
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return nx_alive_gpio_get_value(dev, pin);
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value = (readl(®s->pad) & mask) >> pin;
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return value;
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}
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static int nx_gpio_set_value(struct udevice *dev, unsigned int pin, int val)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_gpio_regs *const regs = plat->regs;
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if (nx_alive_gpio_is_check(dev))
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return nx_alive_gpio_set_value(dev, pin, val);
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if (val)
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setbits_le32(®s->data, 1 << pin);
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else
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clrbits_le32(®s->data, 1 << pin);
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return 0;
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}
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static int nx_gpio_get_function(struct udevice *dev, unsigned int pin)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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struct nx_gpio_regs *const regs = plat->regs;
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unsigned int mask = (1UL << pin);
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unsigned int output;
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if (nx_alive_gpio_is_check(dev))
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return nx_alive_gpio_get_function(dev, pin);
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output = readl(®s->outputenb) & mask;
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if (output)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int nx_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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uc_priv->gpio_count = plat->gpio_count;
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uc_priv->bank_name = plat->bank_name;
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return 0;
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}
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static int nx_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct nx_gpio_platdata *plat = dev_get_platdata(dev);
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plat->regs = map_physmem(devfdt_get_addr(dev),
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sizeof(struct nx_gpio_regs),
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MAP_NOCACHE);
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plat->gpio_count = dev_read_s32_default(dev, "nexell,gpio-bank-width",
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32);
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plat->bank_name = dev_read_string(dev, "gpio-bank-name");
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return 0;
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}
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static const struct dm_gpio_ops nx_gpio_ops = {
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.direction_input = nx_gpio_direction_input,
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.direction_output = nx_gpio_direction_output,
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.get_value = nx_gpio_get_value,
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.set_value = nx_gpio_set_value,
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.get_function = nx_gpio_get_function,
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};
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static const struct udevice_id nx_gpio_ids[] = {
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{ .compatible = "nexell,nexell-gpio" },
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{ }
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};
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U_BOOT_DRIVER(nx_gpio) = {
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.name = "nx_gpio",
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.id = UCLASS_GPIO,
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.of_match = nx_gpio_ids,
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.ops = &nx_gpio_ops,
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.ofdata_to_platdata = nx_gpio_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct nx_gpio_platdata),
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.probe = nx_gpio_probe,
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};
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