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Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"

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This reverts commit 72a89e0da5, which
causes the imx53 HSC to hang as the eMMC is not working properly anymore.

The exact error message:
MMC write: dev # 0, block # 2, count 927 ... mmc write failed
0 blocks written: ERROR

imx53 is not using the DDR mode.

Debugging of pre_div and div generation showed that those values are
generated in a way, which is not matching the ones from working setup.

As the original patch was performing code refactoring, let's revert this
change, so all imx53 boards would work again.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski 2019-05-07 17:47:28 +02:00 committed by Peng Fan
parent e14d9ca491
commit b6a0427554
1 changed files with 5 additions and 18 deletions
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23
drivers/mmc/fsl_esdhc.c
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@ -621,31 +621,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
#else
int pre_div = 2;
#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
int sdhc_clk = priv->sdhc_clk;
uint clk;
/*
* For ddr mode, usdhc need to enable DDR mode first, after select
* this DDR mode, usdhc will automatically divide the usdhc clock
*/
if (mmc->ddr_mode) {
writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl);
sdhc_clk >>= 1;
}
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
if (sdhc_clk / 16 > clock) {
for (; pre_div < 256; pre_div *= 2)
if ((sdhc_clk / pre_div) <= (clock * 16))
break;
} else
pre_div = 1;
while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
pre_div *= 2;
for (div = 1; div <= 16; div++)
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
div++;
pre_div >>= 1;
div -= 1;