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imx: zmx25: Convert to iomux-v3
There is no change of behavior, even if some pad control values could probably be simplified. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau
Stefano Babic
parent
97549cb546
commit
b597ff6be9
@ -32,91 +32,85 @@
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx25-pinmux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/iomux-mx25.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init()
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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struct iomuxc_pad_input_select *inputselect;
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u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
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u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
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u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
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u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
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static const iomux_v3_cfg_t sdhc1_pads[] = {
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NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
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};
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static const iomux_v3_cfg_t dig_out_pads[] = {
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MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
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MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
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NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
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NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
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};
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static const iomux_v3_cfg_t led_pads[] = {
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MX25_PAD_CSI_D9__GPIO_4_21,
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MX25_PAD_CSI_D4__GPIO_1_29,
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};
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static const iomux_v3_cfg_t can_pads[] = {
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NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
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};
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static const iomux_v3_cfg_t i2c3_pads[] = {
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MX25_PAD_CSPI1_SS1__I2C3_DAT,
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MX25_PAD_GPIO_E__I2C3_CLK,
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};
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icache_enable();
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
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/* Setup of core volatage selection pin to run at 1.4V */
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writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
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/* Setup of core voltage selection pin to run at 1.4V */
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imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
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gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
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/* Setup of input daisy chains for SD card pins*/
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
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/* Setup of SD card pins*/
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imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
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/* Setup of digital output for USB power and OC */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
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imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
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gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
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writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
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imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
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gpio_direction_input(IMX_GPIO_NR(1, 18));
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/* Setup of digital output control pins */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
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writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
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writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
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writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
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imx_iomux_v3_setup_multiple_pads(dig_out_pads,
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ARRAY_SIZE(dig_out_pads));
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/* Switch both output drivers off */
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gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
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gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
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/* Setup of key input pin GPIO2[29]*/
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writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
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writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
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/* Setup of key input pin */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
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gpio_direction_input(IMX_GPIO_NR(2, 29));
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/* Setup of status LED outputs */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
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imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
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/* Switch both LEDs off */
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gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
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gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
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/* Setup of CAN1 and CAN2 signals */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
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/* Setup of input daisy chains for CAN signals*/
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writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
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writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
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imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
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/* Setup of I2C3 signals */
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writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
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writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
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/* Setup of input daisy chains for I2C3 signals*/
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writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
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writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
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imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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@ -128,25 +122,32 @@ int board_late_init(void)
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const char *e;
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#ifdef CONFIG_FEC_MXC
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struct iomuxc_mux_ctl *muxctl;
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u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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/*
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* FIXME: need to revisit this
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* The original code enabled PUE and 100-k pull-down without PKE, so the right
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* value here is likely:
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* 0 for no pull
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* or:
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* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
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*/
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#define FEC_OUT_PAD_CTRL 0
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/*
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* fec pin init is generic
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*/
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mx25_fec_init_pins();
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static const iomux_v3_cfg_t fec_pads[] = {
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MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX25_PAD_FEC_RX_DV__FEC_RX_DV,
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MX25_PAD_FEC_RDATA0__FEC_RDATA0,
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NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
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NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
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MX25_PAD_FEC_MDIO__FEC_MDIO,
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MX25_PAD_FEC_RDATA1__FEC_RDATA1,
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NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
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/*
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* Set up LAN-RESET and FEC_RX_ERR
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*
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* LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
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* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
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*/
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
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MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
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};
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writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
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writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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/* assert PHY reset (low) */
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gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
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