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spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data

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The current implementation encounters issues when testing data ranging
from 0 to 8 bytes. This was confirmed through testing with both ISSI
(IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.

Upon investigation, it was observed that utilizing the
"SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in
STIG mode results in a read failure, leading to a compare test failure.

To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized
instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode.

This is based on patch series:
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Tejas Bhumkar 2024-01-28 12:07:46 +05:30 committed by Jagan Teki
parent 18e61f2378
commit b4b0228db8
3 changed files with 7 additions and 3 deletions
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3
drivers/spi/cadence_ospi_versal.c
View File

@ -18,9 +18,6 @@
#include "cadence_qspi.h" #include "cadence_qspi.h"
#include <dt-bindings/power/xlnx-versal-power.h> #include <dt-bindings/power/xlnx-versal-power.h>
#define CMD_4BYTE_READ 0x13
#define CMD_4BYTE_FAST_READ 0x0C
int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op) const struct spi_mem_op *op)
{ {

4
drivers/spi/cadence_qspi.h
View File

@ -33,6 +33,10 @@
#define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_DUMMY_CLKS_MAX 31 #define CQSPI_DUMMY_CLKS_MAX 31
#define CMD_4BYTE_FAST_READ 0x0C
#define CMD_4BYTE_OCTAL_READ 0x7c
#define CMD_4BYTE_READ 0x13
/**************************************************************************** /****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE) * Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/ ****************************************************************************/

3
drivers/spi/cadence_qspi_apb.c
View File

@ -469,6 +469,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
else else
opcode = op->cmd.opcode; opcode = op->cmd.opcode;
if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
opcode = CMD_4BYTE_FAST_READ;
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
/* Set up dummy cycles. */ /* Set up dummy cycles. */