mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-24 04:34:22 +08:00
* Patch by Andre Schwarz, 24 Nov 2003:
add support for mvblue (mvBlueLYNX and mvBlueBOX) boards * Patch by Pavel Bartusek, 21 Nov 2003: set ZMII bridge speed on 440 * Patch by Anders Larsen, 17 Nov 2003: Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
This commit is contained in:
wdenk
parent
a2663ea4fc
commit
b4676a25e2
@ -2,6 +2,15 @@
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Changes since U-Boot 1.0.0:
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======================================================================
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* Patch by Andre Schwarz, 24 Nov 2003:
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add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
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* Patch by Pavel Bartusek, 21 Nov 2003:
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set ZMII bridge speed on 440
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* Patch by Anders Larsen, 17 Nov 2003:
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Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
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* Patches by David Müller, 14 Nov 2003:
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- board/mpl/common/common_util.c
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* implement support for BZIP2 compressed images
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6
MAKEALL
6
MAKEALL
@ -71,9 +71,9 @@ LIST_4xx=" \
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LIST_824x=" \
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A3000 BMW CPC45 CU824 \
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debris MOUSSE MUSENKI OXC \
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PN62 Sandpoint8240 Sandpoint8245 SL8245 \
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utx8245 \
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debris MOUSSE MUSENKI MVBLUE \
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OXC PN62 Sandpoint8240 Sandpoint8245 \
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SL8245 utx8245 \
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"
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#########################################################################
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3
Makefile
3
Makefile
@ -638,6 +638,9 @@ MOUSSE_config: unconfig
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MUSENKI_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x musenki
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MVBLUE_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x mvblue
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OXC_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x oxc
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41
board/mvblue/Makefile
Normal file
41
board/mvblue/Makefile
Normal file
@ -0,0 +1,41 @@
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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SOBJS =
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$(LIB): .depend $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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26
board/mvblue/config.mk
Normal file
26
board/mvblue/config.mk
Normal file
@ -0,0 +1,26 @@
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#
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# (C) Copyright 2001-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFF00000
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
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583
board/mvblue/flash.c
Normal file
583
board/mvblue/flash.c
Normal file
@ -0,0 +1,583 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* (C) Copyright 2001-2003
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*
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* Changes for MATRIX Vision mvBLUE devices
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* MATRIX Vision GmbH / hg,as info@matrix-vision.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#if 0
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#define mvdebug(p) printf ##p
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#else
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#define mvdebug(p)
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#endif
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define FLASH_BUS_WIDTH 8
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#if (FLASH_BUS_WIDTH==32)
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#define FLASH_DATA_MASK 0xffffffff
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#define FLASH_SHIFT 1
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#define FDT vu_long
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#elif (FLASH_BUS_WIDTH==16)
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#define FLASH_DATA_MASK 0xff
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#define FLASH_SHIFT 0
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#define FDT vu_short
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#elif (FLASH_BUS_WIDTH==8)
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#define FLASH_DATA_MASK 0xff
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#define FLASH_SHIFT 0
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#define FDT vu_char
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#else
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#error FLASH_BUS_WIDTH undefined
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#endif
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *address, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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int i;
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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size_b0 = flash_get_size((vu_long *)0xffc00000, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH : Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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flash_get_offsets (0xffc00000, &flash_info[0]);
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flash_info[0].size = size_b0;
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/* monitor protection OFF by default */
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flash_protect ( FLAG_PROTECT_CLEAR, 0xffc00000, 0x2000, flash_info );
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return size_b0;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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/* set up sector start address table */
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if (info->flash_id & FLASH_BTYPE)
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{ /* bottom boot sector types - these are the useful ones! */
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/* set sector offsets for bottom boot block type */
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
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{ /* AMDLV320B has 8 x 8k bottom boot sectors */
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for (i = 0; i < 8; i++) /* +8k */
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info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
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for (; i < info->sector_count; i++) /* +64k */
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info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
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}
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else
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{ /* other types have 4 bottom boot sectors (16,8,8,32) */
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i = 0;
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info->start[i++] = base + 0x00000000; /* - */
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info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */
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info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */
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info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */
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info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */
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for (; i < info->sector_count; i++) /* +64k */
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info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
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}
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}
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else
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{ /* top boot sector types - not so useful */
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/* set sector offsets for top boot block type */
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
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{ /* AMDLV320T has 8 x 8k top boot sectors */
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for (i = 0; i < info->sector_count - 8; i++) /* +64k */
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info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
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for (; i < info->sector_count; i++) /* +8k */
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info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
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}
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else
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{ /* other types have 4 top boot sectors (32,8,8,16) */
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for (i = 0; i < info->sector_count - 4; i++) /* +64k */
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info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
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info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */
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info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */
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info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */
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info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_STM: printf ("ST "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
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break;
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case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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}
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|
||||
/*
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||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK)
|
||||
#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK)
|
||||
#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK)
|
||||
#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK)
|
||||
#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK)
|
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#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK)
|
||||
#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK)
|
||||
#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK)
|
||||
#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK)
|
||||
|
||||
#if (FLASH_BUS_WIDTH >= 16)
|
||||
#define AUTOSELECT_ADDR1 0x0555
|
||||
#define AUTOSELECT_ADDR2 0x02AA
|
||||
#define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1
|
||||
#else
|
||||
#define AUTOSELECT_ADDR1 0x0AAA
|
||||
#define AUTOSELECT_ADDR2 0x0555
|
||||
#define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1
|
||||
#endif
|
||||
|
||||
#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
|
||||
#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK)
|
||||
#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK)
|
||||
|
||||
#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK)
|
||||
|
||||
|
||||
static ulong flash_get_size (vu_long *address, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
FDT value;
|
||||
FDT *addr = (FDT *)address;
|
||||
|
||||
ulong base = (ulong)address;
|
||||
addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
|
||||
addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
|
||||
addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
udelay(180);
|
||||
|
||||
value = addr[0]; /* manufacturer ID */
|
||||
switch (value) {
|
||||
case AMD_MANUFACT_MVS:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case FUJ_MANUFACT_MVS:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case STM_MANUFACT_MVS:
|
||||
info->flash_id = FLASH_MAN_STM;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
#if (FLASH_BUS_WIDTH >= 16)
|
||||
value = addr[1]; /* device ID */
|
||||
#else
|
||||
value = addr[2]; /* device ID */
|
||||
#endif
|
||||
|
||||
switch (value) {
|
||||
case AMD_ID_LV160T_MVS:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 37;
|
||||
info->size = (0x00200000 << FLASH_SHIFT);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case AMD_ID_LV160B_MVS:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 37;
|
||||
info->size = (0x00200000 << FLASH_SHIFT);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case AMD_ID_LV320T_MVS:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 71;
|
||||
info->size = (0x00400000 << FLASH_SHIFT);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case AMD_ID_LV320B_MVS:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 71;
|
||||
info->size = (0x00400000 << FLASH_SHIFT);
|
||||
break; /* => 4 or 8MB */
|
||||
|
||||
case STM_ID_W320DT_MVS:
|
||||
info->flash_id += FLASH_STMW320DT;
|
||||
info->sector_count = 67;
|
||||
info->size = (0x00400000 << FLASH_SHIFT);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case STM_ID_W320DB_MVS:
|
||||
info->flash_id += FLASH_STMW320DB;
|
||||
info->sector_count = 67;
|
||||
info->size = (0x00400000 << FLASH_SHIFT);
|
||||
break; /* => 4 or 8MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
flash_get_offsets (base, info);
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (FDT *)(info->start[i]);
|
||||
info->protect[i] = addr[2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr = (FDT *)info->start[0];
|
||||
*addr = RESET_BANK_DATA; /* reset bank */
|
||||
}
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if (FLASH_BUS_WIDTH >= 16)
|
||||
#define ERASE_ADDR1 0x0555
|
||||
#define ERASE_ADDR2 0x02AA
|
||||
#else
|
||||
#define ERASE_ADDR1 0x0AAA
|
||||
#define ERASE_ADDR2 0x0555
|
||||
#endif
|
||||
|
||||
#define ERASE_ADDR3 ERASE_ADDR1
|
||||
#define ERASE_ADDR4 ERASE_ADDR1
|
||||
#define ERASE_ADDR5 ERASE_ADDR2
|
||||
|
||||
#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
|
||||
#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
|
||||
#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
|
||||
#define ERASE_DATA4 ERASE_DATA1
|
||||
#define ERASE_DATA5 ERASE_DATA2
|
||||
|
||||
#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK)
|
||||
#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK)
|
||||
#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK)
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
FDT *addr = (FDT *)(info->start[0]);
|
||||
|
||||
int prot, sect, l_sect, flag;
|
||||
ulong start, now, last;
|
||||
|
||||
__asm__ __volatile__ ("sync");
|
||||
addr[0] = 0xf0;
|
||||
udelay(1000);
|
||||
|
||||
printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] );
|
||||
printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] );
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[ERASE_ADDR1] = ERASE_DATA1;
|
||||
addr[ERASE_ADDR2] = ERASE_DATA2;
|
||||
addr[ERASE_ADDR3] = ERASE_DATA3;
|
||||
addr[ERASE_ADDR4] = ERASE_DATA4;
|
||||
addr[ERASE_ADDR5] = ERASE_DATA5;
|
||||
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) {
|
||||
addr = (FDT *)(info->start[sect]);
|
||||
addr[0] = ERASE_SECTOR_DATA;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (FDT *)(info->start[l_sect]);
|
||||
|
||||
while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
#define BUFF_INC 4
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt));
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<BUFF_INC && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += BUFF_INC;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle (half)word aligned part
|
||||
*/
|
||||
mvdebug ((" handle word aligned part (cnt = 0x%08lx)\n", cnt));
|
||||
while (cnt >= BUFF_INC) {
|
||||
data = 0;
|
||||
for (i=0; i<BUFF_INC; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += BUFF_INC;
|
||||
cnt -= BUFF_INC;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
mvdebug ((" handle unaligned tail bytes (cnt = 0x%08lx)\n", cnt));
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<BUFF_INC; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
#if (FLASH_BUS_WIDTH >= 16)
|
||||
#define WRITE_ADDR1 0x0555
|
||||
#define WRITE_ADDR2 0x02AA
|
||||
#else
|
||||
#define WRITE_ADDR1 0x0AAA
|
||||
#define WRITE_ADDR2 0x0555
|
||||
#define WRITE_ADDR3 WRITE_ADDR1
|
||||
#endif
|
||||
|
||||
#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
|
||||
#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
|
||||
#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
|
||||
|
||||
#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a byte to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_char (flash_info_t *info, ulong dest, uchar data)
|
||||
{
|
||||
vu_char *addr = (vu_char *)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_char *)dest) & data) != data) {
|
||||
printf(" *** ERROR: Flash not erased !\n");
|
||||
return (2);
|
||||
}
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[WRITE_ADDR1] = WRITE_DATA1;
|
||||
addr[WRITE_ADDR2] = WRITE_DATA2;
|
||||
addr[WRITE_ADDR3] = WRITE_DATA3;
|
||||
*((vu_char *)dest) = data;
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
addr = (vu_char *)dest;
|
||||
while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
printf(" *** ERROR: Flash write timeout !");
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
mvdebug (("-write_byte\n"));
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
int i,
|
||||
result = 0;
|
||||
|
||||
mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest));
|
||||
for ( i=0; (i < 4) && (result == 0); i++, dest+=1 )
|
||||
result = write_char (info, dest, (data >> (8*(3-i))) & 0xff );
|
||||
mvdebug (("-write_word\n"));
|
||||
return result;
|
||||
}
|
||||
/*---------------------------------------------------------------- */
|
||||
253
board/mvblue/mvblue.c
Normal file
253
board/mvblue/mvblue.c
Normal file
@ -0,0 +1,253 @@
|
||||
/*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* MATRIX Vision GmbH / June 2002-Nov 2003
|
||||
* Andre Schwarz
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc824x.h>
|
||||
#include <asm/io.h>
|
||||
#include <ns16550.h>
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#include <pci.h>
|
||||
#endif
|
||||
|
||||
u32 get_BoardType(void);
|
||||
|
||||
#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
|
||||
| ((d&0x1f)<<11) \
|
||||
| ((f&0x7)<<7) \
|
||||
| (r&0xfc) )
|
||||
|
||||
int mv_pci_read( int bus, int dev, int func, int reg )
|
||||
{
|
||||
*(u32*)(0xfec00cf8) = PCI_CONFIG(bus,dev,func,reg);
|
||||
asm("sync");
|
||||
return cpu_to_le32( *(u32*)(0xfee00cfc) );
|
||||
}
|
||||
u32 get_BoardType() {
|
||||
return ( mv_pci_read(0,0xe,0,0) == 0x06801095 ? 0 : 1 );
|
||||
}
|
||||
|
||||
void init_2nd_DUART(void)
|
||||
{
|
||||
NS16550_t console = (NS16550_t)CFG_NS16550_COM2;
|
||||
int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
|
||||
*(u8*)(0xfc004511) = 0x1;
|
||||
NS16550_init(console, clock_divisor);
|
||||
}
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
if (get_BoardType() == 0 ) {
|
||||
*(u32*)(0xff000005) = 0;
|
||||
asm("sync");
|
||||
}
|
||||
}
|
||||
int checkboard (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
ulong busfreq = get_bus_freq(0);
|
||||
char buf[32];
|
||||
u32 BoardType = get_BoardType();
|
||||
char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
|
||||
char *p;
|
||||
bd_t *bd = gd->bd;
|
||||
|
||||
hw_watchdog_reset();
|
||||
|
||||
printf("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
|
||||
printf(" Found %s running at %s MHz memory clock.\n", BoardName[BoardType], strmhz(buf, busfreq) );
|
||||
|
||||
init_2nd_DUART();
|
||||
|
||||
if ( (p = getenv("console_nr")) != NULL ) {
|
||||
unsigned long con_nr = simple_strtoul( p, NULL, 10) & 3;
|
||||
bd->bi_baudrate &= ~3;
|
||||
bd->bi_baudrate |= con_nr & 3;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
int i, cnt;
|
||||
volatile uchar * base= CFG_SDRAM_BASE;
|
||||
volatile ulong * addr;
|
||||
ulong save[32];
|
||||
ulong val, ret = 0;
|
||||
|
||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
||||
addr = (volatile ulong *)base + cnt;
|
||||
save[i++] = *addr;
|
||||
*addr = ~cnt;
|
||||
}
|
||||
|
||||
addr = (volatile ulong *)base;
|
||||
save[i] = *addr;
|
||||
*addr = 0;
|
||||
|
||||
if (*addr != 0) {
|
||||
*addr = save[i];
|
||||
goto Done;
|
||||
}
|
||||
|
||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
||||
addr = (volatile ulong *)base + cnt;
|
||||
val = *addr;
|
||||
*addr = save[--i];
|
||||
if (val != ~cnt) {
|
||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||
mear1 = (mear1 & 0xFFFFFF00) |
|
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||
emear1 = (emear1 & 0xFFFFFF00) |
|
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||
ret = cnt * sizeof(long);
|
||||
goto Done;
|
||||
}
|
||||
}
|
||||
|
||||
ret = CFG_MAX_RAM_SIZE;
|
||||
Done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
u8 *dhcp_vendorex_prep(u8 *e)
|
||||
{
|
||||
char *ptr;
|
||||
|
||||
/* DHCP vendor-class-identifier = 60 */
|
||||
if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
|
||||
*e++ = 60;
|
||||
*e++ = strlen(ptr);
|
||||
while (*ptr)
|
||||
*e++ = *ptr++;
|
||||
}
|
||||
/* my DHCP_CLIENT_IDENTIFIER = 61 */
|
||||
if ((ptr = getenv("dhcp_client_id"))) {
|
||||
*e++ = 61;
|
||||
*e++ = strlen(ptr);
|
||||
while (*ptr)
|
||||
*e++ = *ptr++;
|
||||
}
|
||||
return e;
|
||||
}
|
||||
u8 *dhcp_vendorex_proc(u8 *popt)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices
|
||||
*/
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_mvblue_clear_base( struct pci_controller *hose, pci_dev_t dev )
|
||||
{
|
||||
u32 cnt;
|
||||
printf("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV(dev), PCI_FUNC(dev) );
|
||||
for( cnt = 0; cnt < 6; cnt++ )
|
||||
pci_hose_write_config_dword( hose, dev, 0x10 + (4*cnt), 0x0 );
|
||||
printf("done\n");
|
||||
}
|
||||
|
||||
void duart_setup( u32 base, u16 divisor )
|
||||
{
|
||||
printf("duart setup ...");
|
||||
out_8( (u8*)( CFG_ISA_IO+base+3), 0x80);
|
||||
out_8( (u8*)( CFG_ISA_IO+base+0), divisor & 0xff);
|
||||
out_8( (u8*)( CFG_ISA_IO+base+1), divisor >> 8 );
|
||||
out_8( (u8*)( CFG_ISA_IO+base+3), 0x03);
|
||||
out_8( (u8*)( CFG_ISA_IO+base+4), 0x03);
|
||||
out_8( (u8*)( CFG_ISA_IO+base+2), 0x07);
|
||||
printf("done\n");
|
||||
}
|
||||
|
||||
void pci_mvblue_fixup_irq_behind_bridge( struct pci_controller *hose, pci_dev_t bridge, unsigned char irq)
|
||||
{
|
||||
pci_dev_t d;
|
||||
unsigned char bus;
|
||||
unsigned short vendor,
|
||||
class;
|
||||
|
||||
pci_hose_read_config_byte( hose, bridge, PCI_SECONDARY_BUS, &bus );
|
||||
for (d = PCI_BDF(bus,0,0);
|
||||
d < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
|
||||
d += PCI_BDF(0,0,1))
|
||||
{
|
||||
pci_hose_read_config_word(hose, d, PCI_VENDOR_ID, &vendor);
|
||||
if (vendor != 0xffff && vendor != 0x0000)
|
||||
{
|
||||
pci_hose_read_config_word( hose, d, PCI_CLASS_DEVICE, &class );
|
||||
if ( class == PCI_CLASS_BRIDGE_PCI )
|
||||
pci_mvblue_fixup_irq_behind_bridge( hose, d, irq );
|
||||
else
|
||||
pci_hose_write_config_byte( hose, d, PCI_INTERRUPT_LINE, irq );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define MV_MAX_PCI_BUSSES 3
|
||||
#define SLOT0_IRQ 3
|
||||
#define SLOT1_IRQ 4
|
||||
void pci_mvblue_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
unsigned char line=0xff;
|
||||
unsigned short class;
|
||||
|
||||
if( PCI_BUS(dev) == 0 ) {
|
||||
switch(PCI_DEV(dev)) {
|
||||
case 0xd:
|
||||
if ( get_BoardType() == 0 ) {
|
||||
line = 1;
|
||||
} else
|
||||
/* mvBL */
|
||||
line = 2;
|
||||
break;
|
||||
case 0xe:
|
||||
/* mvBB: IDE */
|
||||
line = 2;
|
||||
pci_hose_write_config_byte(hose, dev, 0x8a, 0x20 );
|
||||
break;
|
||||
case 0xf:
|
||||
/* mvBB: Slot0 (Grabber) */
|
||||
pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
|
||||
if ( class == PCI_CLASS_BRIDGE_PCI ) {
|
||||
pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT0_IRQ );
|
||||
line = 0xff;
|
||||
} else
|
||||
line = SLOT0_IRQ;
|
||||
break;
|
||||
case 0x10:
|
||||
/* mvBB: Slot1 */
|
||||
pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
|
||||
if ( class == PCI_CLASS_BRIDGE_PCI ) {
|
||||
pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT1_IRQ );
|
||||
line = 0xff;
|
||||
} else
|
||||
line = SLOT1_IRQ;
|
||||
break;
|
||||
default:
|
||||
printf("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV(dev) );
|
||||
line = 0xff;
|
||||
break;
|
||||
}
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line );
|
||||
}
|
||||
}
|
||||
|
||||
struct pci_controller hose = {
|
||||
fixup_irq: pci_mvblue_fixup_irq
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc824x_init(&hose);
|
||||
}
|
||||
#endif
|
||||
133
board/mvblue/u-boot.lds
Normal file
133
board/mvblue/u-boot.lds
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc824x/start.o (.text)
|
||||
lib_ppc/board.o (.text)
|
||||
lib_ppc/ppcstring.o (.text)
|
||||
lib_generic/vsprintf.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -8,4 +8,4 @@
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xa1fe0000
|
||||
#TEXT_BASE = 0xa1001000
|
||||
#TEXT_BASE = 0xa1001000
|
||||
|
||||
@ -67,6 +67,9 @@
|
||||
* 17-Jun-02 stefan.roese@esd-electronics.com
|
||||
* - MAL error debug printf 'M' removed (rx de interrupt may
|
||||
* occur upon many incoming packets with only 4 rx buffers).
|
||||
* 21-Nov-03 pavel.bartusek@sysgo.com
|
||||
* - set ZMII bridge speed on 440
|
||||
*
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
#include <common.h>
|
||||
@ -414,6 +417,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
|
||||
|
||||
out32 (EMAC_M1, mode_reg);
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
/* set speed in the ZMII bridge */
|
||||
if (speed == _100BASET)
|
||||
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
|
||||
else
|
||||
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
|
||||
#endif
|
||||
|
||||
/* Enable broadcast and indvidual address */
|
||||
out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
|
||||
/*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
|
||||
|
||||
@ -84,10 +84,6 @@ typedef struct { volatile u32 offset[4096]; } __regbase;
|
||||
# define __REG(x) io_p2v(x)
|
||||
# define __PREG(x) io_v2p(x)
|
||||
|
||||
#endif
|
||||
#endif /* UBOOT_REG_FIX */
|
||||
|
||||
#ifdef UBOOT_REG_FIX
|
||||
# undef io_p2v
|
||||
# undef __REG
|
||||
# ifndef __ASSEMBLY__
|
||||
@ -96,6 +92,7 @@ typedef struct { volatile u32 offset[4096]; } __regbase;
|
||||
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
|
||||
# else
|
||||
# define __REG(x) (x)
|
||||
# endif
|
||||
#endif /* UBOOT_REG_FIX */
|
||||
|
||||
#include "pxa-regs.h"
|
||||
|
||||
325
include/configs/MVBLUE.h
Normal file
325
include/configs/MVBLUE.h
Normal file
@ -0,0 +1,325 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define MV_VERSION "v0.2.0"
|
||||
|
||||
/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
|
||||
#define ERR_NONE 0
|
||||
#define ERR_ENV 1
|
||||
#define ERR_BOOTM_BADMAGIC 2
|
||||
#define ERR_BOOTM_BADCRC 3
|
||||
#define ERR_BOOTM_GUNZIP 4
|
||||
#define ERR_BOOTP_TIMEOUT 5
|
||||
#define ERR_DHCP 6
|
||||
#define ERR_TFTP 7
|
||||
#define ERR_NOLAN 8
|
||||
#define ERR_LANDRV 9
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1
|
||||
#define MVBLUE_BOARD_BOX 1
|
||||
#define MVBLUE_BOARD_LYNX 2
|
||||
|
||||
#if 0
|
||||
#define ERR_LED(code) do { if (code) \
|
||||
*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
|
||||
else \
|
||||
*(volatile char *)(0xff000003) = ( 1 ); \
|
||||
} while(0)
|
||||
#else
|
||||
#define ERR_LED(code)
|
||||
#endif
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#define CONFIG_MPC824X 1
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_MVBLUE 1
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOT_RETRY_TIME -1
|
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n\0"
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "s\0"
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
#define CONFIG_RESET_TO_RETRY 60
|
||||
|
||||
#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \
|
||||
CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \
|
||||
CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN )
|
||||
|
||||
|
||||
#define CONFIG_BOOTP_MASK ( 0xffffffff )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_MAXARGS 16 /* Max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run nfsboot"
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console_nr=0\0" \
|
||||
"dhcp_client_id=mvBOX-XP\0" \
|
||||
"dhcp_vendor-class-identifier=mvBOX\0" \
|
||||
"adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
|
||||
"flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
|
||||
"safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
|
||||
"hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
|
||||
"addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \
|
||||
"mv_version=" MV_VERSION "\0" \
|
||||
"bootretry=30\0"
|
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
|
||||
#define CONFIG_TULIP
|
||||
#define CONFIG_TULIP_FIX_DAVICOM 1
|
||||
#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
|
||||
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
|
||||
#define CFG_FLASH_BASE 0xFFF00000
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100
|
||||
#define CFG_EUMB_ADDR 0xFC000000
|
||||
|
||||
#define CFG_MONITOR_LEN 0x00100000
|
||||
#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
|
||||
|
||||
/* Maximum amount of RAM. */
|
||||
#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
|
||||
|
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
|
||||
#undef CFG_RAMBOOT
|
||||
#else
|
||||
#define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_ISA_IO 0xFE000000
|
||||
|
||||
/*
|
||||
* serial configuration
|
||||
*/
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_INIT_RAM_END 0x1000
|
||||
#define CFG_GBL_DATA_SIZE 128
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
* For the detail description refer to the MPC8240 user's manual.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000
|
||||
#define CFG_HZ 10000
|
||||
|
||||
/* Bit-field values for MCCR1. */
|
||||
#define CFG_ROMNAL 7
|
||||
#define CFG_ROMFAL 11
|
||||
|
||||
/* Bit-field values for MCCR2. */
|
||||
#define CFG_TSWAIT 0x5
|
||||
#define CFG_REFINT 430
|
||||
|
||||
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
|
||||
#define CFG_BSTOPRE 121
|
||||
|
||||
/* Bit-field values for MCCR3. */
|
||||
#define CFG_REFREC 8
|
||||
|
||||
/* Bit-field values for MCCR4. */
|
||||
#define CFG_PRETOACT 3
|
||||
#define CFG_ACTTOPRE 5
|
||||
#define CFG_ACTORW 3
|
||||
#define CFG_SDMODE_CAS_LAT 3
|
||||
#define CFG_REGISTERD_TYPE_BUFFER 1
|
||||
#define CFG_EXTROM 1
|
||||
#define CFG_REGDIMM 0
|
||||
#define CFG_DBUS_SIZE2 1
|
||||
#define CFG_SDMODE_WRAP 0
|
||||
|
||||
#define CFG_PGMAX 0x32
|
||||
#define CFG_SDRAM_DSCD 0x20
|
||||
|
||||
/* Memory bank settings.
|
||||
* Only bits 20-29 are actually used from these vales to set the
|
||||
* start/end addresses. The upper two bits will always be 0, and the lower
|
||||
* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
|
||||
* address. Refer to the MPC8240 book.
|
||||
*/
|
||||
|
||||
#define CFG_BANK0_START 0x00000000
|
||||
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
|
||||
#define CFG_BANK0_ENABLE 1
|
||||
#define CFG_BANK1_START 0x3ff00000
|
||||
#define CFG_BANK1_END 0x3fffffff
|
||||
#define CFG_BANK1_ENABLE 0
|
||||
#define CFG_BANK2_START 0x3ff00000
|
||||
#define CFG_BANK2_END 0x3fffffff
|
||||
#define CFG_BANK2_ENABLE 0
|
||||
#define CFG_BANK3_START 0x3ff00000
|
||||
#define CFG_BANK3_END 0x3fffffff
|
||||
#define CFG_BANK3_ENABLE 0
|
||||
#define CFG_BANK4_START 0x3ff00000
|
||||
#define CFG_BANK4_END 0x3fffffff
|
||||
#define CFG_BANK4_ENABLE 0
|
||||
#define CFG_BANK5_START 0x3ff00000
|
||||
#define CFG_BANK5_END 0x3fffffff
|
||||
#define CFG_BANK5_ENABLE 0
|
||||
#define CFG_BANK6_START 0x3ff00000
|
||||
#define CFG_BANK6_END 0x3fffffff
|
||||
#define CFG_BANK6_ENABLE 0
|
||||
#define CFG_BANK7_START 0x3ff00000
|
||||
#define CFG_BANK7_END 0x3fffffff
|
||||
#define CFG_BANK7_ENABLE 0
|
||||
|
||||
#define CFG_ODCR 0xff
|
||||
|
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
|
||||
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
#define CFG_DBAT2L CFG_IBAT2L
|
||||
#define CFG_DBAT2U CFG_IBAT2U
|
||||
#define CFG_DBAT3L CFG_IBAT3L
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#undef CFG_FLASH_PROTECTION
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||
#define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 12000
|
||||
#define CFG_FLASH_WRITE_TOUT 1000
|
||||
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
|
||||
#define CFG_ENV_OFFSET 0x00010000
|
||||
#define CFG_ENV_SIZE 0x00010000
|
||||
#define CFG_ENV_SECT_SIZE 0x00010000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -1101,6 +1101,9 @@
|
||||
|
||||
#define PCI_VENDOR_ID_ROCKWELL 0x127A
|
||||
|
||||
#define PCI_VENDOR_ID_DAVICOM 0x1282
|
||||
#define PCI_DEVICE_ID_DAVICOM_DM9102A 0x9102
|
||||
|
||||
#define PCI_VENDOR_ID_ITE 0x1283
|
||||
#define PCI_DEVICE_ID_ITE_IT8172G 0x8172
|
||||
#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
|
||||
@ -1540,3 +1543,4 @@
|
||||
#define PCI_DEVICE_ID_SMI_710 0x0710
|
||||
#define PCI_DEVICE_ID_SMI_712 0x0712
|
||||
#define PCI_DEVICE_ID_SMI_810 0x0810
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user