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Add SPI support to mx51evk board
The patch adds SPI devices to the mx51evk board. The MC13892 chip (PMIC) is supported. Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
parent
d3588a55d4
commit
b4377e12e9
@ -27,9 +27,12 @@
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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#include "mx51evk.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -147,6 +150,130 @@ static void setup_iomux_fec(void)
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mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
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}
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#ifdef CONFIG_MXC_SPI
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static void setup_iomux_spi(void)
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{
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/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
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/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
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/* de-select SS1 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
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/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
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/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
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/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
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}
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#endif
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static void power_init(void)
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{
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unsigned int val;
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unsigned int reg;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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/* Write needed to Power Gate 2 register */
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val = pmic_reg_read(REG_POWER_MISC);
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val &= ~PWGT2SPIEN;
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pmic_reg_write(REG_POWER_MISC, val);
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/* Write needed to update Charger 0 */
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pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
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ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
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OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
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/* power up the system first */
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pmic_reg_write(REG_POWER_MISC, PWUP);
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/* Set core voltage to 1.1V */
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val = pmic_reg_read(REG_SW_0);
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val = (val & (~0x1F)) | 0x14;
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pmic_reg_write(REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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val = pmic_reg_read(REG_SW_1);
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val = (val & (~0x1F)) | 0x1A;
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pmic_reg_write(REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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val = pmic_reg_read(REG_SW_2);
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val = (val & (~0x1F)) | 0x1A;
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pmic_reg_write(REG_SW_2, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, &mxc_ccm->cacrr);
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/* Set switchers in Auto in NORMAL mode & STANDBY mode */
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/* Setup the switcher mode for SW1 & SW2*/
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val = pmic_reg_read(REG_SW_4);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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val = pmic_reg_read(REG_SW_5);
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val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
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(SWMODE_MASK << SWMODE4_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
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pmic_reg_write(REG_SW_5, val);
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
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val = pmic_reg_read(REG_SETTING_0);
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val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
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val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
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pmic_reg_write(REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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val = pmic_reg_read(REG_SETTING_1);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
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pmic_reg_write(REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(REG_MODE_1, val);
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udelay(200);
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reg = readl(GPIO2_BASE_ADDR + 0x0);
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reg &= ~0x4000; /* Lower reset line */
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writel(reg, GPIO2_BASE_ADDR + 0x0);
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reg = readl(GPIO2_BASE_ADDR + 0x4);
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reg |= 0x4000; /* configure GPIO lines as output */
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writel(reg, GPIO2_BASE_ADDR + 0x4);
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/* Reset the ethernet controller over GPIO */
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writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(REG_MODE_1, val);
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udelay(500);
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reg = readl(GPIO2_BASE_ADDR + 0x0);
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reg |= 0x4000;
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writel(reg, GPIO2_BASE_ADDR + 0x0);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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@ -284,9 +411,21 @@ int board_init(void)
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setup_iomux_uart();
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setup_iomux_fec();
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return 0;
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}
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#ifdef BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_MXC_SPI
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setup_iomux_spi();
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power_init();
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#endif
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Board: MX51EVK ");
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@ -54,12 +54,27 @@
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/* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define BOARD_LATE_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_SYS_MX51_UART1
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/*
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* SPI Configs
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* */
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#define CONFIG_CMD_SPI
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#define CONFIG_MXC_SPI
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 0
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 2500000
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#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH)
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/*
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* MMC Configs
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* */
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