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imx: mx6q DDR3 init: Fix MR0.PPD
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x0000803B
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DATA 4 0x021b001c 0x00428031
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DATA 4 0x021b001c 0x00428039
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DATA 4 0x021b001c 0x09408030
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DATA 4 0x021b001c 0x09408038
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DATA 4 0x021b001c 0x19408030
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DATA 4 0x021b001c 0x19408038
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DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b001c 0x04008048
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