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imx: mx6q DDR3 init: Fix MR0.PPD

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MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau 2013-01-30 11:19:17 +00:00 committed by Stefano Babic
parent 1791b1f97f
commit b42b5b7a24
1 changed files with 2 additions and 2 deletions
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4
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
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@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039 DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x09408030 DATA 4 0x021b001c 0x19408030
DATA 4 0x021b001c 0x09408038 DATA 4 0x021b001c 0x19408038
DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048 DATA 4 0x021b001c 0x04008048