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stm32mp1: ram: remove tuning support

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Remove the DDR interactive command tuning, as the support of a predefined
DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A
and the result of this tuning will be never used.

Moreover this SW tuning procedure can failed on some hardware
configuration (to many BIST errors and no convergence); it will be no
more supported in the next delivery of the DDR utilities included in
the CubeMX tool of STMicroelectronics.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay 2021-11-15 15:32:30 +01:00 committed by Patrice Chotard
parent 9819fe345c
commit b3c29dc9e5
7 changed files with 7 additions and 1636 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/ram/stm32mp1/Makefile
View File

@ -8,7 +8,6 @@ obj-y += stm32mp1_ddr.o
obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o
obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o
obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o
ifneq ($(DDR_INTERACTIVE),)
CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y

8
drivers/ram/stm32mp1/stm32mp1_ddr.c
View File

@ -557,7 +557,7 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
(u32)&phy->pgsr, pgsr, ret);
}
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
@ -626,7 +626,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode)
log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
{
start_sw_done(ctl);
/* quasi-dynamic register update*/
@ -637,8 +637,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
wait_sw_done_ack(ctl);
}
void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
u32 rfshctl3, u32 pwrctl)
static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
u32 rfshctl3, u32 pwrctl)
{
start_sw_done(ctl);
if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))

5
drivers/ram/stm32mp1/stm32mp1_ddr.h
View File

@ -157,11 +157,6 @@ struct stm32mp1_ddr_config {
};
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
u32 rfshctl3,
u32 pwrctl);
void stm32mp1_ddr_init(
struct ddr_info *priv,

64
drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
View File

@ -6,8 +6,9 @@
#ifndef _RAM_STM32MP1_DDR_REGS_H
#define _RAM_STM32MP1_DDR_REGS_H
/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
#include <linux/bitops.h>
/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
struct stm32mp1_ddrctl {
u32 mstr ; /* 0x0 Master*/
u32 stat; /* 0x4 Operating Mode Status*/
@ -275,25 +276,6 @@ struct stm32mp1_ddrphy {
#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
#define DDRCTRL_DBG1_DIS_HIF BIT(1)
#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
#define DDRCTRL_SWCTL_SW_DONE BIT(0)
#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
@ -312,11 +294,6 @@ struct stm32mp1_ddrphy {
#define DDRPHYC_PIR_RVTRN BIT(8)
#define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30)
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
#define DDRPHYC_PGCR_DFTCMP BIT(2)
#define DDRPHYC_PGCR_PDDISDX BIT(24)
#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
#define DDRPHYC_PGSR_IDONE BIT(0)
#define DDRPHYC_PGSR_DTERR BIT(5)
@ -325,43 +302,6 @@ struct stm32mp1_ddrphy {
#define DDRPHYC_PGSR_RVERR BIT(8)
#define DDRPHYC_PGSR_RVEIRR BIT(9)
#define DDRPHYC_DLLGCR_BPS200 BIT(23)
#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
#define DDRPHYC_DXNGCR_DXEN BIT(0)
#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit))
#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0)
#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0)
#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2)
#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20)
#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20
#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23)
#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23
#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0)
#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0
#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12)
#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12
#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19)
#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19
#define DDRPHYC_BISTGSR_BDDONE BIT(0)
#define DDRPHYC_BISTGSR_BDXERR BIT(2)
#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16
/* PWR registers */
#define PWR_CR3 0x00C
#define PWR_CR3_DDRSRDIS BIT(11)

22
drivers/ram/stm32mp1/stm32mp1_interactive.c
View File

@ -32,7 +32,6 @@ enum ddr_command {
DDR_CMD_NEXT,
DDR_CMD_GO,
DDR_CMD_TEST,
DDR_CMD_TUNING,
DDR_CMD_UNKNOWN,
};
@ -59,9 +58,6 @@ enum ddr_command stm32mp1_get_command(char *cmd, int argc)
[DDR_CMD_GO] = "go",
#ifdef CONFIG_STM32MP1_DDR_TESTS
[DDR_CMD_TEST] = "test",
#endif
#ifdef CONFIG_STM32MP1_DDR_TUNING
[DDR_CMD_TUNING] = "tuning",
#endif
};
/* min and max number of argument */
@ -78,9 +74,6 @@ enum ddr_command stm32mp1_get_command(char *cmd, int argc)
[DDR_CMD_GO] = { 0, 0 },
#ifdef CONFIG_STM32MP1_DDR_TESTS
[DDR_CMD_TEST] = { 0, 255 },
#endif
#ifdef CONFIG_STM32MP1_DDR_TUNING
[DDR_CMD_TUNING] = { 0, 255 },
#endif
};
int i;
@ -125,9 +118,6 @@ static void stm32mp1_do_usage(void)
"reset reboots machine\n"
#ifdef CONFIG_STM32MP1_DDR_TESTS
"test [help] | <n> [...] lists (with help) or executes test <n>\n"
#endif
#ifdef CONFIG_STM32MP1_DDR_TUNING
"tuning [help] | <n> [...] lists (with help) or execute tuning <n>\n"
#endif
"\nwith for [type|reg]:\n"
" all registers if absent\n"
@ -311,7 +301,7 @@ end:
return step;
}
#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
#if defined(CONFIG_STM32MP1_DDR_TESTS)
static const char * const s_result[] = {
[TEST_PASSED] = "Pass",
[TEST_FAILED] = "Failed",
@ -468,16 +458,6 @@ bool stm32mp1_ddr_interactive(void *priv,
stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
break;
#endif
#ifdef CONFIG_STM32MP1_DDR_TUNING
case DDR_CMD_TUNING:
if (!stm32mp1_check_step(step, STEP_DDR_READY))
continue;
stm32mp1_ddr_subcmd(priv, argc, argv,
tuning, tuning_nb);
break;
#endif
default:
break;
}

3
drivers/ram/stm32mp1/stm32mp1_tests.h
View File

@ -28,7 +28,4 @@ struct test_desc {
extern const struct test_desc test[];
extern const int test_nb;
extern const struct test_desc tuning[];
extern const int tuning_nb;
#endif

1540
drivers/ram/stm32mp1/stm32mp1_tuning.c
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