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ARM: davinci: Move CONFIG_SYS_DA850_DDR_INIT to Kconfig
Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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@ -8,11 +8,13 @@ config TARGET_IPAM390
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bool "IPAM390 board"
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select SUPPORT_SPL
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select SYS_DA850_PLL_INIT
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select SYS_DA850_DDR_INIT
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config TARGET_DA850EVM
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bool "DA850 EVM board"
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select SUPPORT_SPL
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select SYS_DA850_PLL_INIT
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select SYS_DA850_DDR_INIT
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config TARGET_EA20
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bool "EA20 board"
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@ -24,10 +26,12 @@ config TARGET_OMAPL138_LCDK
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config TARGET_CALIMAIN
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bool "Calimain board"
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select SYS_DA850_PLL_INIT
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select SYS_DA850_DDR_INIT
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config TARGET_LEGOEV3
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bool "LEGO MINDSTORMS EV3"
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select SYS_DA850_PLL_INIT
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select SYS_DA850_DDR_INIT
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endchoice
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@ -37,6 +41,9 @@ config SYS_SOC
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config SYS_DA850_PLL_INIT
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bool
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config SYS_DA850_DDR_INIT
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bool
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source "board/Barix/ipam390/Kconfig"
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source "board/davinci/da8xxevm/Kconfig"
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source "board/davinci/ea20/Kconfig"
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@ -32,7 +32,6 @@
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#define CONFIG_DA850_LOWLEVEL
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#define CONFIG_SYS_DA850_DDR_INIT
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_HW_WATCHDOG
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@ -31,7 +31,6 @@
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_DA850_DDR_INIT
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#ifdef CONFIG_DIRECT_NOR_BOOT
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#define CONFIG_ARCH_CPU_INIT
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@ -32,7 +32,6 @@
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_DA850_DDR_INIT
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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/*
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@ -26,7 +26,6 @@
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_DA850_DDR_INIT
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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@ -4690,7 +4690,6 @@ CONFIG_SYS_DA850_DDR2_SDBCR2
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CONFIG_SYS_DA850_DDR2_SDRCR
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CONFIG_SYS_DA850_DDR2_SDTIMR
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CONFIG_SYS_DA850_DDR2_SDTIMR2
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CONFIG_SYS_DA850_DDR_INIT
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CONFIG_SYS_DA850_PLL0_PLLDIV1
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CONFIG_SYS_DA850_PLL0_PLLDIV2
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CONFIG_SYS_DA850_PLL0_PLLDIV3
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