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Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
8993e54b6f
commit
b1b54e3520
46
CHANGELOG
46
CHANGELOG
@ -1,3 +1,49 @@
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commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Fri Jul 27 14:43:59 2007 +0200
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[ADS5121] Support for the ADS5121 board
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The following MPC5121e subsystems are supported:
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- low-level CPU init
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- NOR Boot Flash (common CFI driver)
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- DDR SDRAM
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- FEC
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- I2C
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- Watchdog
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Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
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commit 1863cfb7b100ba0ee3401799457a01dc058745f8
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Fri Jul 27 14:22:04 2007 +0200
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[PPC] Remove unused MSR_USER definition
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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commit cc3023b9f95d7ac959a764471a65001062aecf41
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Author: Rafal Jaworowski <raj@semihalf.com>
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Date: Thu Jul 19 17:12:28 2007 +0200
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Fix breakage of 8xx boards from recent commit.
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This patch fixes the negative consequences for 8xx of the recent
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"ppc4xx: Clean up 440 exceptions handling" commit.
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Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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commit 3a6cab844cf74f76639d795e0be8717e02c86af7
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Author: Wolfgang Denk <wd@denx.de>
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Date: Sat Jul 14 22:51:02 2007 +0200
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Update CHANGELOG
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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commit 011595307731a7a67a7445d107c279d031e8ab97
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Author: Heiko Schocher <hs@pollux.denx.de>
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Date: Sat Jul 14 01:06:58 2007 +0200
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@ -114,7 +114,7 @@ long int fixed_sdram (void)
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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*/
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i = im->sysconf.ddrlaw.ar;
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__asm__ __volatile__ ("isync");
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@ -183,6 +183,6 @@ int checkboard (void)
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uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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brd_rev, cpld_rev);
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return 0;
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}
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@ -76,7 +76,7 @@ void cpu_init_f (volatile immap_t * im)
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*
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* NOTICE: TB needs to be enabled as early as possible in order to
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* have udelay() working; if not enabled, usually leads to a hang, like
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* during FLASH chip identification etc.
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* during FLASH chip identification etc.
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*/
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im->sysconf.spcr |= SPCR_TBEN;
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}
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@ -77,20 +77,20 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
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* Trasmit BDs init
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*/
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for (ix = 0; ix < FEC_TBD_NUM; ix++) {
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fec->bdBase->tbd[ix].status = 0;
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}
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fec->bdBase->tbd[ix].status = 0;
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}
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/*
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* Have the last TBD to close the ring
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*/
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fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Have the last TBD to close the ring
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*/
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fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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return 0;
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}
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@ -238,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
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fec->eth->r_cntrl = 0x05ee000c;
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/* Half-duplex, heartbeat disabled */
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fec->eth->x_cntrl = 0x00000000;
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fec->eth->x_cntrl = 0x00000000;
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/* Enable MIB counters */
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fec->eth->mib_control = 0x0;
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@ -260,7 +260,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
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/* Initilize addresses and status words of BDs */
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mpc512x_fec_bd_init (fec);
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/* Descriptor polling active */
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/* Descriptor polling active */
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fec->eth->r_des_active = 0x01000000;
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#if (DEBUG & 0x1)
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@ -296,7 +296,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
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fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
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/*
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* Reset PHY, then delay 300ns
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@ -312,7 +312,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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printf ("Forcing 10 Mbps ethernet link... ");
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#endif
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miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
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miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
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timeout = 20;
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@ -346,7 +346,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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#if (DEBUG & 0x2)
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printf ("done.\n");
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#endif
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} else { /* MII100 */
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} else { /* MII100 */
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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@ -487,7 +487,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
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pTbd->dataPointer = (uint32)eth_data;
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pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
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fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
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/* Activate transmit Buffer Descriptor polling */
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fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
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@ -529,7 +529,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
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#if (DEBUG & 0x8)
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printf( "-" );
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#endif
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/*
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* Check if any critical events have happened
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*/
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@ -555,10 +555,10 @@ static int mpc512x_fec_recv (struct eth_device *dev)
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}
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if (!(pRbd->status & FEC_RBD_EMPTY)) {
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if ((pRbd->status & FEC_RBD_LAST) &&
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if ((pRbd->status & FEC_RBD_LAST) &&
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!(pRbd->status & FEC_RBD_ERR) &&
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((pRbd->dataLength - 4) > 14)) {
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/*
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* Get buffer size
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*/
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@ -635,7 +635,7 @@ int mpc512x_fec_initialize (bd_t * bis)
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* Initialize I\O pins
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*/
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reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
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for (i = 0; i < 15; i++)
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reg[i] = IOCTRL_MUX_FEC | 0x00000001;
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@ -645,13 +645,13 @@ int mpc512x_fec_initialize (bd_t * bis)
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/* Clean up space FEC's MIB and FIFO RAM ...*/
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memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
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/*
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/*
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* Malloc space for BDs (must be quad word-aligned)
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* this pointer is lost, so cannot be freed
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* this pointer is lost, so cannot be freed
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*/
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bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
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fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
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fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
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memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
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/*
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@ -28,7 +28,7 @@ typedef struct ethernet_register_set {
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volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
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volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
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volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
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volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
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volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
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@ -42,10 +42,10 @@ typedef struct ethernet_register_set {
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volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
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volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
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volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
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volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
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volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
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volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
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volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
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volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
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@ -63,7 +63,7 @@ typedef struct ethernet_register_set {
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volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
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volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
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volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
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volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
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volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
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volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
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@ -79,14 +79,14 @@ int get_clocks (void)
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spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
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spll = ref_clk * spmf_mult[spmf];
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sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
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sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
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csb_clk = sys_clk / 2;
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cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
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core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
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cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
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core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
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ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
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if (ips_div != 0) {
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@ -208,8 +208,8 @@ boot_cold:
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*/
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/* Boot CS/CS0 window range */
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lis r3, CFG_IMMR@h
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ori r3, r3, CFG_IMMR@l
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lis r3, CFG_IMMR@h
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ori r3, r3, CFG_IMMR@l
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lis r4, START_REG(CFG_FLASH_BASE)
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ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
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@ -222,11 +222,11 @@ boot_cold:
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lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
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stw r4, SRAMBAR(r3)
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/*
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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*/
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lwz r4, SRAMBAR(r3)
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isync
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@ -235,11 +235,11 @@ boot_cold:
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* config register so no params can be set for it
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*/
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lis r3, (CFG_IMMR + LPC_OFFSET)@h
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ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
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ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
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lis r4, CFG_CS0_CFG@h
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ori r4, r4, CFG_CS0_CFG@l
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stw r4, CS0_CONFIG(r3)
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lis r4, CFG_CS0_CFG@h
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ori r4, r4, CFG_CS0_CFG@l
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stw r4, CS0_CONFIG(r3)
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/* Master enable all CS's */
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lis r4, CS_CTRL_ME@h
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@ -65,48 +65,49 @@
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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/* DDR Controller Configuration
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SYS_CFG:
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[31:31] MDDRC Soft Reset: Diabled
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[30:30] DRAM CKE pin: Enabled
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[29:29] DRAM CLK: Enabled
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[28:28] Command Mode: Enabled (For initialization only)
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[27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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[24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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[20:19] Read Test: DON'T USE
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[18:18] Self Refresh: Enabled
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[17:17] 16bit Mode: Disabled
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[16:13] Ready Delay: 2
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[12:12] Half DQS Delay: Disabled
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[11:11] Quarter DQS Delay: Disabled
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[10:08] Write Delay: 2
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[07:07] Early ODT: Disabled
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[06:06] On DIE Termination: Disabled
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[05:05] FIFO Overflow Clear: DON'T USE here
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[04:04] FIFO Underflow Clear: DON'T USE here
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[03:03] FIFO Overflow Pending: DON'T USE here
|
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[02:02] FIFO Underlfow Pending: DON'T USE here
|
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[01:01] FIFO Overlfow Enabled: Enabled
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[00:00] FIFO Underflow Enabled: Enabled
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TIME_CFG0
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[31:16] DRAM Refresh Time: 0 CSB clocks
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[15:8] DRAM Command Time: 0 CSB clocks
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[07:00] DRAM Precharge Time: 0 CSB clocks
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TIME_CFG1
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[31:26] DRAM tRFC:
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[25:21] DRAM tWR1:
|
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[20:17] DRAM tWRT1:
|
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[16:11] DRAM tDRR:
|
||||
[10:05] DRAM tRC:
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[04:00] DRAM tRAS:
|
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TIME_CFG2
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[31:28] DRAM tRCD:
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[27:23] DRAM tFAW:
|
||||
[22:19] DRAM tRTW1:
|
||||
[18:15] DRAM tCCD:
|
||||
[14:10] DRAM tRTP:
|
||||
[09:05] DRAM tRP:
|
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[04:00] DRAM tRPA */
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
|
||||
* [30:30] DRAM CKE pin: Enabled
|
||||
* [29:29] DRAM CLK: Enabled
|
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* [28:28] Command Mode: Enabled (For initialization only)
|
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
|
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
|
||||
* [20:19] Read Test: DON'T USE
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||||
* [18:18] Self Refresh: Enabled
|
||||
* [17:17] 16bit Mode: Disabled
|
||||
* [16:13] Ready Delay: 2
|
||||
* [12:12] Half DQS Delay: Disabled
|
||||
* [11:11] Quarter DQS Delay: Disabled
|
||||
* [10:08] Write Delay: 2
|
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* [07:07] Early ODT: Disabled
|
||||
* [06:06] On DIE Termination: Disabled
|
||||
* [05:05] FIFO Overflow Clear: DON'T USE here
|
||||
* [04:04] FIFO Underflow Clear: DON'T USE here
|
||||
* [03:03] FIFO Overflow Pending: DON'T USE here
|
||||
* [02:02] FIFO Underlfow Pending: DON'T USE here
|
||||
* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
|
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
|
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* [15:8] DRAM Command Time: 0 CSB clocks
|
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* [07:00] DRAM Precharge Time: 0 CSB clocks
|
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* TIME_CFG1
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* [31:26] DRAM tRFC:
|
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* [25:21] DRAM tWR1:
|
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
|
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* [10:05] DRAM tRC:
|
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* [04:00] DRAM tRAS:
|
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* TIME_CFG2
|
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* [31:28] DRAM tRCD:
|
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* [27:23] DRAM tFAW:
|
||||
* [22:19] DRAM tRTW1:
|
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* [18:15] DRAM tCCD:
|
||||
* [14:10] DRAM tRTP:
|
||||
* [09:05] DRAM tRP:
|
||||
* [04:00] DRAM tRPA
|
||||
*/
|
||||
|
||||
#define CFG_MDDRC_SYS_CFG 0xF8604200
|
||||
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
|
||||
@ -276,7 +277,7 @@ SYS_CFG:
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
| CFG_CMD_NET \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_I2C)
|
||||
#endif
|
||||
|
||||
@ -384,26 +385,26 @@ SYS_CFG:
|
||||
"bootm\0" \
|
||||
"load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \
|
||||
"update=protect off fff00000 fff3ffff; " \
|
||||
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
|
||||
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
|
||||
@ -60,7 +60,7 @@
|
||||
|
||||
#define CS_CTRL 0x00020
|
||||
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
|
||||
#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
|
||||
#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
|
||||
|
||||
/* SPRIDR - System Part and Revision ID Register
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user