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arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask

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Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan 2018-08-16 02:20:17 +08:00 committed by Marek Vasut
parent d81b5da3fe
commit b0c0a715f9
1 changed files with 3 additions and 3 deletions
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6
arch/arm/mach-socfpga/include/mach/system_manager_s10.h
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@ -146,9 +146,9 @@ struct socfpga_system_manager {
#define SYSMGR_FPGAINTF_SDMMC BIT(8)
#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0