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https://github.com/u-boot/u-boot.git
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mtd: remove SPEAr flash driver st_smi
Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit570c3dcfc1("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes:570c3dcfc1("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Patrick Delaunay
Tom Rini
parent
cff383caa3
commit
b071431d52
@ -12,7 +12,6 @@ mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
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mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
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mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
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mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o
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mtd-$(CONFIG_ST_SMI) += st_smi.o
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mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o
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mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
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mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
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@ -1,565 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <flash.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mtd/st_smi.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_MTD_NOR_FLASH)
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static struct smi_regs *const smicntl =
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(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
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static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
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CONFIG_SYS_FLASH_ADDR_BASE;
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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/* data structure to maintain flash ids from different vendors */
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struct flash_device {
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char *name;
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u8 erase_cmd;
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u32 device_id;
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u32 pagesize;
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unsigned long sectorsize;
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unsigned long size_in_bytes;
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};
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#define FLASH_ID(n, es, id, psize, ssize, size) \
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{ \
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.name = n, \
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.erase_cmd = es, \
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.device_id = id, \
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.pagesize = psize, \
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.sectorsize = ssize, \
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.size_in_bytes = size \
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}
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/*
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* List of supported flash devices.
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* Currently the erase_cmd field is not used in this driver.
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*/
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static struct flash_device flash_devices[] = {
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FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
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FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
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FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
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FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
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FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
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FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
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FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
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FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
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FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
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FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
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FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
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FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
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FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
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FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
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FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
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FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
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FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
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FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
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FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
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FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
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FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
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FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
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FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
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FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
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FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
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FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
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FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
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FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
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FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
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FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000),
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};
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/*
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* smi_wait_xfer_finish - Wait until TFF is set in status register
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* @timeout: timeout in milliseconds
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*
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* Wait until TFF is set in status register
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*/
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static int smi_wait_xfer_finish(int timeout)
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{
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ulong start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (readl(&smicntl->smi_sr) & TFF)
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return 0;
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/* Try after 10 ms */
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udelay(10);
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};
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return -1;
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}
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/*
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* smi_read_id - Read flash id
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* @info: flash_info structure pointer
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* @banknum: bank number
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*
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* Read the flash id present at bank #banknum
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*/
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static unsigned int smi_read_id(flash_info_t *info, int banknum)
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{
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unsigned int value;
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writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
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writel(READ_ID, &smicntl->smi_tr);
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writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
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&smicntl->smi_cr2);
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if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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return -EIO;
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value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
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writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
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writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
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return value;
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}
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/*
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* flash_get_size - Detect the SMI flash by reading the ID.
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* @base: Base address of the flash area bank #banknum
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* @banknum: Bank number
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*
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* Detect the SMI flash by reading the ID. Initializes the flash_info structure
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* with size, sector count etc.
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*/
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static ulong flash_get_size(ulong base, int banknum)
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{
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flash_info_t *info = &flash_info[banknum];
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int value;
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int i;
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value = smi_read_id(info, banknum);
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if (value < 0) {
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printf("Flash id could not be read\n");
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return 0;
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}
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/* Matches chip-id to entire list of 'serial-nor flash' ids */
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for (i = 0; i < ARRAY_SIZE(flash_devices); i++) {
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if (flash_devices[i].device_id == value) {
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info->size = flash_devices[i].size_in_bytes;
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info->flash_id = value;
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info->start[0] = base;
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info->sector_count =
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info->size/flash_devices[i].sectorsize;
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return info->size;
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}
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}
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return 0;
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}
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/*
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* smi_read_sr - Read status register of SMI
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* @bank: bank number
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*
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* This routine will get the status register of the flash chip present at the
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* given bank
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*/
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static int smi_read_sr(int bank)
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{
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u32 ctrlreg1, val;
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/* store the CTRL REG1 state */
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ctrlreg1 = readl(&smicntl->smi_cr1);
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/* Program SMI in HW Mode */
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writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
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&smicntl->smi_cr1);
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/* Performing a RSR instruction in HW mode */
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writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
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if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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return -1;
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val = readl(&smicntl->smi_sr);
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/* Restore the CTRL REG1 state */
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writel(ctrlreg1, &smicntl->smi_cr1);
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return val;
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}
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/*
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* smi_wait_till_ready - Wait till last operation is over.
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* @bank: bank number shifted.
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* @timeout: timeout in milliseconds.
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*
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* This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
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* The routine checks for #timeout loops, each at interval of 1 milli-second.
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* If successful the routine returns 0.
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*/
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static int smi_wait_till_ready(int bank, int timeout)
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{
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int sr;
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ulong start = get_timer(0);
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/* One chip guarantees max 5 msec wait here after page writes,
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but potentially three seconds (!) after page erase. */
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while (get_timer(start) < timeout) {
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sr = smi_read_sr(bank);
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if ((sr >= 0) && (!(sr & WIP_BIT)))
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return 0;
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/* Try again after 10 usec */
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udelay(10);
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} while (timeout--);
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printf("SMI controller is still in wait, timeout=%d\n", timeout);
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return -EIO;
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}
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/*
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* smi_write_enable - Enable the flash to do write operation
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* @bank: bank number
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*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static int smi_write_enable(int bank)
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{
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u32 ctrlreg1;
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u32 start;
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int timeout = WMODE_TOUT;
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int sr;
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/* Store the CTRL REG1 state */
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ctrlreg1 = readl(&smicntl->smi_cr1);
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/* Program SMI in H/W Mode */
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writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
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/* Give the Flash, Write Enable command */
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writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
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if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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return -1;
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/* Restore the CTRL REG1 state */
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writel(ctrlreg1, &smicntl->smi_cr1);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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sr = smi_read_sr(bank);
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if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT))))
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return 0;
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/* Try again after 10 usec */
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udelay(10);
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};
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return -1;
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}
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/*
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* smi_init - SMI initialization routine
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*
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* SMI initialization routine. Sets SMI control register1.
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*/
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void smi_init(void)
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{
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/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
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writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
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&smicntl->smi_cr1);
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}
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/*
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* smi_sector_erase - Erase flash sector
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* @info: flash_info structure pointer
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* @sector: sector number
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*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static int smi_sector_erase(flash_info_t *info, unsigned int sector)
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{
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int bank;
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unsigned int sect_add;
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unsigned int instruction;
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switch (info->start[0]) {
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case SMIBANK0_BASE:
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bank = BANK0;
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break;
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case SMIBANK1_BASE:
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bank = BANK1;
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break;
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case SMIBANK2_BASE:
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bank = BANK2;
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break;
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case SMIBANK3_BASE:
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bank = BANK3;
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break;
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default:
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return -1;
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}
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sect_add = sector * (info->size / info->sector_count);
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instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
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writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
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/* Wait until finished previous write command. */
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if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
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return -EBUSY;
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/* Send write enable, before erase commands. */
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if (smi_write_enable(bank))
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return -EIO;
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/* Put SMI in SW mode */
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writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
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/* Send Sector Erase command in SW Mode */
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writel(instruction, &smicntl->smi_tr);
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writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
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&smicntl->smi_cr2);
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if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
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return -EIO;
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if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
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return -EBUSY;
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/* Put SMI in HW mode */
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writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
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&smicntl->smi_cr1);
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return 0;
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}
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/*
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* smi_write - Write to SMI flash
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* @src_addr: source buffer
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* @dst_addr: destination buffer
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* @length: length to write in bytes
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* @bank: bank base address
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*
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* Write to SMI flash
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*/
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static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
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unsigned int length, ulong bank_addr)
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{
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u8 *src_addr8 = (u8 *)src_addr;
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u8 *dst_addr8 = (u8 *)dst_addr;
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int banknum;
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int i;
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switch (bank_addr) {
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case SMIBANK0_BASE:
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banknum = BANK0;
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break;
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case SMIBANK1_BASE:
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banknum = BANK1;
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break;
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case SMIBANK2_BASE:
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banknum = BANK2;
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break;
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case SMIBANK3_BASE:
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banknum = BANK3;
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break;
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default:
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return -1;
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}
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if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
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return -EBUSY;
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/* Set SMI in Hardware Mode */
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writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
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if (smi_write_enable(banknum))
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return -EIO;
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/* Perform the write command */
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for (i = 0; i < length; i += 4) {
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if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
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if (smi_wait_till_ready(banknum,
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CONFIG_SYS_FLASH_WRITE_TOUT))
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return -EBUSY;
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if (smi_write_enable(banknum))
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return -EIO;
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}
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if (length < 4) {
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int k;
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/*
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* Handle special case, where length < 4 (redundant env)
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*/
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for (k = 0; k < length; k++)
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*dst_addr8++ = *src_addr8++;
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} else {
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/* Normal 32bit write */
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*dst_addr++ = *src_addr++;
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}
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if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
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return -EIO;
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}
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if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
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return -EBUSY;
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|
||||
writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* write_buff - Write to SMI flash
|
||||
* @info: flash info structure
|
||||
* @src: source buffer
|
||||
* @dest_addr: destination buffer
|
||||
* @length: length to write in words
|
||||
*
|
||||
* Write to SMI flash
|
||||
*/
|
||||
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
|
||||
{
|
||||
return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
|
||||
length, info->start[0]);
|
||||
}
|
||||
|
||||
/*
|
||||
* flash_init - SMI flash initialization
|
||||
*
|
||||
* SMI flash initialization
|
||||
*/
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long size = 0;
|
||||
int i, j;
|
||||
|
||||
smi_init();
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size += flash_info[i].size = flash_get_size(bank_base[i], i);
|
||||
}
|
||||
|
||||
for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
|
||||
for (i = 1; i < flash_info[j].sector_count; i++)
|
||||
flash_info[j].start[i] =
|
||||
flash_info[j].start[i - 1] +
|
||||
flash_info->size / flash_info->sector_count;
|
||||
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*
|
||||
* flash_print_info - Print SMI flash information
|
||||
*
|
||||
* Print SMI flash information
|
||||
*/
|
||||
void flash_print_info(flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
puts("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (info->size >= 0x100000)
|
||||
printf(" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
else
|
||||
printf(" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
|
||||
puts(" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
int size;
|
||||
int erased;
|
||||
u32 *flash;
|
||||
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
size = (info->size) / (info->sector_count);
|
||||
flash = (u32 *) info->start[i];
|
||||
size = size / sizeof(int);
|
||||
|
||||
while ((size--) && (*flash++ == ~0))
|
||||
;
|
||||
|
||||
size++;
|
||||
if (size)
|
||||
erased = 0;
|
||||
else
|
||||
erased = 1;
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf("\n");
|
||||
|
||||
printf(" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ", info->protect[i] ? "RO " : " ");
|
||||
#else
|
||||
if ((i % 5) == 0)
|
||||
printf("\n ");
|
||||
printf(" %08lX%s",
|
||||
info->start[i], info->protect[i] ? " (RO) " : " ");
|
||||
#endif
|
||||
}
|
||||
putc('\n');
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* flash_erase - Erase SMI flash
|
||||
*
|
||||
* Erase SMI flash
|
||||
*/
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int rcode = 0;
|
||||
int prot = 0;
|
||||
flash_sect_t sect;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
puts("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
if (prot) {
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
putc('\n');
|
||||
}
|
||||
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) {
|
||||
if (smi_sector_erase(info, sect))
|
||||
rcode = 1;
|
||||
else
|
||||
putc('.');
|
||||
}
|
||||
}
|
||||
puts(" done\n");
|
||||
return rcode;
|
||||
}
|
||||
#endif
|
||||
@ -130,7 +130,6 @@ extern phys_addr_t prior_stage_fdt_address;
|
||||
/*
|
||||
* Flash configuration.
|
||||
*/
|
||||
#define CONFIG_ST_SMI
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
|
||||
|
||||
@ -1,100 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
||||
*/
|
||||
|
||||
#ifndef ST_SMI_H
|
||||
#define ST_SMI_H
|
||||
|
||||
/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
|
||||
/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
|
||||
|
||||
#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE
|
||||
|
||||
#define SMIBANK0_BASE (FLASH_START_ADDRESS)
|
||||
#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE)
|
||||
#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE)
|
||||
#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE)
|
||||
|
||||
#define BANK0 0
|
||||
#define BANK1 1
|
||||
#define BANK2 2
|
||||
#define BANK3 3
|
||||
|
||||
struct smi_regs {
|
||||
u32 smi_cr1;
|
||||
u32 smi_cr2;
|
||||
u32 smi_sr;
|
||||
u32 smi_tr;
|
||||
u32 smi_rr;
|
||||
};
|
||||
|
||||
/* CONTROL REG 1 */
|
||||
#define BANK_EN 0x0000000F /* enables all banks */
|
||||
#define DSEL_TIME 0x00000060 /* Deselect time */
|
||||
#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */
|
||||
#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */
|
||||
#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */
|
||||
#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */
|
||||
#define SW_MODE 0x10000000 /* enables SW Mode */
|
||||
#define WB_MODE 0x20000000 /* Write Burst Mode */
|
||||
#define FAST_MODE 0x00008000 /* Fast Mode */
|
||||
#define HOLD1 0x00010000
|
||||
|
||||
/* CONTROL REG 2 */
|
||||
#define RD_STATUS_REG 0x00000400 /* reads status reg */
|
||||
#define WE 0x00000800 /* Write Enable */
|
||||
#define BANK0_SEL 0x00000000 /* Select Banck0 */
|
||||
#define BANK1_SEL 0x00001000 /* Select Banck1 */
|
||||
#define BANK2_SEL 0x00002000 /* Select Banck2 */
|
||||
#define BANK3_SEL 0x00003000 /* Select Banck3 */
|
||||
#define BANKSEL_SHIFT 12
|
||||
#define SEND 0x00000080 /* Send data */
|
||||
#define TX_LEN_1 0x00000001 /* data length = 1 byte */
|
||||
#define TX_LEN_2 0x00000002 /* data length = 2 byte */
|
||||
#define TX_LEN_3 0x00000003 /* data length = 3 byte */
|
||||
#define TX_LEN_4 0x00000004 /* data length = 4 byte */
|
||||
#define RX_LEN_1 0x00000010 /* data length = 1 byte */
|
||||
#define RX_LEN_2 0x00000020 /* data length = 2 byte */
|
||||
#define RX_LEN_3 0x00000030 /* data length = 3 byte */
|
||||
#define RX_LEN_4 0x00000040 /* data length = 4 byte */
|
||||
#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */
|
||||
#define WCIE 0x00000200 /* WCF Interrupt Enable */
|
||||
|
||||
/* STATUS_REG */
|
||||
#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */
|
||||
#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */
|
||||
#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */
|
||||
#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */
|
||||
#define RSR 0x00000005 /* Read Status regiser */
|
||||
#define TFF 0x00000100 /* Transfer Finished FLag */
|
||||
#define WCF 0x00000200 /* Transfer Finished FLag */
|
||||
#define ERF1 0x00000400 /* Error Flag 1 */
|
||||
#define ERF2 0x00000800 /* Error Flag 2 */
|
||||
#define WM0 0x00001000 /* WM Bank 0 */
|
||||
#define WM1 0x00002000 /* WM Bank 1 */
|
||||
#define WM2 0x00004000 /* WM Bank 2 */
|
||||
#define WM3 0x00008000 /* WM Bank 3 */
|
||||
#define WM_SHIFT 12
|
||||
|
||||
/* TR REG */
|
||||
#define READ_ID 0x0000009F /* Read Identification */
|
||||
#define BULK_ERASE 0x000000C7 /* BULK erase */
|
||||
#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */
|
||||
#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */
|
||||
|
||||
struct flash_dev {
|
||||
u32 density;
|
||||
ulong size;
|
||||
ushort sector_count;
|
||||
};
|
||||
|
||||
#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
|
||||
#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
|
||||
#define WMODE_TOUT 15 /* write enable timeout(in ms) */
|
||||
|
||||
extern void smi_init(void);
|
||||
|
||||
#endif
|
||||
@ -1427,7 +1427,6 @@ CONFIG_STM32_FLASH
|
||||
CONFIG_STV0991
|
||||
CONFIG_STV0991_HZ
|
||||
CONFIG_STV0991_HZ_CLOCK
|
||||
CONFIG_ST_SMI
|
||||
CONFIG_SXNI855T
|
||||
CONFIG_SYSFS
|
||||
CONFIG_SYSMGR_ISWGRP_HANDOFF
|
||||
|
||||
Loading…
Reference in New Issue
Block a user