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powerpc/mpc8536ds: Add eSPI support for MPC8536DS

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1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
   so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
   to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Xie Xiaobo 2011-10-03 12:18:39 -07:00 committed by Kumar Gala
parent 867b06f434
commit ae2044d8b3
3 changed files with 21 additions and 4 deletions
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5
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1934,7 +1934,12 @@ typedef struct ccsr_gur {
u8 res1[8]; u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */ u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12]; u8 res2[12];
#if defined(CONFIG_MPC8536)
u32 gencfgr; /* General Configuration Register */
#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
#else
u32 gpiocr; /* GPIO control */ u32 gpiocr; /* GPIO control */
#endif
u8 res3[12]; u8 res3[12];
#if defined(CONFIG_MPC8569) #if defined(CONFIG_MPC8569)
u32 plppar1; /* Platform port pin assignment 1 */ u32 plppar1; /* Platform port pin assignment 1 */

6
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2008-2010 Freescale Semiconductor, Inc. * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -49,10 +49,8 @@ int board_early_init_f (void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr, setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SD_DATA | (MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_WP)); MPC85xx_PMUXCR_SDHC_WP));
#endif #endif
return 0; return 0;
} }

14
include/configs/MPC8536DS.h
View File

@ -77,6 +77,7 @@
#define CONFIG_MPC8536DS 1 #define CONFIG_MPC8536DS 1
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
@ -457,6 +458,19 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#define CONFIG_FSL_ESPI
#if defined(CONFIG_SPI_FLASH)
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#endif
/* /*
* General PCI * General PCI
* Memory space is mapped 1-1, but I/O space must start from 0. * Memory space is mapped 1-1, but I/O space must start from 0.