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arm: mvebu: update RTC values for PCIe memory wrappers

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Update the RTC (Read Timing Control) values for PCIe memory wrappers
following an ERRATA (ERRATA# TDB). This means the PCIe accesses will
used slower memory Read Timing, to allow more efficient energy
consumption, in order to lower the minimum VDD of the memory.  Will lead
to more robust memory when voltage drop occurs (VDDSEG)

The code is based on changes from Marvell's U-Boot, specifically:

20cd270407
eb608a7c8d
c4af19ae2b

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2020-02-26 19:53:50 +13:00 committed by Stefan Roese
parent 201a500dec
commit ad91fdfff0
4 changed files with 35 additions and 0 deletions
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2
arch/arm/mach-mvebu/include/mach/cpu.h
View File

@ -166,8 +166,10 @@ int ddr3_init(void);
/* Auto Voltage Scaling */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
void mv_avs_init(void);
void mv_rtc_config(void);
#else
static inline void mv_avs_init(void) {}
static inline void mv_rtc_config(void) {}
#endif
/*

17
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
View File

@ -257,6 +257,23 @@ u8 sys_env_device_rev_get(void)
return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
}
void mv_rtc_config(void)
{
u32 i, val;
if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
return;
/* Activate pipe0 for read/write transaction, and set XBAR client number #1 */
val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS |
0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS;
writel(val, MVEBU_DFX_BASE);
/* Set new RTC value for all memory wrappers */
for (i = 0; i < RTC_MEMORY_WRAPPER_COUNT; i++)
reg_write(RTC_MEMORY_WRAPPER_REG(i), RTC_MEMORY_WRAPPER_CTRL_VAL);
}
void mv_avs_init(void)
{
u32 sar_freq;

13
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
View File

@ -150,6 +150,19 @@
#define MPP_UART1_SET_MASK (~(0xff000))
#define MPP_UART1_SET_DATA (0x66000)
#define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0
/* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit
* address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] =>
* [14:13] are dismissed. hence field offset is also shifted to 10
*/
#define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10
#define RTC_MEMORY_CTRL_REG_BASE 0xE6000
#define RTC_MEMORY_WRAPPER_COUNT 8
#define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40))
#define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6
#define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS)
#define AVS_DEBUG_CNTR_REG 0xe4124
#define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073

3
arch/arm/mach-mvebu/spl.c
View File

@ -130,6 +130,9 @@ void board_init_f(ulong dummy)
/* Initialize Auto Voltage Scaling */
mv_avs_init();
/* Update read timing control for PCIe */
mv_rtc_config();
/*
* Return to the BootROM to continue the Marvell xmodem
* UART boot protocol. As initiated by the kwboot tool.