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Merge branch 'master' of /home/wd/git/u-boot/custodians

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This commit is contained in:
Wolfgang Denk 2008-11-09 00:01:59 +01:00
commit ac4aeb1735
106 changed files with 4333 additions and 7699 deletions
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1
MAINTAINERS
View File

@ -722,6 +722,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
M5235EVB mcf52x2
M5253DEMO mcf52x2
M53017EVB mcf532x
M5329EVB mcf532x
M5373EVB mcf532x
M54455EVB mcf5445x

1
MAKEALL
View File

@ -709,6 +709,7 @@ LIST_coldfire=" \
M5272C3 \
M5275EVB \
M5282EVB \
M53017EVB \
M5329AFEE \
M5373EVB \
M54451EVB \

25
Makefile
View File

@ -1932,7 +1932,27 @@ ZPC1900_config: unconfig
## Coldfire
#########################################################################
M52277EVB_config: unconfig
M52277EVB_config \
M52277EVB_spansion_config \
M52277EVB_stmicro_config : unconfig
@case "$@" in \
M52277EVB_config) FLASH=SPANSION;; \
M52277EVB_spansion_config) FLASH=SPANSION;; \
M52277EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
$(XECHO) "... with SPANSION boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi
@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
M5235EVB_config \
@ -1992,6 +2012,9 @@ M5275EVB_config : unconfig
M5282EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
M53017EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \

2
board/BuS/EB+MCF-EV123/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

304
board/BuS/EB+MCF-EV123/mii.c
View File

@ -1,304 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/cobra5272/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o mii.o
COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

303
board/cobra5272/mii.c
View File

@ -1,303 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
} else {
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

4
board/freescale/m52277evb/config.mk
View File

@ -22,4 +22,6 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

26
board/freescale/m52277evb/m52277evb.c
View File

@ -38,8 +38,18 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
/*
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
u32 dramsize, i;
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
}
i--;
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Issue LEMR */
/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
__asm__("nop");
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
__asm__("nop");
udelay(1000);
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Perform two refresh cycles */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
udelay(100);
#endif
return (dramsize);
};

0
board/freescale/m52277evb/u-boot.lds → board/freescale/m52277evb/u-boot.spa
View File

20
board/freescale/m5235evb/u-boot.lds → board/freescale/m52277evb/u-boot.stm
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@ -55,15 +55,7 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf523x/start.o (.text)
cpu/mcf523x/cpu_init.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
cpu/mcf5227x/start.o (.text)
*(.text)
*(.fixup)
@ -129,7 +121,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)

2
board/freescale/m5235evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

307
board/freescale/m5235evb/mii.c
View File

@ -1,307 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m5271evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

303
board/freescale/m5271evb/mii.c
View File

@ -1,303 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
} else {
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m5272c3/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

378
board/freescale/m5272c3/flash.c
View File

@ -1,378 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
printf ("AM29PL160CB (16Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
Done:
return;
}
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_PL160CB & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured to many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
/* 1st is 16 KiB */
flash_info[i].start[j] = flashbase;
}
if ((j >= 1) && (j <= 2)) {
/* 2nd and 3rd are 8 KiB */
flash_info[i].start[j] =
flashbase + 0x4000 + 0x2000 * (j - 1);
}
if (j == 3) {
/* 4th is 224 KiB */
flash_info[i].start[j] = flashbase + 0x8000;
}
if ((j >= 4) && (j <= 10)) {
/* rest is 256 KiB */
flash_info[i].start[j] =
flashbase + 0x40000 + 0x40000 * (j -
4);
}
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
return size;
}
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define READY 1
#define ERR 2
#define TMO 4
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
ulong result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
printf ("\n");
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
set_timer (0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr =
(volatile u16 *) (info->start[sect]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
}
if (!chip1
&& (result & 0xFFFF) & BIT_ERASE_DONE)
chip1 = READY;
} while (!chip1);
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip1 == ERR) {
rc = ERR_PROG_ERROR;
goto outahere;
}
if (chip1 == TMO) {
rc = ERR_TIMOUT;
goto outahere;
}
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
}
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay (10000);
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
int rc = ERR_OK;
int cflag, iflag;
int chip1;
/*
* Check if Flash is (sufficiently) erased
*/
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
set_timer (0);
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
if (!chip1 && ((result & 0x80) == (data & 0x80)))
chip1 = READY;
} while (!chip1);
*addr = CMD_READ_ARRAY;
if (chip1 == ERR || *addr != data)
rc = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, data;
int rc;
if (addr & 1) {
printf ("unaligned destination not supported\n");
return ERR_ALIGN;
}
#if 0
if (cnt & 1) {
printf ("odd transfer sizes not supported\n");
return ERR_ALIGN;
}
#endif
wp = addr;
if (addr & 1) {
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
src);
if ((rc = write_word (info, wp - 1, data)) != 0) {
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
}
while (cnt >= 2) {
data = *((volatile u16 *) src);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 1) {
data = (*((volatile u8 *) src) << 8) |
*((volatile u8 *) (wp + 1));
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
}
return ERR_OK;
}

303
board/freescale/m5272c3/mii.c
View File

@ -1,303 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
} else {
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m5275evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

319
board/freescale/m5275evb/mii.c
View File

@ -1,319 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
if (setclear) {
/* Enable Ethernet pins */
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c |= 0x0F00;
gpio->par_fec0hl |= 0xC0;
} else {
gpio->par_feci2c |= 0x00A0;
gpio->par_fec1hl |= 0xC0;
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
} else {
gpio->par_feci2c &= ~0x00A0;
gpio->par_fec1hl &= ~0xC0;
}
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m5282evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

304
board/freescale/m5282evb/mii.c
View File

@ -1,304 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_AMD79C874VC "AMD79C874VC"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
strcpy(info->phy_name,
STR_ID_AMD79C874VC);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_AMD79C874VC:
printf(STR_ID_AMD79C874VC);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

44
board/freescale/m53017evb/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/freescale/m53017evb/config.mk Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0

94
board/freescale/m53017evb/m53017evb.c Normal file
View File

@ -0,0 +1,94 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale M53017EVB\n");
return 0;
};
phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
#endif
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
udelay(500);
/* Issue PALL */
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
asm("nop");
/* Issue LEMR */
sdram->mode = CONFIG_SYS_SDRAM_MODE;
asm("nop");
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
asm("nop");
udelay(100);
return dramsize;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}

6
board/freescale/m54455evb/u-boot.lds → board/freescale/m53017evb/u-boot.lds
View File

@ -55,9 +55,9 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
cpu/mcf532x/start.o (.text)
cpu/mcf532x/libmcf532x.a (.text)
lib_m68k/libm68k.a (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)

2
board/freescale/m5329evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o nand.o
COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

306
board/freescale/m5329evb/mii.c
View File

@ -1,306 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
} else {
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

57
board/freescale/m5329evb/nand.c
View File

@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR;
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08
#define CLR_ALE ~SET_ALE
static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
nand_baseaddr |= SET_CLE;
else
nand_baseaddr &= CLR_CLE;
if ( ctrl & NAND_ALE )
nand_baseaddr |= SET_ALE;
else
nand_baseaddr &= CLR_ALE;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
*nCE &= 0xFFFB;
if (ctrl & NAND_NCE)
*nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
}
static u8 nand_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
}
static int nand_dev_ready(struct mtd_info *mtdinfo)
{
return 1;
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
/* set up pin configuration */
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;
@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand)
nand->chip_delay = 50;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_hwcontrol;
nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready;
return 0;
}

2
board/freescale/m5373evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o nand.o
COBJS = $(BOARD).o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

306
board/freescale/m5373evb/mii.c
View File

@ -1,306 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
} else {
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

17
board/freescale/m5373evb/nand.c
View File

@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(SET_ALE | SE_CLE);
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
*nCE &= 0xFFFB;
if (ctrl & NAND_NCE)
*nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
/* set up pin configuration */
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;

2
board/freescale/m54451evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

303
board/freescale/m54451evb/mii.c
View File

@ -1,303 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_KSZ8041NL 0x00221512
#define STR_ID_KSZ8041NL "KSZ8041NL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
struct eth_device *dev;
int i, miispd;
u16 rst = 0;
dev = eth_get_dev();
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
for (i = 0; i < FEC_RESET_DELAY; ++i) {
udelay(500);
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
if ((rst & PHY_BMCR_RESET) == 0)
break;
}
if (i == FEC_RESET_DELAY)
printf("Mii reset timeout %d\n", i);
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KSZ8041NL:
strcpy(info->phy_name,
STR_ID_KSZ8041NL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KSZ8041NL:
printf(STR_ID_KSZ8041NL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m54455evb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

324
board/freescale/m54455evb/mii.c
View File

@ -1,324 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
struct eth_device *dev;
int i, miispd;
u16 rst = 0;
dev = eth_get_dev();
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
for (i = 0; i < FEC_RESET_DELAY; ++i) {
udelay(500);
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
if ((rst & PHY_BMCR_RESET) == 0)
break;
}
if (i == FEC_RESET_DELAY)
printf("Mii reset timeout %d\n", i);
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
strcpy(info->phy_name,
STR_ID_DP83848VV);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_DP83848VV:
printf(STR_ID_DP83848VV);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m547xevb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

322
board/freescale/m547xevb/mii.c
View File

@ -1,322 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <asm/immap.h>
#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq |= 0xF000;
else
gpio->par_feci2cirq |= 0x0FC0;
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq &= 0x0FFF;
else
gpio->par_feci2cirq &= 0xF03F;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_BCM5222 "BCM5222"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_dma *info)
{
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_dma *info;
struct eth_device *dev;
volatile fecdma_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fecdma_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_dma *info = dev->priv;
int phyaddr, pass, temp;
uint phyno, phytype;
if (info->phyname_init) {
return info->phy_addr;
}
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
temp = 0;
if (info->index > 0) {
/* Some phy have multiple address, to solve the issue
where phyno keeps starting from 0, check the
previous phy address if both miibase are the same. */
if (info->miibase == (info->next)->miibase) {
temp = (info->next)->phy_addr + 1;
}
}
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_BCM5222:
strcpy(info->phy_name, STR_ID_BCM5222);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_BCM5222:
printf(STR_ID_BCM5222);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
void __mii_init(void)
{
volatile fecdma_t *fecp;
struct fec_info_dma *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fecdma_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/freescale/m548xevb/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o mii.o
COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

322
board/freescale/m548xevb/mii.c
View File

@ -1,322 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <asm/immap.h>
#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq |= 0xF000;
else
gpio->par_feci2cirq |= 0x0FC0;
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq &= 0x0FFF;
else
gpio->par_feci2cirq &= 0xF03F;
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_BCM5222 "BCM5222"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_dma *info)
{
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_dma *info;
struct eth_device *dev;
volatile fecdma_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fecdma_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_dma *info = dev->priv;
int phyaddr, pass, temp;
uint phyno, phytype;
if (info->phyname_init) {
return info->phy_addr;
}
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
temp = 0;
if (info->index > 0) {
/* Some phy have multiple address, to solve the issue
where phyno keeps starting from 0, check the
previous phy address if both miibase are the same. */
if (info->miibase == (info->next)->miibase) {
temp = (info->next)->phy_addr + 1;
}
}
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_BCM5222:
strcpy(info->phy_name, STR_ID_BCM5222);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_BCM5222:
printf(STR_ID_BCM5222);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
void __mii_init(void)
{
volatile fecdma_t *fecp;
struct fec_info_dma *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fecdma_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
board/idmr/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o mii.o
COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

303
board/idmr/mii.c
View File

@ -1,303 +0,0 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>
#include <config.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
} else {
}
return 0;
}
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
/* PHY identification */
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
#define STR_ID_LXT970 "LXT970"
#define STR_ID_LXT971 "LXT971"
#define STR_ID_82555 "Intel82555"
#define STR_ID_QS6612 "QS6612"
#define STR_ID_AMD79C784 "AMD79C784"
#define STR_ID_LSI80225 "LSI80225"
#define STR_ID_LSI80225B "LSI80225/B"
#define STR_ID_DP83848VV "N83848"
#define STR_ID_DP83849 "N83849"
#define STR_ID_KS8721BL "KS8721BL"
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_reset(struct fec_info_s *info)
{
volatile fec_t *fecp = (fec_t *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
struct fec_info_s *info;
struct eth_device *dev;
volatile fec_t *ep;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (fec_t *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
struct fec_info_s *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
strcpy(info->phy_name,
STR_ID_KS8721BL);
info->phyname_init = 1;
break;
default:
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d type ", phyno, pass);
switch (phytype & 0xffffffff) {
case PHY_ID_KS8721BL:
printf(STR_ID_KS8721BL);
break;
default:
printf("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
volatile fec_t *fecp;
struct fec_info_s *info;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 autoneg = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
while (i < MCFFEC_TOUT_LOOP) {
autoneg = 0;
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
i++;
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
break;
udelay(500);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Auto Negotiation not complete\n");
}
/* adapt to the half/full speed settings */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

2
cpu/mcf5227x/Makefile
View File

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

10
cpu/mcf5227x/cpu.c
View File

@ -65,12 +65,12 @@ int checkcpu(void)
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk)),
strmhz(buf2, gd->bus_clk)),
strmhz(buf3, gd->flb_clk)));
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk),
strmhz(buf3, gd->flb_clk));
printf(" INP CLK %s MHz VCO CLK %s MHz\n",
strmhz(buf1, gd->inp_clk)),
strmhz(buf2, gd->vco_clk)));
strmhz(buf1, gd->inp_clk),
strmhz(buf2, gd->vco_clk));
}
return 0;

20
cpu/mcf5227x/cpu_init.c
View File

@ -45,6 +45,7 @@ void cpu_init_f(void)
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
pll->psr = 0x12;
@ -58,37 +59,44 @@ void cpu_init_f(void)
scm1->pacrg = 0;
scm1->pacri = 0;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;

261
cpu/mcf5227x/dspi.c Normal file
View File

@ -0,0 +1,261 @@
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <malloc.h>
#if defined(CONFIG_CF_DSPI)
#include <asm/immap.h>
void dspi_init(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio->par_dspi =
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK;
dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
#ifdef CONFIG_SYS_DSPI_DCTAR0
dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR1
dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR2
dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR3
dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR4
dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR5
dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR6
dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR7
dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
#endif
}
void dspi_tx(int chipsel, u8 attrib, u16 data)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
while ((dspi->dsr & 0x0000F000) >= 4) ;
dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
}
u16 dspi_rx(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
while ((dspi->dsr & 0x000000F0) == 0) ;
return (dspi->drfr & 0xFFFF);
}
#if defined(CONFIG_CMD_SPI)
void spi_init_f(void)
{
}
void spi_init_r(void)
{
}
void spi_init(void)
{
dspi_init();
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct spi_slave *slave;
slave = malloc(sizeof(struct spi_slave));
if (!slave)
return NULL;
switch (cs) {
case 0:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
break;
}
slave->bus = bus;
slave->cs = cs;
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
switch (slave->cs) {
case 0:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
break;
}
free(slave);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
static int bWrite = 0;
u8 *spi_rd, *spi_wr;
int len = bitlen >> 3;
spi_rd = (u8 *) din;
spi_wr = (u8 *) dout;
/* command handling */
if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
switch (*spi_wr) {
case 0x02: /* Page Prog */
bWrite = 1;
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[3]);
dspi_rx();
return 0;
case 0x05: /* Read Status */
if (len == 4)
if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
&& (spi_wr[3] == 0xFF)) {
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
}
return 0;
case 0x06: /* WREN */
dspi_tx(slave->cs, 0x00, *spi_wr);
dspi_rx();
return 0;
case 0x0B: /* Fast read */
if ((len == 5) && (spi_wr[4] == 0)) {
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[3]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[4]);
dspi_rx();
}
return 0;
case 0x9F: /* RDID */
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
return 0;
case 0xD8: /* Sector erase */
if (len == 4)
if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x00, spi_wr[3]);
dspi_rx();
}
return 0;
}
}
if (bWrite)
len--;
while (len--) {
if (dout != NULL) {
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
spi_wr++;
}
if (din != NULL) {
dspi_tx(slave->cs, 0x80, 0);
*spi_rd = dspi_rx();
spi_rd++;
}
}
if (flags == SPI_XFER_END) {
if (bWrite) {
dspi_tx(slave->cs, 0x00, *spi_wr);
dspi_rx();
bWrite = 0;
} else {
dspi_tx(slave->cs, 0x00, 0);
dspi_rx();
}
}
return 0;
}
#endif /* CONFIG_CMD_SPI */
#endif /* CONFIG_CF_DSPI */

30
cpu/mcf5227x/speed.c
View File

@ -90,17 +90,33 @@ int get_clocks(void)
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
bootmode = (ccm->ccr & 0x000C) >> 2;
pcrvalue = pll->pcr & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr != 0x1E) {
if (pfdr == 0x1E)
bootmode = 0; /* Normal Mode */
#ifdef CONFIG_CF_SBF
bootmode = 3; /* Serial Mode */
#endif
if (bootmode == 0) {
/* Normal mode */
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
pcrvalue = (pll->pcr & 0x00FFFFFF);
pcrvalue |= 0x1E << 24;
pll->pcr = pcrvalue;
vco =
((pll->pcr & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
} else {
/* Normal Mode */
vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco;
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {

245
cpu/mcf5227x/start.S
View File

@ -46,6 +46,11 @@
addl #60,%sp; /* space for 15 regs */ \
rte;
#if defined(CONFIG_CF_SBF)
#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
/*
* Vector table. This is used for initial platform startup.
@ -53,8 +58,14 @@
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
#if defined(CONFIG_CF_SBF)
INITSP: .long 0 /* Initial SP */
INITPC: .long ASM_DRAMINIT /* Initial PC */
#else
INITSP: .long 0 /* Initial SP */
INITPC: .long _START /* Initial PC */
#endif
vector02: .long _FAULT /* Access Error */
vector03: .long _FAULT /* Address Error */
vector04: .long _FAULT /* Illegal Instruction */
@ -83,6 +94,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
#if !defined(CONFIG_CF_SBF)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@ -122,9 +134,231 @@ vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
#if defined(CONFIG_CF_SBF)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00020000 /* image length */
.long TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1 /* init Rambar */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
/* Must disable global address */
move.l #0xFC008000, %a1
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
/*
* Dram Initialization
* a1, a2, and d0
*/
/* mscr sdram */
move.l #0xFC0A4074, %a1
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
nop
/* SDRAM Chip 0 and 1 */
move.l #0xFC0B8110, %a1
move.l #0xFC0B8114, %a2
/* calculate the size */
move.l #0x13, %d1
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
#ifdef CONFIG_SYS_SDRAM_BASE1
lsr.l #1, %d2
#endif
dramsz_loop:
lsr.l #1, %d2
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
#ifdef CONFIG_SYS_SDRAM_BASE1
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
or.l %d1, (%a2)
#endif
nop
/* dram cfg1 and cfg2 */
move.l #0xFC0B8008, %a1
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
nop
move.l #0xFC0B800C, %a2
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
nop
move.l #0xFC0B8000, %a1 /* Mode */
move.l #0xFC0B8004, %a2 /* Ctrl */
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Issue LEMR */
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
nop
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
nop
move.l #1000, %d0
wait1000:
nop
subq.l #1, %d0
bne wait1000
/* Issue PALL */
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
nop
/* Perform two refresh cycles */
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
nop
move.l %d0, (%a2)
move.l %d0, (%a2)
nop
move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
and.l #0x7FFFFFFF, %d0
or.l #0x10000c00, %d0
move.l %d0, (%a2)
nop
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
* a1 - dspi status
* a2 - dtfr
* a3 - drfr
* a4 - Dst addr
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
move.l #0xFC0A4036, %a0
move.b #0x3F, %d0
move.b %d0, (%a0)
/* DSPI CS */
#ifdef CONFIG_SYS_DSPI_CS0
move.b (%a0), %d0
or.l #0xC0, %d0
move.b %d0, (%a0)
#endif
#ifdef CONFIG_SYS_DSPI_CS2
move.l #0xFC0A4037, %a0
move.b (%a0), %d0
or.l #0x10, %d0
move.b %d0, (%a0)
#endif
nop
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
move.l #0x3E000011, (%a0)
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
move.l #(ASM_SBF_IMG_HDR + 4), %a1
move.l (%a1)+, %d5
move.l (%a1), %a4
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
/* Issue commands and address */
move.l #0x8004000B, %d2 /* Fast Read Cmd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 2 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 1 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Address byte 0 */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.l #0x80040000, %d2 /* Dummy Wr and Rd */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* Transfer serial boot header to sram */
asm_dspi_rd_loop1:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a0) /* read, copy to dst */
add.l #1, %a0 /* inc dst by 1 */
sub.l #1, %d4 /* dec cnt by 1 */
bne asm_dspi_rd_loop1
/* Transfer u-boot from serial flash to memory */
asm_dspi_rd_loop2:
move.l #0x80040000, %d2
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
move.b %d1, (%a4) /* read, copy to dst */
add.l #1, %a4 /* inc dst by 1 */
sub.l #1, %d5 /* dec cnt by 1 */
bne asm_dspi_rd_loop2
move.l #0x00040000, %d2 /* Terminate */
jsr asm_dspi_wr_status
jsr asm_dspi_rd_status
/* jump to memory and execute */
move.l #(TEXT_BASE + 0x400), %a0
move.l %a0, (%a1)
jmp (%a0)
asm_dspi_wr_status:
move.l (%a1), %d0 /* status */
and.l #0x0000F000, %d0
cmp.l #0x00003000, %d0
bgt asm_dspi_wr_status
move.l %d2, (%a2)
rts
asm_dspi_rd_status:
move.l (%a1), %d0 /* status */
and.l #0x000000F0, %d0
lsr.l #4, %d0
cmp.l #0, %d0
beq asm_dspi_rd_status
move.b (%a3), %d1
rts
#endif /* CONFIG_CF_SBF */
.text
. = 0x400
.globl _start
_start:
nop
@ -132,11 +366,16 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
#if defined(CONFIG_CF_SBF)
move.l #TEXT_BASE, %d0
movec %d0, %VBR
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
/* initialize general use internal ram */
move.l #0, %d0

4
cpu/mcf523x/cpu.c
View File

@ -65,8 +65,8 @@ int checkcpu(void)
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk)),
strmhz(buf2, gd->bus_clk)));
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk));
}
return 0;

24
cpu/mcf523x/cpu_init.c
View File

@ -27,9 +27,14 @@
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif
/*
* Breath some life into the CPU...
*
@ -143,3 +148,20 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
}
return 0;
}
#endif

349
cpu/mcf52x2/cpu_init.c
View File

@ -36,6 +36,71 @@
#include <watchdog.h>
#include <asm/immap.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif
#ifndef CONFIG_M5272
/* Only 5272 Flexbus chipselect is different from the rest */
void init_fbcs(void)
{
volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
&& defined(CONFIG_SYS_CS6_CTRL))
fbcs->csar6 = CONFIG_SYS_CS6_BASE;
fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
&& defined(CONFIG_SYS_CS7_CTRL))
fbcs->csar7 = CONFIG_SYS_CS7_BASE;
fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
#endif
}
#endif
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
@ -66,22 +131,14 @@ void cpu_init_f(void)
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
/*
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
/* FlexBus Chipselect */
init_fbcs();
#ifdef CONFIG_FSL_I2C
CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
@ -121,6 +178,9 @@ void cpu_init_f(void)
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
/* FlexBus Chipselect */
init_fbcs();
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@ -153,6 +213,19 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
} else {
}
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5272)
@ -255,6 +328,22 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
} else {
}
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5272) */
#if defined(CONFIG_M5275)
@ -268,66 +357,20 @@ void uart_port_conf(void)
*/
void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
/*
* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
/* Memory Controller: */
/* Flash */
csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
#endif
/* FlexBus Chipselect */
init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
@ -349,7 +392,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CONFIG_SYS_UART_PORT) {
@ -364,6 +407,35 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
if (setclear) {
/* Enable Ethernet pins */
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c |= 0x0F00;
gpio->par_fec0hl |= 0xC0;
} else {
gpio->par_feci2c |= 0x00A0;
gpio->par_fec1hl |= 0xC0;
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
} else {
gpio->par_feci2c &= ~0x00A0;
gpio->par_fec1hl &= ~0xC0;
}
}
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5275) */
#if defined(CONFIG_M5282)
@ -384,7 +456,8 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@ -425,119 +498,8 @@ void cpu_init_f(void)
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
/* This is probably a bad place to setup chip selects, but everyone
else is doing it! */
#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS0_WIDTH == 8)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS0_WIDTH == 16)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS0_WIDTH == 32)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
| CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS1_WIDTH == 8)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS1_WIDTH == 16)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS1_WIDTH == 32)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
| CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS2_WIDTH == 8)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS2_WIDTH == 16)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS2_WIDTH == 32)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
| CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS3_WIDTH == 8)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS3_WIDTH == 16)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS3_WIDTH == 32)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
| CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS3_RO != 0)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 3 are not initialized/used"
#endif
/* FlexBus Chipselect */
init_fbcs();
#endif /* CONFIG_MONITOR_IS_IN_RAM */
@ -571,6 +533,20 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
}
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5249)
@ -632,17 +608,8 @@ void cpu_init_f(void)
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
/*
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
/* FlexBus Chipselect */
init_fbcs();
/* enable instruction cache now */
icache_enable();

25
cpu/mcf532x/cpu.c
View File

@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -56,6 +56,24 @@ int checkcpu(void)
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
#ifdef CONFIG_MCF5301x
case 0x78:
id = 53010;
break;
case 0x77:
id = 53012;
break;
case 0x76:
id = 53015;
break;
case 0x74:
id = 53011;
break;
case 0x73:
id = 53013;
break;
#endif
#ifdef CONFIG_MCF532x
case 0x54:
id = 5329;
break;
@ -77,6 +95,7 @@ int checkcpu(void)
case 0x6B:
id = 5372;
break;
#endif
}
if (id) {
@ -85,8 +104,8 @@ int checkcpu(void)
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk)),
strmhz(buf2, gd->bus_clk)));
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk));
}
return 0;

227
cpu/mcf532x/cpu_init.c
View File

@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -27,16 +27,188 @@
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif
#ifdef CONFIG_MCF5301x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
/*wdog->cr = 0; */
#endif
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
scm1->pacrg = 0;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
gpio->par_cs |= GPIO_PAR_CS0_CS0;
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
gpio->par_cs |= GPIO_PAR_CS1_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
#endif
icache_enable();
}
/* initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
rtcex->gocu = CONFIG_SYS_RTC_CNT;
rtcex->gocl = CONFIG_SYS_RTC_SETUP;
#endif
#ifdef CONFIG_MCFFEC
if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
ccm->misccr |= CCM_MISCCR_FECM;
else
ccm->misccr &= ~CCM_MISCCR_FECM;
#endif
return (0);
}
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
gpio->par_simp1h &=
~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
gpio->par_simp1h |=
(GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
gpio->par_ssih &=
~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
gpio->par_ssih |=
(GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
#endif
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
gpio->par_dspih &=
~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
gpio->par_dspih |=
(GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_fec |=
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
} else {
gpio->par_fec |=
GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_fec &=
~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
} else {
gpio->par_fec &=
~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
}
}
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_MCF5301x */
#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
@ -63,13 +235,15 @@ void cpu_init_f(void)
/* Port configuration */
gpio->par_cs = 0;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
@ -77,28 +251,32 @@ void cpu_init_f(void)
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
@ -139,3 +317,22 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
gpio->par_feci2c |=
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
} else {
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
#endif
#endif /* CONFIG_MCF532x */

121
cpu/mcf532x/speed.c
View File

@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
#define MIN_FSYS 58333 /* KHz */
#ifdef CONFIG_MCF5301x
#define FREF 20000 /* KHz */
#define MAX_MFD 63 /* Multiplier */
#define MIN_MFD 0 /* Multiplier */
#define USBDIV 8
/* Low Power Divider specifications */
#define MIN_LPD (0) /* Divider (not encoded) */
#define MAX_LPD (15) /* Divider (not encoded) */
#define DEFAULT_LPD (0) /* Divider (not encoded) */
#endif
#ifdef CONFIG_MCF532x
#define FREF 16000 /* KHz */
#define MAX_MFD 135 /* Multiplier */
#define MIN_MFD 88 /* Multiplier */
#define BUSDIV 6 /* Divider */
/*
* Low Power Divider specifications
*/
/* Low Power Divider specifications */
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
#endif
/*
* Get the value of the current system clock
*
* Parameters:
* none
*
* Return Value:
* The current output system frequency
*/
#define BUSDIV 6 /* Divider */
/* Get the value of the current system clock */
int get_sys_clock(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@ -65,9 +72,23 @@ int get_sys_clock(void)
/* Test to see if device is in LIMP mode */
if (ccm->misccr & CCM_MISCCR_LIMP) {
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
#ifdef CONFIG_MCF5301x
return (FREF / (3 * (1 << divider)));
#endif
#ifdef CONFIG_MCF532x
return (FREF / (2 << divider));
#endif
} else {
#ifdef CONFIG_MCF5301x
u32 pfdr = (pll->pcr & 0x3F) + 1;
u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
return (((FREF * pfdr) / refdiv) / busdiv);
#endif
#ifdef CONFIG_MCF532x
return ((FREF * pll->pfdr) / (BUSDIV * 4));
#endif
}
}
@ -92,7 +113,7 @@ int clock_limp(int div)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
@ -102,15 +123,7 @@ int clock_limp(int div)
return (FREF / (3 * (1 << div)));
}
/*
* Exit low power LIMP mode
*
* Parameters:
* div Desired system frequency divider
*
* Return Value:
* The resulting output system frequency
*/
/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@ -139,7 +152,10 @@ int clock_exit_limp(void)
*/
int clock_pll(int fsys, int flags)
{
#ifdef CONFIG_MCF532x
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
#endif
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) {
/* Return current PLL output */
#ifdef CONFIG_MCF5301x
u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
mfd = (pll->pcr & 0x3F) + 1;
return (fref * mfd) / busdiv;
#endif
#ifdef CONFIG_MCF532x
mfd = pll->pfdr;
return (fref * mfd / (BUSDIV * 4));
#endif
}
/* Check bounds of requested system clock */
@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags)
if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
/* Multiplying by 100 when calculating the temp value,
and then dividing by 100 to calculate the mfd allows
for exact values without needing to include floating
point libraries. */
/*
* Multiplying by 100 when calculating the temp value,
* and then dividing by 100 to calculate the mfd allows
* for exact values without needing to include floating
* point libraries.
*/
temp = (100 * fsys) / fref;
#ifdef CONFIG_MCF5301x
mfd = (BUSDIV * temp) / 100;
/* Determine the output frequency for selected values */
fout = ((fref * mfd) / BUSDIV);
#endif
#ifdef CONFIG_MCF532x
mfd = (4 * BUSDIV * temp) / 100;
/* Determine the output frequency for selected values */
fout = ((fref * mfd) / (BUSDIV * 4));
#endif
/*
* Check to see if the SDRAM has already been initialized.
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
if (sdram->ctrl & SDRAMC_SDCR_REF)
sdram->ctrl &= ~SDRAMC_SDCR_CKE;
/*
* Initialize the PLL to generate the new system clock frequency.
@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags)
/* Enter LIMP mode */
clock_limp(DEFAULT_LPD);
#ifdef CONFIG_MCF5301x
pll->pdr =
PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
PLL_PDR_OUTDIV2(BUSDIV - 1) |
PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
PLL_PDR_OUTDIV4(USBDIV - 1);
pll->pcr &= PLL_PCR_FBDIV_MASK;
pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
#endif
#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
pll->pfdr = mfd;
#endif
/* Exit LIMP mode */
clock_exit_limp();
/*
* Return the SDRAM to normal operation if it is in use.
*/
/* Return the SDRAM to normal operation if it is in use. */
if (sdram->ctrl & SDRAMC_SDCR_REF)
sdram->ctrl |= SDRAMC_SDCR_CKE;
/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
#ifdef CONFIG_MCF532x
/*
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
#endif
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++) ;
@ -205,9 +258,7 @@ int clock_pll(int fsys, int flags)
return fout;
}
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;

11
cpu/mcf532x/start.S
View File

@ -2,6 +2,9 @@
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -140,6 +143,14 @@ _start:
movec %d0, %ACR0
movec %d0, %ACR1
#ifdef CONFIG_MCF5301x
move.l #(0xFC0a0010), %a0
move.w (%a0), %d0
and.l %d0, 0xEFFF
move.w %d0, (%a0)
#endif
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1

34
cpu/mcf5445x/cpu_init.c
View File

@ -27,10 +27,15 @@
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/rtc.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif
/*
* Breath some life into the CPU...
*
@ -139,3 +144,30 @@ void uart_port_conf(void)
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
else
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
else
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
}
return 0;
}
#endif

27
cpu/mcf547x_8x/cpu_init.c
View File

@ -29,6 +29,12 @@
#include <MCD_dma.h>
#include <asm/immap.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fsl_mcdmafec.h>
#endif
/*
* Breath some life into the CPU...
*
@ -130,3 +136,24 @@ void uart_port_conf(void)
*pscsicr &= 0xF8;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq |= 0xF000;
else
gpio->par_feci2cirq |= 0x0FC0;
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
gpio->par_feci2cirq &= 0x0FFF;
else
gpio->par_feci2cirq &= 0xF03F;
}
return 0;
}
#endif

181
doc/README.m53017evb Normal file
View File

@ -0,0 +1,181 @@
Freescale MCF53017EVB ColdFire Development Board
================================================
TsiChung Liew(Tsi-Chung.Liew@freescale.com)
Created 10/22/08
===========================================
Changed files:
==============
- board/freescale/m53017evb/m53017evb.c Dram setup
- board/freescale/m53017evb/mii.c Mii access
- board/freescale/m53017evb/Makefile Makefile
- board/freescale/m53017evb/config.mk config make
- board/freescale/m53017evb/u-boot.lds Linker description
- cpu/mcf532x/cpu.c cpu specific code
- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
- cpu/mcf532x/interrupts.c cpu specific interrupt support
- cpu/mcf532x/speed.c system, flexbus, and cpu clock
- cpu/mcf532x/Makefile Makefile
- cpu/mcf532x/config.mk config make
- cpu/mcf532x/start.S start up assembly code
- doc/README.m53017evb This readme file
- drivers/net/mcffec.c ColdFire common FEC driver
- drivers/net/mcfmii.c ColdFire common Mii driver
- drivers/serial/mcfuart.c ColdFire common UART driver
- drivers/rtc/mcfrtc.c Realtime clock Driver
- include/asm-m68k/bitops.h Bit operation function export
- include/asm-m68k/byteorder.h Byte order functions
- include/asm-m68k/fec.h FEC structure and definition
- include/asm-m68k/fsl_i2c.h I2C structure and definition
- include/asm-m68k/global_data.h Global data structure
- include/asm-m68k/immap.h ColdFire specific header file and driver macros
- include/asm-m68k/immap_5301x.h mcf5301x specific header file
- include/asm-m68k/io.h io functions
- include/asm-m68k/m532x.h mcf5301x specific header file
- include/asm-m68k/posix_types.h Posix
- include/asm-m68k/processor.h header file
- include/asm-m68k/ptrace.h Exception structure
- include/asm-m68k/rtc.h Realtime clock header file
- include/asm-m68k/string.h String function export
- include/asm-m68k/timer.h Timer structure and definition
- include/asm-m68k/types.h Data types definition
- include/asm-m68k/uart.h Uart structure and definition
- include/asm-m68k/u-boot.h u-boot structure
- include/configs/M53017EVB.h Board specific configuration file
- lib_m68k/board.c board init function
- lib_m68k/cache.c
- lib_m68k/interrupts Coldfire common interrupt functions
- lib_m68k/m68k_linux.c
- lib_m68k/time.c Timer functions (Dma timer and PIT)
- lib_m68k/traps.c Exception init code
1 MCF5301x specific Options/Settings
====================================
1.1 pre-loader is no longer suppoer in thie coldfire family
1.2 Configuration settings for M53017EVB Development Board
CONFIG_MCF5301x -- define for all MCF5301x CPUs
CONFIG_M53015 -- define for MCF53015 CPUs
CONFIG_M53017EVB -- define for M53017EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver
CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
RTC_DEBUG -- define to show RTC debug message
CONFIG_CMD_DATE -- enable to use date feature in u-boot
CONFIG_MCFFEC -- define to use common CF FEC driver
CONFIG_NET_MULTI -- define to use multi FEC in u-boot
CONFIG_MII -- enable to use MII driver
CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SOFT_I2C -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_SYS_IMMR -- define for MBAR offset
CONFIG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
2.1. System memory map:
Flash: 0x00000000-0x3FFFFFFF (1024MB)
DDR: 0x40000000-0x7FFFFFFF (1024MB)
SRAM: 0x80000000-0x8FFFFFFF (256MB)
IP: 0xFC000000-0xFFFFFFFF (256MB)
2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
linux kernel, you can customize it based on your system requirements:
Flash0: 0x00000000-0x00FFFFFF (16MB)
DDR: 0x40000000-0x4FFFFFFF (256MB)
SRAM: 0x80000000-0x80007FFF (32KB)
IP: 0xFC000000-0xFC0FFFFF (64KB)
3. COMPILATION
==============
3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
uClinux version) from codesourcery.com was used. Download it from:
http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
3.2 Compilation
export CROSS_COMPILE=cross-compile-prefix
cd u-boot
make distclean
make M53017EVB_config
make
4. SCREEN DUMP
==============
4.1 M53017EVB Development board
(NOTE: May not show exactly the same)
U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
CPU: Freescale MCF53015 (Mask:76 Version:0)
CPU CLK 240 Mhz BUS CLK 80 Mhz
Board: Freescale M53017EVB
I2C: ready
DRAM: 64 MB
FLASH: 16 MB
In: serial
Out: serial
Err: serial
NAND: 16 MiB
Net: FEC0, FEC1
-> print
bootdelay=1
baudrate=115200
ethaddr=00:e0:0c:bc:e5:60
hostname=M53017EVB
netdev=eth0
loadaddr=40010000
u-boot=u-boot.bin
load=tftp ${loadaddr) ${u-boot}
upd=run load; run prog
prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
gatewayip=192.168.1.1
netmask=255.255.255.0
ipaddr=192.168.1.3
serverip=192.168.1.2
stdin=serial
stdout=serial
stderr=serial
mem=65024k
Environment size: 437/4092 bytes
->

79
include/asm-m68k/coldfire/ata.h Normal file
View File

@ -0,0 +1,79 @@
/*
* ATA Internal Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ATA_H__
#define __ATA_H__
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
#endif /* __ATA_H__ */

15
include/asm-m68k/coldfire/dspi.h
View File

@ -46,15 +46,14 @@ typedef struct dspi {
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
#ifdef CONFIG_MCF547x_8x
u32 dtfdr[4];
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
u32 drfdr[4];
#else
u32 dtfdr[16];
u32 drfdr[16];
#endif
} dspi_t;
/* Bit definitions and macros for DMCR */

139
include/asm-m68k/coldfire/eport.h Normal file
View File

@ -0,0 +1,139 @@
/*
* Edge Port Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EPORT_H__
#define __EPORT_H__
/* Edge Port Module (EPORT) */
typedef struct eport {
#ifdef CONFIG_MCF547x_8x
u16 par; /* 0x00 */
u16 res0; /* 0x02 */
u8 ddr; /* 0x04 */
u8 ier; /* 0x05 */
u16 res1; /* 0x06 */
u8 dr; /* 0x08 */
u8 pdr; /* 0x09 */
u16 res2; /* 0x0A */
u8 fr; /* 0x0C */
u8 res3[3]; /* 0x0D */
#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
u8 dr; /* 0x04 Data */
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
#endif
} eport_t;
/* EPPAR */
#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_PAR_LEVEL (0)
#define EPORT_PAR_RISING (1)
#define EPORT_PAR_FALLING (2)
#define EPORT_PAR_BOTH (3)
#define EPORT_PAR_EPPA7_LEVEL (0x0000)
#define EPORT_PAR_EPPA7_RISING (0x4000)
#define EPORT_PAR_EPPA7_FALLING (0x8000)
#define EPORT_PAR_EPPA7_BOTH (0xC000)
#define EPORT_PAR_EPPA6_LEVEL (0x0000)
#define EPORT_PAR_EPPA6_RISING (0x1000)
#define EPORT_PAR_EPPA6_FALLING (0x2000)
#define EPORT_PAR_EPPA6_BOTH (0x3000)
#define EPORT_PAR_EPPA5_LEVEL (0x0000)
#define EPORT_PAR_EPPA5_RISING (0x0400)
#define EPORT_PAR_EPPA5_FALLING (0x0800)
#define EPORT_PAR_EPPA5_BOTH (0x0C00)
#define EPORT_PAR_EPPA4_LEVEL (0x0000)
#define EPORT_PAR_EPPA4_RISING (0x0100)
#define EPORT_PAR_EPPA4_FALLING (0x0200)
#define EPORT_PAR_EPPA4_BOTH (0x0300)
#define EPORT_PAR_EPPA3_LEVEL (0x0000)
#define EPORT_PAR_EPPA3_RISING (0x0040)
#define EPORT_PAR_EPPA3_FALLING (0x0080)
#define EPORT_PAR_EPPA3_BOTH (0x00C0)
#define EPORT_PAR_EPPA2_LEVEL (0x0000)
#define EPORT_PAR_EPPA2_RISING (0x0010)
#define EPORT_PAR_EPPA2_FALLING (0x0020)
#define EPORT_PAR_EPPA2_BOTH (0x0030)
#define EPORT_PAR_EPPA1_LEVEL (0x0000)
#define EPORT_PAR_EPPA1_RISING (0x0004)
#define EPORT_PAR_EPPA1_FALLING (0x0008)
#define EPORT_PAR_EPPA1_BOTH (0x000C)
/* EPDDR */
#define EPORT_DDR_EPDD1 (0x02)
#define EPORT_DDR_EPDD2 (0x04)
#define EPORT_DDR_EPDD3 (0x08)
#define EPORT_DDR_EPDD4 (0x10)
#define EPORT_DDR_EPDD5 (0x20)
#define EPORT_DDR_EPDD6 (0x40)
#define EPORT_DDR_EPDD7 (0x80)
/* EPIER */
#define EPORT_IER_EPIE1 (0x02)
#define EPORT_IER_EPIE2 (0x04)
#define EPORT_IER_EPIE3 (0x08)
#define EPORT_IER_EPIE4 (0x10)
#define EPORT_IER_EPIE5 (0x20)
#define EPORT_IER_EPIE6 (0x40)
#define EPORT_IER_EPIE7 (0x80)
/* EPDR */
#define EPORT_DR_EPD1 (0x02)
#define EPORT_DR_EPD2 (0x04)
#define EPORT_DR_EPD3 (0x08)
#define EPORT_DR_EPD4 (0x10)
#define EPORT_DR_EPD5 (0x20)
#define EPORT_DR_EPD6 (0x40)
#define EPORT_DR_EPD7 (0x80)
/* EPPDR */
#define EPORT_PDR_EPPD1 (0x02)
#define EPORT_PDR_EPPD2 (0x04)
#define EPORT_PDR_EPPD3 (0x08)
#define EPORT_PDR_EPPD4 (0x10)
#define EPORT_PDR_EPPD5 (0x20)
#define EPORT_PDR_EPPD6 (0x40)
#define EPORT_PDR_EPPD7 (0x80)
/* EPFR */
#define EPORT_FR_EPF1 (0x02)
#define EPORT_FR_EPF2 (0x04)
#define EPORT_FR_EPF3 (0x08)
#define EPORT_FR_EPF4 (0x10)
#define EPORT_FR_EPF5 (0x20)
#define EPORT_FR_EPF6 (0x40)
#define EPORT_FR_EPF7 (0x80)
#endif /* __EPORT_H__ */

96
include/asm-m68k/coldfire/flexbus.h
View File

@ -31,33 +31,36 @@
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
u32 csar4; /* Chip-select Address Register */
u32 csmr4; /* Chip-select Mask Register */
u32 cscr4; /* Chip-select Control Register */
u32 csar5; /* Chip-select Address Register */
u32 csmr5; /* Chip-select Mask Register */
u32 cscr5; /* Chip-select Control Register */
u32 csar0; /* Chip-select Address */
u32 csmr0; /* Chip-select Mask */
u32 cscr0; /* Chip-select Control */
u32 csar1;
u32 csmr1;
u32 cscr1;
u32 csar2;
u32 csmr2;
u32 cscr2;
u32 csar3;
u32 csmr3;
u32 cscr3;
u32 csar4;
u32 csmr4;
u32 cscr4;
u32 csar5;
u32 csmr5;
u32 cscr5;
u32 csar6;
u32 csmr6;
u32 cscr6;
u32 csar7;
u32 csmr7;
u32 cscr7;
} fbcs_t;
/* Bit definitions and macros for CSAR group */
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
/* Bit definitions and macros for CSMR group */
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
#define FBCS_CSMR_BAM_MASK (0x0000FFFF)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
@ -78,21 +81,40 @@ typedef struct fbcs {
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for CSCR group */
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
#ifdef CONFIG_M5249
#define FBCS_CSMR_WP (0x00000080)
#define FBCS_CSMR_AM (0x00000040)
#define FBCS_CSMR_CI (0x00000020)
#define FBCS_CSMR_SC (0x00000010)
#define FBCS_CSMR_SD (0x00000008)
#define FBCS_CSMR_UC (0x00000004)
#define FBCS_CSMR_UD (0x00000002)
#else
#define FBCS_CSMR_WP (0x00000100)
#endif
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
#define FBCS_CSCR_SWSEN (0x00800000)
#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
#define FBCS_CSCR_WS_MASK (0xFFFF03FF)
#define FBCS_CSCR_SBM (0x00000200)
#define FBCS_CSCR_AA (0x00000100)
#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
#define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
#define FBCS_CSCR_BEM (0x00000020)
#define FBCS_CSCR_BSTR (0x00000010)
#define FBCS_CSCR_BSTW (0x00000008)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_32 (0x00000000)
#endif /* __FLEXBUS_H */

219
include/asm-m68k/coldfire/flexcan.h Normal file
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@ -0,0 +1,219 @@
/*
* Flex CAN Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FLEXCAN_H__
#define __FLEXCAN_H__
/* FlexCan Message Buffer */
typedef struct can_msgbuf_ctrl {
#ifdef CONFIG_M5282
u8 tmstamp; /* 0x00 Timestamp */
u8 ctrl; /* 0x01 Control */
u16 idh; /* 0x02 ID High */
u16 idl; /* 0x04 ID High */
u8 data[8]; /* 0x06 8 Byte Data Field */
u16 res; /* 0x0E */
#else
u16 ctrl; /* 0x00 Control/Status */
u16 tmstamp; /* 0x02 Timestamp */
u32 id; /* 0x04 Identifier */
u8 data[8]; /* 0x08 8 Byte Data Field */
#endif
} can_msg_t;
#ifdef CONFIG_M5282
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
/* MSGBUF ID */
#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_IDH_SRR (0x0010)
#define CAN_MSGBUF_IDH_IDE (0x0080)
#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
#define CAN_MSGBUF_IDL_RTR (0x0001)
#else
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
#define CAN_MSGBUF_CTRL_SRR (0x0040)
#define CAN_MSGBUF_CTRL_IDE (0x0020)
#define CAN_MSGBUF_CTRL_RTR (0x0010)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
/* MSGBUF ID */
#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
#endif
/* FlexCan module */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration */
u32 ctrl; /* 0x04 Control */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmsk; /* 0x10 Rx Global Mask */
u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
#ifdef CONFIG_M5282
u32 res2; /* 0x1C */
u16 errstat; /* 0x20 Error and status */
u16 imsk; /* 0x22 Interrupt Mask */
u16 iflag; /* 0x24 Interrupt Flag */
u16 errcnt; /* 0x26 Error Counter */
u32 res3[3]; /* 0x28 - 0x33 */
#else
u16 res2; /* 0x1C */
u16 errcnt; /* 0x1E Error Counter */
u16 res3; /* 0x20 */
u16 errstat; /* 0x22 Error and status */
u32 res4; /* 0x24 */
u32 imsk; /* 0x28 Interrupt Mask */
u32 res5; /* 0x2C */
u16 iflag; /* 0x30 Interrupt Flag */
#endif
u32 res6[19]; /* 0x34 - 0x7F */
void *msgbuf; /* 0x80 Message Buffer 0-15 */
} can_t;
/* MCR */
#define CAN_MCR_MDIS (0x80000000)
#define CAN_MCR_FRZ (0x40000000)
#define CAN_MCR_HALT (0x10000000)
#define CAN_MCR_NORDY (0x08000000)
#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
#define CAN_MCR_SOFTRST (0x02000000)
#define CAN_MCR_FRZACK (0x01000000)
#define CAN_MCR_SUPV (0x00800000)
#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
#define CAN_MCR_APS (0x00200000) /* 5282 */
#define CAN_MCR_LPMACK (0x00100000)
#define CAN_MCF_BCC (0x00010000)
#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
/* CTRL */
#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
#define CAN_CTRL_BOFFMSK (0x00008000)
#define CAN_CTRL_ERRMSK (0x00004000)
#define CAN_CTRL_CLKSRC (0x00002000)
#define CAN_CTRL_LPB (0x00001000)
#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
#define CAN_CTRL_SMP (0x00000080)
#define CAN_CTRL_BOFFREC (0x00000040)
#define CAN_CTRL_TSYNC (0x00000020)
#define CAN_CTRL_LBUF (0x00000010)
#define CAN_CTRL_LOM (0x00000008)
#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
/* TIMER */
/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
#define CAN_TIMER(x) ((x) & 0xFFFF)
#define CAN_TIMER_MASK (0xFFFF0000)
/* RXGMASK */
#ifdef CONFIG_M5282
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
#else
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
#endif
/* ERRCNT */
#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
/* ERRSTAT */
#define CAN_ERRSTAT_BITERR1 (0x8000)
#define CAN_ERRSTAT_BITERR0 (0x4000)
#define CAN_ERRSTAT_ACKERR (0x2000)
#define CAN_ERRSTAT_CRCERR (0x1000)
#define CAN_ERRSTAT_FRMERR (0x0800)
#define CAN_ERRSTAT_STFERR (0x0400)
#define CAN_ERRSTAT_TXWRN (0x0200)
#define CAN_ERRSTAT_RXWRN (0x0100)
#define CAN_ERRSTAT_IDLE (0x0080)
#define CAN_ERRSTAT_TXRX (0x0040)
#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
#ifdef CONFIG_M5282
#define CAN_ERRSTAT_BOFFINT (0x0004)
#define CAN_ERRSTAT_ERRINT (0x0002)
#else
#define CAN_ERRSTAT_ERRINT (0x0004)
#define CAN_ERRSTAT_BOFFINT (0x0002)
#define CAN_ERRSTAT_WAKEINT (0x0001)
#endif
/* IMASK */
#ifdef CONFIG_M5253
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#else
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#endif
/* IFLAG */
#ifdef CONFIG_M5253
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#else
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#endif
#endif /* __FLEXCAN_H__ */

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/*
* Interrupt Controller Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __INTCTRL_H__
#define __INTCTRL_H__
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x) || defined(CONFIG_M548x)
# define CONFIG_SYS_CF_INTC_REG1
#endif
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending High */
u32 iprl0; /* 0x04 Pending Low */
u32 imrh0; /* 0x08 Mask High */
u32 imrl0; /* 0x0C Mask Low */
u32 frch0; /* 0x10 Force High */
u32 frcl0; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
#endif
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 L1iack0; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 L2iack0; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 L3iack0; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 L4iack0; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 L5iack0; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 L6iack0; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 L7iack0; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending High */
u32 iprl1; /* 0x04 Pending Low */
u32 imrh1; /* 0x08 Mask High */
u32 imrl1; /* 0x0C Mask Low */
u32 frch1; /* 0x10 Force High */
u32 frcl1; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
#endif
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 L1iack1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 L2iack1; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 L3iack1; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 L4iack1; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 L5iack1; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 L6iack1; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 L7iack1; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0x00 Global Software Interrupt ack */
u8 res0[0x3];
u8 gl1iack; /* 0x04 */
u8 resv1[0x3];
u8 gl2iack; /* 0x08 */
u8 res2[0x3];
u8 gl3iack; /* 0x0C */
u8 res3[0x3];
u8 gl4iack; /* 0x10 */
u8 res4[0x3];
u8 gl5iack; /* 0x14 */
u8 res5[0x3];
u8 gl6iack; /* 0x18 */
u8 res6[0x3];
u8 gl7iack; /* 0x1C */
u8 res7[0x3];
} intgack_t;
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IMRLn_MASKALL (0x00000001)
#define INTC_IRLR(x) (((x) & 0x7F) << 1)
#define INTC_IRLR_MASK (0x01)
#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4)
#define INTC_IACKLPR_LVL_MASK (0x8F)
#define INTC_IACKLPR_PRI(x) ((x) & 0x0F)
#define INTC_IACKLPR_PRI_MASK (0xF0)
#if defined(CONFIG_SYS_CF_INTC_REG1)
#define INTC_ICR_IL(x) (((x) & 0x07) << 3)
#define INTC_ICR_IL_MASK (0xC7)
#define INTC_ICR_IP(x) ((x) & 0x07)
#define INTC_ICR_IP_MASK (0xF8)
#else
#define INTC_ICR_IL(x) ((x) & 0x07)
#define INTC_ICR_IL_MASK (0xF8)
#endif
#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_SIMR_ALL (0x40)
#define INTC_SIMR(x) ((x) & 0x3F)
#define INTC_SIMR_MASK (0x80)
#define INTC_CIMR_ALL (0x40)
#define INTC_CIMR(x) ((x) & 0x3F)
#define INTC_CIMR_MASK (0x80)
#define INTC_CLMASK(x) ((x) & 0x0F)
#define INTC_CLMASK_MASK (0xF0)
#define INTC_SLMASK(x) ((x) & 0x0F)
#define INTC_SLMASK_MASK (0xF0)
#endif /* __INTCTRL_H__ */

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include/asm-m68k/coldfire/mdha.h Normal file
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/*
* Message Digest Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MDHA_H__
#define __MDHA_H__
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mr; /* 0x00 MDHA Mode */
u32 cr; /* 0x04 Control */
u32 cmd; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 isr; /* 0x10 Interrupt Status */
u32 imr; /* 0x14 Interrupt Mask */
u32 dsz; /* 0x1C Data Size */
u32 inp; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mda0; /* 0x30 Message Digest AO */
u32 mdb0; /* 0x34 Message Digest BO */
u32 mdc0; /* 0x38 Message Digest CO */
u32 mdd0; /* 0x3C Message Digest DO */
u32 mde0; /* 0x40 Message Digest EO */
u32 mdsz; /* 0x44 Message Data Size */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 */
u32 mdb1; /* 0x74 Message Digest B1 */
u32 mdc1; /* 0x78 Message Digest C1 */
u32 mdd1; /* 0x7C Message Digest D1 */
u32 mde1; /* 0x80 Message Digest E1 */
} mdha_t;
#define MDHA_MR_SSL (0x00000400)
#define MDHA_MR_MACFUL (0x00000200)
#define MDHA_MR_SWAP (0x00000100)
#define MDHA_MR_OPAD (0x00000080)
#define MDHA_MR_IPAD (0x00000040)
#define MDHA_MR_INIT (0x00000020)
#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
#define MDHA_MR_MAC_EHMAC (0x00000010)
#define MDHA_MR_MAC_HMAC (0x00000008)
#define MDHA_MR_MAC_NONE (0x00000000)
#define MDHA_MR_PDATA (0x00000004)
#define MDHA_MR_ALG (0x00000001)
#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
#define MDHA_CR_END (0x00000004) /* 532x */
#define MDHA_CR_DMA (0x00000002) /* 532x */
#define MDHA_CR_IE (0x00000001)
#define MDHA_CMD_GO (0x00000008)
#define MDHA_CMD_CI (0x00000004)
#define MDHA_CMD_RI (0x00000001)
#define MDHA_CMD_SWR (0x00000001)
#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define MDHA_SR_IFL_MASK (0xFF00FFFF)
#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
#define MDHA_SR_APD_MASK (0xFFFF1FFF)
#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
#define MDHA_SR_FS_MASK (0xFFFFF8FF)
#define MDHA_SR_GNW (0x00000080)
#define MDHA_SR_HSH (0x00000040)
#define MDHA_SR_BUSY (0x00000010)
#define MDHA_SR_RD (0x00000008)
#define MDHA_SR_ERR (0x00000004)
#define MDHA_SR_DONE (0x00000002)
#define MDHA_SR_INT (0x00000001)
#define MDHA_ISR_DRL (0x00000400) /* 532x */
#define MDHA_ISR_GTDS (0x00000200)
#define MDHA_ISR_ERE (0x00000100)
#define MDHA_ISR_RMDP (0x00000080)
#define MDHA_ISR_DSE (0x00000020)
#define MDHA_ISR_IME (0x00000010)
#define MDHA_ISR_NEIF (0x00000004)
#define MDHA_ISR_IFO (0x00000001)
#endif /* __MDHA_H__ */

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include/asm-m68k/coldfire/pwm.h Normal file
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/*
* Pulse Width Modulation Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ATA_H__
#define __ATA_H__
/* Pulse Width Modulation (PWM) */
typedef struct pwm_ctrl {
#ifdef CONFIG_M5272
u8 cr0;
u8 res1[3];
u8 cr1;
u8 res2[3];
u8 cr2;
u8 res3[7];
u8 pwr0;
u8 res4[3];
u8 pwr1;
u8 res5[3];
u8 pwr2;
u8 res6[7];
#else
u8 en; /* 0x00 PWM Enable */
u8 pol; /* 0x01 Polarity */
u8 clk; /* 0x02 Clock Select */
u8 prclk; /* 0x03 Prescale Clock Select */
u8 cae; /* 0x04 Center Align Enable */
u8 ctl; /* 0x05 Control */
u16 res1; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A */
u8 sclb; /* 0x09 Scale B */
u16 res2; /* 0x0A - 0x0B */
#ifdef CONFIG_M5275
u8 cnt[4]; /* 0x0C Channel n Counter */
u16 res3; /* 0x10 - 0x11 */
u8 per[4]; /* 0x14 Channel n Period */
u16 res4; /* 0x16 - 0x17 */
u8 dty[4]; /* 0x18 Channel n Duty */
#else
u8 cnt[8]; /* 0x0C Channel n Counter */
u8 per[8]; /* 0x14 Channel n Period */
u8 dty[8]; /* 0x1C Channel n Duty */
u8 sdn; /* 0x24 Shutdown */
u8 res3[3]; /* 0x25 - 0x27 */
#endif /* CONFIG_M5275 */
#endif /* CONFIG_M5272 */
} pwm_t;
#ifdef CONFIG_M5272
#define PWM_CR_EN (0x80)
#define PWM_CR_FRC1 (0x40)
#define PWM_CR_LVL (0x20)
#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
#define PWM_CR_CLKSEL_MASK (0xF0)
#else
#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
#define PWM_EN_PWMEn_MASK (0xF0)
#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
#define PWM_POL_PPOLn_MASK (0xF0)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
#define PWM_PRCLK_PCKB_MASK (0x8F)
#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
#define PWM_PRCLK_PCKA_MASK (0xF8)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_CTL_CON67 (0x80)
#define PWM_CTL_CON45 (0x40)
#define PWM_CTL_CON23 (0x20)
#define PWM_CTL_CON01 (0x10)
#define PWM_CTL_PSWAR (0x08)
#define PWM_CTL_PFRZ (0x04)
#define PWM_SDN_IF (0x80)
#define PWM_SDN_IE (0x40)
#define PWM_SDN_RESTART (0x20)
#define PWM_SDN_LVL (0x10)
#define PWM_SDN_PWM7IN (0x04)
#define PWM_SDN_PWM7IL (0x02)
#define PWM_SDN_SDNEN (0x01)
#endif /* CONFIG_M5272 */
#endif /* __ATA_H__ */

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include/asm-m68k/coldfire/qspi.h Normal file
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/*
* Queue Serial Peripheral Interface Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __QSPI_H__
#define __QSPI_H__
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 mr; /* 0x00 Mode */
u16 res1;
u16 dlyr; /* 0x04 Delay */
u16 res2;
u16 wr; /* 0x08 Wrap */
u16 res3;
u16 ir; /* 0x0C Interrupt */
u16 res4;
u16 ar; /* 0x10 Address */
u16 res5;
u16 dr; /* 0x14 Data */
u16 res6;
} qspi_t;
/* MR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_BITS_MASK (0xC3FF)
#define QSPI_QMR_BITS_8 (0x2000)
#define QSPI_QMR_BITS_9 (0x2400)
#define QSPI_QMR_BITS_10 (0x2800)
#define QSPI_QMR_BITS_11 (0x2C00)
#define QSPI_QMR_BITS_12 (0x3000)
#define QSPI_QMR_BITS_13 (0x3400)
#define QSPI_QMR_BITS_14 (0x3800)
#define QSPI_QMR_BITS_15 (0x3C00)
#define QSPI_QMR_BITS_16 (0x0000)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
#define QSPI_QMR_BAUD_MASK (0xFF00)
/* DLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_QCD_MASK (0x80FF)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
#define QSPI_QDLYR_DTL_MASK (0xFF00)
/* WR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_ENDQP_MASK (0xF0FF)
#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
#define QSPI_QWR_CPTQP_MASK (0xFF0F)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
#define QSPI_QWR_NEWQP_MASK (0xFFF0)
/* IR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* AR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
#define QSPI_QAR_ADDR_MASK (0xFFC0)
#define QSPI_QAR_TRANS (0x0000)
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* DR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
#endif /* __QSPI_H__ */

52
include/asm-m68k/coldfire/rng.h Normal file
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@ -0,0 +1,52 @@
/*
* RNG Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __RNG_H__
#define __RNG_H__
/* Random Number Generator */
typedef struct rng_ctrl {
u32 cr; /* 0x00 Control */
u32 sr; /* 0x04 Status */
u32 er; /* 0x08 Entropy */
u32 out; /* 0x0C Output FIFO */
} rng_t;
#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */
#define RNG_CR_CI (0x00000008) /* Clear interrupt */
#define RNG_CR_IM (0x00000004) /* Interrupt mask */
#define RNG_CR_HA (0x00000002) /* High assurance */
#define RNG_CR_GO (0x00000001) /* Go bit */
#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16)
#define RNG_SR_OFS_MASK (0xFF00FFFF)
#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8)
#define RNG_SR_OFL_MASK (0xFFFF00FF)
#define RNG_SR_EI (0x00000008)
#define RNG_SR_FUF (0x00000004)
#define RNG_SR_LRS (0x00000002)
#define RNG_SR_SV (0x00000001)
#endif /* __RNG_H__ */

121
include/asm-m68k/coldfire/skha.h Normal file
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@ -0,0 +1,121 @@
/*
* Symmetric Key Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SKHA_H__
#define __SKHA_H__
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode */
u32 cr; /* 0x04 Control */
u32 cmr; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 esr; /* 0x10 Error Status */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size */
u32 dsr; /* 0x1C Data Size */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data 1 */
u32 kdr2; /* 0x34 Key Data 2 */
u32 kdr3; /* 0x38 Key Data 3 */
u32 kdr4; /* 0x3C Key Data 4 */
u32 kdr5; /* 0x40 Key Data 5 */
u32 kdr6; /* 0x44 Key Data 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
} skha_t;
#ifdef CONFIG_MCF532x
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
#define SKHA_MODE_DKP (0x00000100)
#else
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
#define SKHA_MODE_DKP (0x00000080)
#endif
#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
#define SKHA_MODE_DIR (0x00000004)
#define SKHA_MODE_ALG(x) ((x) & 0x03)
#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
#define SHKA_CR_END (0x00000008)
#define SHKA_CR_ODMA (0x00000004)
#define SHKA_CR_IDMA (0x00000002)
#define SKHA_CR_IE (0x00000001)
#define SKHA_CMR_GO (0x00000008)
#define SKHA_CMR_CI (0x00000004)
#define SKHA_CMR_RI (0x00000002)
#define SKHA_CMR_SWR (0x00000001)
#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
#define SKHA_SR_OFL_MASK (0x00FFFFFF)
#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define SKHA_SR_IFL_MASK (0xFF00FFFF)
#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
#define SKHA_SR_AESES_MASK (0xFFFF07FF)
#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
#define SKHA_SR_BUSY (0x00000010)
#define SKHA_SR_RD (0x00000008)
#define SKHA_SR_ERR (0x00000004)
#define SKHA_SR_DONE (0x00000002)
#define SKHA_SR_INT (0x00000001)
#define SHKA_ESE_DRL (0x00000800)
#define SKHA_ESR_KRE (0x00000400)
#define SKHA_ESR_KPE (0x00000200)
#define SKHA_ESR_ERE (0x00000100)
#define SKHA_ESR_RMDP (0x00000080)
#define SKHA_ESR_KSE (0x00000040)
#define SKHA_ESR_DSE (0x00000020)
#define SKHA_ESR_IME (0x00000010)
#define SKHA_ESR_NEOF (0x00000008)
#define SKHA_ESR_NEIF (0x00000004)
#define SKHA_ESR_OFU (0x00000002)
#define SKHA_ESR_IFO (0x00000001)
#define SKHA_KSR_SZ(x) ((x) & 0x3F)
#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
#endif /* __SKHA_H__ */

62
include/asm-m68k/coldfire/ssi.h
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@ -26,10 +26,6 @@
#ifndef __SSI_H__
#define __SSI_H__
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
@ -52,14 +48,10 @@ typedef struct ssi {
u32 rmask;
} ssi_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_MASK (0xFFFFFF9F)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
@ -69,7 +61,6 @@ typedef struct ssi {
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
@ -90,7 +81,6 @@ typedef struct ssi {
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
@ -115,7 +105,6 @@ typedef struct ssi {
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
@ -127,7 +116,6 @@ typedef struct ssi {
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
@ -138,38 +126,44 @@ typedef struct ssi {
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_PM(x) ((x)&0x000000FF)
#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
#define SSI_CCR_WL_MASK (0xFFFE1FFF)
#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
#define SSI_CCR_DC_MASK (0xFFFFE0FF)
#define SSI_CCR_PM(x) ((x) & 0xFF)
#define SSI_CCR_PM_MASK (0xFFFFFF00)
/* Bit definitions and macros for SSI_FCSR */
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
/* Bit definitions and macros for SSI_ACR */
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
/* Bit definitions and macros for SSI_ACADD */
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
/* Bit definitions and macros for SSI_ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
/* Bit definitions and macros for SSI_ATAG */
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
#endif /* __SSI_H__ */

12
include/asm-m68k/fec.h
View File

@ -351,4 +351,16 @@ typedef struct fec {
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
int fecpin_setclear(struct eth_device *dev, int setclear);
#ifdef CONFIG_SYS_DISCOVER_PHY
void __mii_init(void);
uint mii_send(uint mii_cmd);
int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int mcffec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif
#endif /* fec_h */

9
include/asm-m68k/fsl_mcdmafec.h
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@ -164,13 +164,4 @@ struct fec_info_dma {
#define FIFO_CTRL_UFMASK (0x00100000)
#define FIFO_CTRL_OFMASK (0x00080000)
int fecpin_setclear(struct eth_device *dev, int setclear);
void mii_init(void);
uint mii_send(uint mii_cmd);
int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int mcffec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif /* fsl_mcdmafec_h */

32
include/asm-m68k/immap.h
View File

@ -227,6 +227,38 @@
#endif
#endif /* CONFIG_M5282 */
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5301x */
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>

109
include/asm-m68k/immap_5227x.h
View File

@ -69,109 +69,14 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
@ -193,6 +98,12 @@ typedef struct ccm {
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
u32 res0[0x700]; /* 0x100 */
can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
} canex_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */

166
include/asm-m68k/immap_5235.h
View File

@ -63,6 +63,15 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
@ -104,141 +113,9 @@ typedef struct sdram_ctrl {
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
@ -356,23 +233,4 @@ typedef struct wdog_ctrl {
u16 sr; /* 0x06 Service register */
} wdog_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
#endif /* __IMMAP_5235__ */

4
include/asm-m68k/immap_5249.h
View File

@ -26,10 +26,14 @@
#define __IMMAP_5249__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/qspi.h>
#endif /* __IMMAP_5249__ */

65
include/asm-m68k/immap_5253.h
View File

@ -23,10 +23,11 @@
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
#ifndef __IMMAP_5253__
#define __IMMAP_5253__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
@ -39,57 +40,13 @@
#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
/*********************************************************************
* ATA Module (ATAC)
*********************************************************************/
#include <asm/coldfire/ata.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
/* Register read/write struct */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
typedef struct canex_ctrl {
can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */
} canex_t;
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
} atac_t;
#endif /* __IMMAP_5249__ */
#endif /* __IMMAP_5253__ */

39
include/asm-m68k/immap_5271.h
View File

@ -63,36 +63,13 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
#endif /* __IMMAP_5271__ */

34
include/asm-m68k/immap_5272.h
View File

@ -44,6 +44,8 @@
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
@ -104,38 +106,6 @@ typedef struct gpio_ctrl {
uchar res2[4];
} gpio_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
} pwm_t;
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;

120
include/asm-m68k/immap_5275.h
View File

@ -66,6 +66,15 @@
#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System configuration registers
*/
typedef struct sys_ctrl {
@ -109,51 +118,6 @@ typedef struct sdram_ctrl {
u32 sdbmr1;
} sdramctrl_t;
/* Chip select module registers, offset: 0x080
*/
typedef struct cs_ctlr {
u16 ar0;
u16 res1;
u32 mr0;
u16 res2;
u16 cr0;
u16 ar1;
u16 res3;
u32 mr1;
u16 res4;
u16 cr1;
u16 ar2;
u16 res5;
u32 mr2;
u16 res6;
u16 cr2;
u16 ar3;
u16 res7;
u32 mr3;
u16 res8;
u16 cr3;
u16 ar4;
u16 res9;
u32 mr4;
u16 res10;
u16 cr4;
u16 ar5;
u16 res11;
u32 mr5;
u16 res12;
u16 cr5;
u16 ar6;
u16 res13;
u32 mr6;
u16 res14;
u16 cr6;
u16 ar7;
u16 res15;
u32 mr7;
u16 res16;
u16 cr7;
} csctrl_t;
/* DMA module registers, offset 0x100
*/
typedef struct dma_ctrl {
@ -163,55 +127,6 @@ typedef struct dma_ctrl {
u32 dcr;
} dma_t;
/* QSPI module registers, offset 0x340
*/
typedef struct qspi_ctrl {
u16 qmr;
u8 res1[2];
u16 qdlyr;
u8 res2[2];
u16 qwr;
u8 res3[2];
u16 qir;
u8 res4[2];
u16 qar;
u8 res5[2];
u16 qdr;
u8 res6[2];
} qspi_t;
/* Interrupt module registers, offset 0xc00
*/
typedef struct int_ctrl {
u32 iprh0;
u32 iprl0;
u32 imrh0;
u32 imrl0;
u32 frch0;
u32 frcl0;
u8 irlr;
u8 iacklpr;
u8 res1[0x26];
u8 icr0[64]; /* No ICR0, done this way for readability */
u8 res2[0x60];
u8 swiack0;
u8 res3[3];
u8 Lniack0_1;
u8 res4[3];
u8 Lniack0_2;
u8 res5[3];
u8 Lniack0_3;
u8 res6[3];
u8 Lniack0_4;
u8 res7[3];
u8 Lniack0_5;
u8 res8[3];
u8 Lniack0_6;
u8 res9[3];
u8 Lniack0_7;
u8 res10[3];
} int0_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
@ -325,23 +240,6 @@ typedef struct gpio_ctrl {
} gpio_t;
/* PWM module registers
*/
typedef struct pwm_ctrl {
u8 pwcr0;
u8 res1[3];
u8 pwcr1;
u8 res2[3];
u8 pwcr2;
u8 res3[7];
u8 pwwd0;
u8 res4[3];
u8 pwwd1;
u8 res5[3];
u8 pwwd2;
u8 res6[7];
} pwm_t;
/* Watchdog registers
*/
typedef struct wdog_ctrl {

91
include/asm-m68k/immap_5282.h
View File

@ -62,6 +62,12 @@
#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/qspi.h>
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
@ -92,88 +98,9 @@ typedef struct scm_ctrl {
u16 res8;
} scm_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Clock Module registers */
typedef struct pll_ctrl {

324
include/asm-m68k/immap_5301x.h Normal file
View File

@ -0,0 +1,324 @@
/*
* MCF5301x Internal Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5301X__
#define __IMMAP_5301X__
#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
#include <asm/coldfire/rng.h>
#include <asm/rtc.h>
/* System Controller Module */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 Peripheral Access Ctrl A */
u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
u32 rsvd2[4];
u32 pacre; /* 0x40 Peripheral Access Ctrl E */
u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
} scm1_t;
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u8 bcr; /* 0x24 */
u8 rsvd6[74]; /* 0x25 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
/* PWM module */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable */
u8 pol; /* 0x01 Polarity */
u8 clk; /* 0x02 Clock Select */
u8 prclk; /* 0x03 Prescale Clock Select */
u8 cae; /* 0x04 Center Align Enable */
u8 ctl; /* 0x05 Ctrl */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A */
u8 sclb; /* 0x09 Scale B */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter */
u8 cnt1; /* 0x0D Channel 1 Counter */
u8 cnt2; /* 0x0E Channel 2 Counter */
u8 cnt3; /* 0x0F Channel 3 Counter */
u8 cnt4; /* 0x10 Channel 4 Counter */
u8 cnt5; /* 0x11 Channel 5 Counter */
u8 cnt6; /* 0x12 Channel 6 Counter */
u8 cnt7; /* 0x13 Channel 7 Counter */
u8 per0; /* 0x14 Channel 0 Period */
u8 per1; /* 0x15 Channel 1 Period */
u8 per2; /* 0x16 Channel 2 Period */
u8 per3; /* 0x17 Channel 3 Period */
u8 per4; /* 0x18 Channel 4 Period */
u8 per5; /* 0x19 Channel 5 Period */
u8 per6; /* 0x1A Channel 6 Period */
u8 per7; /* 0x1B Channel 7 Period */
u8 dty0; /* 0x1C Channel 0 Duty */
u8 dty1; /* 0x1D Channel 1 Duty */
u8 dty2; /* 0x1E Channel 2 Duty */
u8 dty3; /* 0x1F Channel 3 Duty */
u8 dty4; /* 0x20 Channel 4 Duty */
u8 dty5; /* 0x21 Channel 5 Duty */
u8 dty6; /* 0x22 Channel 6 Duty */
u8 dty7; /* 0x23 Channel 7 Duty */
u8 sdn; /* 0x24 Shutdown */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Chip configuration module */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
typedef struct ccm_ctrl {
u16 ccr; /* 0x00 Chip Cfg */
u16 res1; /* 0x02 */
u16 rcon; /* 0x04 Reset Cfg */
u16 cir; /* 0x06 Chip ID */
u32 res2; /* 0x08 */
u16 misccr; /* 0x0A Misc Ctrl */
u16 cdr; /* 0x0C Clock divider */
u16 uhcsr; /* 0x10 USB Host status */
u16 uocsr; /* 0x12 USB On-the-Go Status */
u16 res3; /* 0x14 */
u16 codeccr; /* 0x16 Codec Control */
u16 misccr2; /* 0x18 Misc2 Ctrl */
} ccm_t;
/* GPIO port */
typedef struct gpio_ctrl {
/* Port Output Data */
u8 podr_fbctl; /* 0x00 */
u8 podr_be; /* 0x01 */
u8 podr_cs; /* 0x02 */
u8 podr_dspi; /* 0x03 */
u8 res01; /* 0x04 */
u8 podr_fec0; /* 0x05 */
u8 podr_feci2c; /* 0x06 */
u8 res02[2]; /* 0x07 - 0x08 */
u8 podr_simp1; /* 0x09 */
u8 podr_simp0; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 podr_uart; /* 0x0C */
u8 podr_debug; /* 0x0D */
u8 res03; /* 0x0E */
u8 podr_sdhc; /* 0x0F */
u8 podr_ssi; /* 0x10 */
u8 res04[3]; /* 0x11 - 0x13 */
/* Port Data Direction */
u8 pddr_fbctl; /* 0x14 */
u8 pddr_be; /* 0x15 */
u8 pddr_cs; /* 0x16 */
u8 pddr_dspi; /* 0x17 */
u8 res05; /* 0x18 */
u8 pddr_fec0; /* 0x19 */
u8 pddr_feci2c; /* 0x1A */
u8 res06[2]; /* 0x1B - 0x1C */
u8 pddr_simp1; /* 0x1D */
u8 pddr_simp0; /* 0x1E */
u8 pddr_timer; /* 0x1F */
u8 pddr_uart; /* 0x20 */
u8 pddr_debug; /* 0x21 */
u8 res07; /* 0x22 */
u8 pddr_sdhc; /* 0x23 */
u8 pddr_ssi; /* 0x24 */
u8 res08[3]; /* 0x25 - 0x27 */
/* Port Data Direction */
u8 ppdr_fbctl; /* 0x28 */
u8 ppdr_be; /* 0x29 */
u8 ppdr_cs; /* 0x2A */
u8 ppdr_dspi; /* 0x2B */
u8 res09; /* 0x2C */
u8 ppdr_fec0; /* 0x2D */
u8 ppdr_feci2c; /* 0x2E */
u8 res10[2]; /* 0x2F - 0x30 */
u8 ppdr_simp1; /* 0x31 */
u8 ppdr_simp0; /* 0x32 */
u8 ppdr_timer; /* 0x33 */
u8 ppdr_uart; /* 0x34 */
u8 ppdr_debug; /* 0x35 */
u8 res11; /* 0x36 */
u8 ppdr_sdhc; /* 0x37 */
u8 ppdr_ssi; /* 0x38 */
u8 res12[3]; /* 0x39 - 0x3B */
/* Port Clear Output Data */
u8 pclrr_fbctl; /* 0x3C */
u8 pclrr_be; /* 0x3D */
u8 pclrr_cs; /* 0x3E */
u8 pclrr_dspi; /* 0x3F */
u8 res13; /* 0x40 */
u8 pclrr_fec0; /* 0x41 */
u8 pclrr_feci2c; /* 0x42 */
u8 res14[2]; /* 0x43 - 0x44 */
u8 pclrr_simp1; /* 0x45 */
u8 pclrr_simp0; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
u8 pclrr_uart; /* 0x48 */
u8 pclrr_debug; /* 0x49 */
u8 res15; /* 0x4A */
u8 pclrr_sdhc; /* 0x4B */
u8 pclrr_ssi; /* 0x4C */
u8 res16[3]; /* 0x4D - 0x4F */
/* Pin Assignment */
u8 par_fbctl; /* 0x50 */
u8 par_be; /* 0x51 */
u8 par_cs; /* 0x52 */
u8 res17; /* 0x53 */
u8 par_dspih; /* 0x54 */
u8 par_dspil; /* 0x55 */
u8 par_fec; /* 0x56 */
u8 par_feci2c; /* 0x57 */
u8 par_irq0h; /* 0x58 */
u8 par_irq0l; /* 0x59 */
u8 par_irq1h; /* 0x5A */
u8 par_irq1l; /* 0x5B */
u8 par_simp1h; /* 0x5C */
u8 par_simp1l; /* 0x5D */
u8 par_simp0; /* 0x5E */
u8 par_timer; /* 0x5F */
u8 par_uart; /* 0x60 */
u8 res18; /* 0x61 */
u8 par_debug; /* 0x62 */
u8 par_sdhc; /* 0x63 */
u8 par_ssih; /* 0x64 */
u8 par_ssil; /* 0x65 */
u8 res19[2]; /* 0x66 - 0x67 */
/* Mode Select Control */
/* Drive Strength Control */
u8 mscr_mscr1; /* 0x68 */
u8 mscr_mscr2; /* 0x69 */
u8 mscr_mscr3; /* 0x6A */
u8 mscr_mscr45; /* 0x6B */
u8 srcr_dspi; /* 0x6C */
u8 dscr_fec; /* 0x6D */
u8 srcr_i2c; /* 0x6E */
u8 srcr_irq; /* 0x6F */
u8 srcr_sim; /* 0x70 */
u8 srcr_timer; /* 0x71 */
u8 srcr_uart; /* 0x72 */
u8 res20; /* 0x73 */
u8 srcr_sdhc; /* 0x74 */
u8 srcr_ssi; /* 0x75 */
u8 res21[2]; /* 0x76 - 0x77 */
u8 pcr_pcrh; /* 0x78 */
u8 pcr_pcrl; /* 0x79 */
} gpio_t;
/* SDRAM controller */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode */
u32 ctrl; /* 0x04 Ctrl */
u32 cfg1; /* 0x08 Cfg 1 */
u32 cfg2; /* 0x0C Cfg 2 */
u32 res1[64]; /* 0x10 - 0x10F */
u32 cs0; /* 0x110 Chip Select 0 Cfg */
u32 cs1; /* 0x114 Chip Select 1 Cfg */
} sdram_t;
/* Clock Module */
typedef struct pll_ctrl {
u32 pcr; /* 0x00 Ctrl */
u32 pdr; /* 0x04 Divider */
u32 psr; /* 0x08 Status */
} pll_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5301X__ */

284
include/asm-m68k/immap_5329.h
View File

@ -70,9 +70,16 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
#include <asm/coldfire/skha.h>
/* System control module registers */
typedef struct scm1_ctrl {
@ -83,72 +90,6 @@ typedef struct scm1_ctrl {
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mdmr; /* 0x00 MDHA Mode Register */
u32 mdcr; /* 0x04 Control register */
u32 mdcmr; /* 0x08 Command Register */
u32 mdsr; /* 0x0C Status Register */
u32 mdisr; /* 0x10 Interrupt Status Register */
u32 mdimr; /* 0x14 Interrupt Mask Register */
u32 mddsr; /* 0x1C Data Size Register */
u32 mdin; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mdao; /* 0x30 Message Digest AO Register */
u32 mdbo; /* 0x34 Message Digest BO Register */
u32 mdco; /* 0x38 Message Digest CO Register */
u32 mddo; /* 0x3C Message Digest DO Register */
u32 mdeo; /* 0x40 Message Digest EO Register */
u32 mdmds; /* 0x44 Message Data Size Register */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 Register */
u32 mdb1; /* 0x74 Message Digest B1 Register */
u32 mdc1; /* 0x78 Message Digest C1 Register */
u32 mdd1; /* 0x7C Message Digest D1 Register */
u32 mde1; /* 0x80 Message Digest E1 Register */
} mdha_t;
/* Symmetric Key Hardware Accelerator */
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode Register */
u32 cr; /* 0x04 Control Register */
u32 cmr; /* 0x08 Command Register */
u32 sr; /* 0x0C Status Register */
u32 esr; /* 0x10 Error Status Register */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size Register */
u32 dsr; /* 0x1C Data Size Register */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data Register 1 */
u32 kdr2; /* 0x34 Key Data Register 2 */
u32 kdr3; /* 0x38 Key Data Register 3 */
u32 kdr4; /* 0x3C Key Data Register 4 */
u32 kdr5; /* 0x40 Key Data Register 5 */
u32 kdr6; /* 0x44 Key Data Register 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
} skha_t;
/* Random Number Generator */
typedef struct rng_ctrl {
u32 rngcr; /* 0x00 RNG Control Register */
u32 rngsr; /* 0x04 RNG Status Register */
u32 rnger; /* 0x08 RNG Entropy Register */
u32 rngout; /* 0x0C RNG Output FIFO */
} rng_t;
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
@ -165,25 +106,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
@ -206,148 +128,9 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable Register */
u8 pol; /* 0x01 Polarity Register */
u8 clk; /* 0x02 Clock Select Register */
u8 prclk; /* 0x03 Prescale Clock Select Register */
u8 cae; /* 0x04 Center Align Enable Register */
u8 ctl; /* 0x05 Control Register */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A register */
u8 sclb; /* 0x09 Scale B register */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter register */
u8 cnt1; /* 0x0D Channel 1 Counter register */
u8 cnt2; /* 0x0E Channel 2 Counter register */
u8 cnt3; /* 0x0F Channel 3 Counter register */
u8 cnt4; /* 0x10 Channel 4 Counter register */
u8 cnt5; /* 0x11 Channel 5 Counter register */
u8 cnt6; /* 0x12 Channel 6 Counter register */
u8 cnt7; /* 0x13 Channel 7 Counter register */
u8 per0; /* 0x14 Channel 0 Period register */
u8 per1; /* 0x15 Channel 1 Period register */
u8 per2; /* 0x16 Channel 2 Period register */
u8 per3; /* 0x17 Channel 3 Period register */
u8 per4; /* 0x18 Channel 4 Period register */
u8 per5; /* 0x19 Channel 5 Period register */
u8 per6; /* 0x1A Channel 6 Period register */
u8 per7; /* 0x1B Channel 7 Period register */
u8 dty0; /* 0x1C Channel 0 Duty register */
u8 dty1; /* 0x1D Channel 1 Duty register */
u8 dty2; /* 0x1E Channel 2 Duty register */
u8 dty3; /* 0x1F Channel 3 Duty register */
u8 dty4; /* 0x20 Channel 4 Duty register */
u8 dty5; /* 0x21 Channel 5 Duty register */
u8 dty6; /* 0x22 Channel 6 Duty register */
u8 dty7; /* 0x23 Channel 7 Duty register */
u8 sdn; /* 0x24 Shutdown register */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Edge Port module registers */
typedef struct eport_ctrl {
u16 par; /* 0x00 Pin Assignment Register */
u8 ddar; /* 0x02 Data Direction Register */
u8 ier; /* 0x03 Interrupt Enable Register */
u8 dr; /* 0x04 Data Register */
u8 pdr; /* 0x05 Pin Data Register */
u8 fr; /* 0x06 Flag_Register */
u8 res1;
} eport_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
@ -593,53 +376,6 @@ typedef struct usb_otg {
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
/* USB Host module registers */
typedef struct usb_host {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 res1; /* 0x0C */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res2[58]; /* 0x18 - 0xFF */
/* Host Controller Capability Register */
u8 caplength; /* 0x100 Capability Register Length */
u8 res3; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res4[13]; /* 0x10C - 0x13F */
/* Host Controller Operational Register */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
u32 prdlst; /* 0x154 Periodic Frame List Base Address */
u32 aynclst; /* 0x158 Current Asynchronous List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
u32 res6[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res7[8]; /* 0x188 - 0x1A7 */
/* non-ehci registers */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbhost_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */

160
include/asm-m68k/immap_5445x.h
View File

@ -69,161 +69,15 @@
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
#include <asm/coldfire/ata.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
@ -387,14 +241,6 @@ typedef struct gpio {
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/* Random Number Generator (RNG) */
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rnger;
u32 rngout;
} rng_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */

40
include/asm-m68k/immap_547x_8x.h
View File

@ -57,7 +57,11 @@
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
typedef struct siu {
u32 mbar; /* 0x00 */
@ -98,37 +102,6 @@ typedef struct xlb_arb {
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 */
u32 iprl0; /* 0x04 */
u32 imrh0; /* 0x08 */
u32 imrl0; /* 0x0C */
u32 frch0; /* 0x10 */
u32 frcl0; /* 0x14 */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1; /* 0x1A - 0x1B */
u32 res2[9]; /* 0x1C - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
@ -147,6 +120,11 @@ typedef struct gptmr {
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */

237
include/asm-m68k/m5227x.h
View File

@ -26,9 +26,7 @@
#ifndef __MCF5227X__
#define __MCF5227X__
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT4 (4)
@ -98,235 +96,6 @@
#define INT1_HI_TOUCH_ADC (61)
#define INT1_HI_PLL_LOCKS (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for IMRH */
#define INTC_IMRH_INT_MASK32 (0x00000001)
#define INTC_IMRH_INT_MASK33 (0x00000002)
#define INTC_IMRH_INT_MASK34 (0x00000004)
#define INTC_IMRH_INT_MASK35 (0x00000008)
#define INTC_IMRH_INT_MASK36 (0x00000010)
#define INTC_IMRH_INT_MASK37 (0x00000020)
#define INTC_IMRH_INT_MASK38 (0x00000040)
#define INTC_IMRH_INT_MASK39 (0x00000080)
#define INTC_IMRH_INT_MASK40 (0x00000100)
#define INTC_IMRH_INT_MASK41 (0x00000200)
#define INTC_IMRH_INT_MASK42 (0x00000400)
#define INTC_IMRH_INT_MASK43 (0x00000800)
#define INTC_IMRH_INT_MASK44 (0x00001000)
#define INTC_IMRH_INT_MASK45 (0x00002000)
#define INTC_IMRH_INT_MASK46 (0x00004000)
#define INTC_IMRH_INT_MASK47 (0x00008000)
#define INTC_IMRH_INT_MASK48 (0x00010000)
#define INTC_IMRH_INT_MASK49 (0x00020000)
#define INTC_IMRH_INT_MASK50 (0x00040000)
#define INTC_IMRH_INT_MASK51 (0x00080000)
#define INTC_IMRH_INT_MASK52 (0x00100000)
#define INTC_IMRH_INT_MASK53 (0x00200000)
#define INTC_IMRH_INT_MASK54 (0x00400000)
#define INTC_IMRH_INT_MASK55 (0x00800000)
#define INTC_IMRH_INT_MASK56 (0x01000000)
#define INTC_IMRH_INT_MASK57 (0x02000000)
#define INTC_IMRH_INT_MASK58 (0x04000000)
#define INTC_IMRH_INT_MASK59 (0x08000000)
#define INTC_IMRH_INT_MASK60 (0x10000000)
#define INTC_IMRH_INT_MASK61 (0x20000000)
#define INTC_IMRH_INT_MASK62 (0x40000000)
#define INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for IMRL */
#define INTC_IMRL_INT_MASK0 (0x00000001)
#define INTC_IMRL_INT_MASK1 (0x00000002)
#define INTC_IMRL_INT_MASK2 (0x00000004)
#define INTC_IMRL_INT_MASK3 (0x00000008)
#define INTC_IMRL_INT_MASK4 (0x00000010)
#define INTC_IMRL_INT_MASK5 (0x00000020)
#define INTC_IMRL_INT_MASK6 (0x00000040)
#define INTC_IMRL_INT_MASK7 (0x00000080)
#define INTC_IMRL_INT_MASK8 (0x00000100)
#define INTC_IMRL_INT_MASK9 (0x00000200)
#define INTC_IMRL_INT_MASK10 (0x00000400)
#define INTC_IMRL_INT_MASK11 (0x00000800)
#define INTC_IMRL_INT_MASK12 (0x00001000)
#define INTC_IMRL_INT_MASK13 (0x00002000)
#define INTC_IMRL_INT_MASK14 (0x00004000)
#define INTC_IMRL_INT_MASK15 (0x00008000)
#define INTC_IMRL_INT_MASK16 (0x00010000)
#define INTC_IMRL_INT_MASK17 (0x00020000)
#define INTC_IMRL_INT_MASK18 (0x00040000)
#define INTC_IMRL_INT_MASK19 (0x00080000)
#define INTC_IMRL_INT_MASK20 (0x00100000)
#define INTC_IMRL_INT_MASK21 (0x00200000)
#define INTC_IMRL_INT_MASK22 (0x00400000)
#define INTC_IMRL_INT_MASK23 (0x00800000)
#define INTC_IMRL_INT_MASK24 (0x01000000)
#define INTC_IMRL_INT_MASK25 (0x02000000)
#define INTC_IMRL_INT_MASK26 (0x04000000)
#define INTC_IMRL_INT_MASK27 (0x08000000)
#define INTC_IMRL_INT_MASK28 (0x10000000)
#define INTC_IMRL_INT_MASK29 (0x20000000)
#define INTC_IMRL_INT_MASK30 (0x40000000)
#define INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for INTFRCH */
#define INTC_INTFRCH_INTFRC32 (0x00000001)
#define INTC_INTFRCH_INTFRC33 (0x00000002)
#define INTC_INTFRCH_INTFRC34 (0x00000004)
#define INTC_INTFRCH_INTFRC35 (0x00000008)
#define INTC_INTFRCH_INTFRC36 (0x00000010)
#define INTC_INTFRCH_INTFRC37 (0x00000020)
#define INTC_INTFRCH_INTFRC38 (0x00000040)
#define INTC_INTFRCH_INTFRC39 (0x00000080)
#define INTC_INTFRCH_INTFRC40 (0x00000100)
#define INTC_INTFRCH_INTFRC41 (0x00000200)
#define INTC_INTFRCH_INTFRC42 (0x00000400)
#define INTC_INTFRCH_INTFRC43 (0x00000800)
#define INTC_INTFRCH_INTFRC44 (0x00001000)
#define INTC_INTFRCH_INTFRC45 (0x00002000)
#define INTC_INTFRCH_INTFRC46 (0x00004000)
#define INTC_INTFRCH_INTFRC47 (0x00008000)
#define INTC_INTFRCH_INTFRC48 (0x00010000)
#define INTC_INTFRCH_INTFRC49 (0x00020000)
#define INTC_INTFRCH_INTFRC50 (0x00040000)
#define INTC_INTFRCH_INTFRC51 (0x00080000)
#define INTC_INTFRCH_INTFRC52 (0x00100000)
#define INTC_INTFRCH_INTFRC53 (0x00200000)
#define INTC_INTFRCH_INTFRC54 (0x00400000)
#define INTC_INTFRCH_INTFRC55 (0x00800000)
#define INTC_INTFRCH_INTFRC56 (0x01000000)
#define INTC_INTFRCH_INTFRC57 (0x02000000)
#define INTC_INTFRCH_INTFRC58 (0x04000000)
#define INTC_INTFRCH_INTFRC59 (0x08000000)
#define INTC_INTFRCH_INTFRC60 (0x10000000)
#define INTC_INTFRCH_INTFRC61 (0x20000000)
#define INTC_INTFRCH_INTFRC62 (0x40000000)
#define INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for INTFRCL */
#define INTC_INTFRCL_INTFRC0 (0x00000001)
#define INTC_INTFRCL_INTFRC1 (0x00000002)
#define INTC_INTFRCL_INTFRC2 (0x00000004)
#define INTC_INTFRCL_INTFRC3 (0x00000008)
#define INTC_INTFRCL_INTFRC4 (0x00000010)
#define INTC_INTFRCL_INTFRC5 (0x00000020)
#define INTC_INTFRCL_INTFRC6 (0x00000040)
#define INTC_INTFRCL_INTFRC7 (0x00000080)
#define INTC_INTFRCL_INTFRC8 (0x00000100)
#define INTC_INTFRCL_INTFRC9 (0x00000200)
#define INTC_INTFRCL_INTFRC10 (0x00000400)
#define INTC_INTFRCL_INTFRC11 (0x00000800)
#define INTC_INTFRCL_INTFRC12 (0x00001000)
#define INTC_INTFRCL_INTFRC13 (0x00002000)
#define INTC_INTFRCL_INTFRC14 (0x00004000)
#define INTC_INTFRCL_INTFRC15 (0x00008000)
#define INTC_INTFRCL_INTFRC16 (0x00010000)
#define INTC_INTFRCL_INTFRC17 (0x00020000)
#define INTC_INTFRCL_INTFRC18 (0x00040000)
#define INTC_INTFRCL_INTFRC19 (0x00080000)
#define INTC_INTFRCL_INTFRC20 (0x00100000)
#define INTC_INTFRCL_INTFRC21 (0x00200000)
#define INTC_INTFRCL_INTFRC22 (0x00400000)
#define INTC_INTFRCL_INTFRC23 (0x00800000)
#define INTC_INTFRCL_INTFRC24 (0x01000000)
#define INTC_INTFRCL_INTFRC25 (0x02000000)
#define INTC_INTFRCL_INTFRC26 (0x04000000)
#define INTC_INTFRCL_INTFRC27 (0x08000000)
#define INTC_INTFRCL_INTFRC28 (0x10000000)
#define INTC_INTFRCL_INTFRC29 (0x20000000)
#define INTC_INTFRCL_INTFRC30 (0x40000000)
#define INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for ICONFIG */
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for SIMR */
#define INTC_SIMR_SIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CIMR */
#define INTC_CIMR_CIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CLMASK */
#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for SLMASK */
#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
@ -513,8 +282,8 @@
/* Bit definitions and macros for PAR_DSPI */
#define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0x80)
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x40)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPI_SIN_MASK (0xCF)
#define GPIO_PAR_DSPI_SIN_SIN (0x30)

303
include/asm-m68k/m5235.h
View File

@ -162,94 +162,6 @@
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSMR */
#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#define FBCS_CSMR_WP (0x00000100)
#define FBCS_CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
#define FBCS_CSCR_AA (0x0100)
#define FBCS_CSCR_PS_MASK (0x00C0)
#define FBCS_CSCR_PS_32 (0x0000)
#define FBCS_CSCR_PS_16 (0x0080)
#define FBCS_CSCR_PS_8 (0x0040)
#define FBCS_CSCR_BEM (0x0020)
#define FBCS_CSCR_BSTR (0x0010)
#define FBCS_CSCR_BSTW (0x0008)
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
@ -370,85 +282,6 @@
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_IRLR */
#define INTC_IRLRn(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for INTC_IACKLPRn */
#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICRnx */
#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
#define INTC_ICRnx_IP(x) ((x)&0x07)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
@ -757,49 +590,6 @@
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Edge Port
*********************************************************************/
#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
#define EPORT_EPIER_EPIE7 (0x80)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
@ -809,97 +599,4 @@
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
#endif /* mcf5235_h */

13
include/asm-m68k/m5249.h
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@ -77,19 +77,6 @@
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */

38
include/asm-m68k/m5271.h
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@ -116,9 +116,7 @@
#define MCFSIM_ICR1 0x000C41
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
@ -182,38 +180,4 @@
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#endif /* _MCF5271_H_ */

46
include/asm-m68k/m5275.h
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@ -30,18 +30,6 @@
* Define the 5275 SIM register set addresses. These are similar,
* but not quite identical to the 5282 registers and offsets.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCF_GPIO_PAR_UART 0x10007c
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
@ -198,40 +186,6 @@
#define INT1_HI_FEC1_BABR (35)
/* 36-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)

23
include/asm-m68k/m5282.h
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@ -440,29 +440,6 @@
#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000080))
#define MCFCSM_CSMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000084))
#define MCFCSM_CSCR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008a))
#define MCFCSM_CSAR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008C))
#define MCFCSM_CSMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000090))
#define MCFCSM_CSCR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000096))
#define MCFCSM_CSAR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000098))
#define MCFCSM_CSMR2 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000009C))
#define MCFCSM_CSCR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A2))
#define MCFCSM_CSAR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A4))
#define MCFCSM_CSMR3 (*(vu_long *) (CONFIG_SYS_MBAR+0x000000A8))
#define MCFCSM_CSCR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000AE))
#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
#define MCFCSM_CSMR_WP (1<<8)
#define MCFCSM_CSMR_V (0x01)
#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
#define MCFCSM_CSCR_AA (0x0100)
#define MCFCSM_CSCR_PS_32 (0x0000)
#define MCFCSM_CSCR_PS_8 (0x0040)
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
* General Purpose Timer (GPT) Module
*********************************************************************/

604
include/asm-m68k/m5301x.h Normal file
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@ -0,0 +1,604 @@
/*
* m5301x.h -- Definitions for Freescale Coldfire 5301x
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef m5301x_h
#define m5301x_h
/* *** System Control Module (SCM) *** */
#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12)
#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8)
#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4)
#define MPROT_MTR 4
#define MPROT_MTW 2
#define MPROT_MPL 1
#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8)
#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8)
#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16)
#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8)
#define SCM_PACRE_PACR39(x) ((x) & 0x0F)
#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16)
#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12)
#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8)
#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4)
#define SCM_PACRF_PACR47(x) ((x) & 0x0F)
#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28)
#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24)
#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20)
#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16)
#define PACR_SP 4
#define PACR_WP 2
#define PACR_TP 1
#define SCM_CWCR_RO (0x8000)
#define SCM_CWCR_CWR_WH (0x0100)
#define SCM_CWCR_CWE (0x0080)
#define SCM_CWCR_CWRI_WINDOW (0x0060)
#define SCM_CWCR_CWRI_RESET (0x0040)
#define SCM_CWCR_CWRI_INT_RESET (0x0020)
#define SCM_CWCR_CWRI_INT (0x0000)
#define SCM_CWCR_CWT(x) (((x) & 0x001F))
#define SCM_ISR_CFEI (0x02)
#define SCM_ISR_CWIC (0x01)
#define BCR_GBR (0x00000200)
#define BCR_GBW (0x00000100)
#define BCR_S7 (0x00000080)
#define BCR_S6 (0x00000040)
#define BCR_S4 (0x00000010)
#define BCR_S1 (0x00000002)
#define SCM_CFIER_ECFEI (0x01)
#define SCM_CFLOC_LOC (0x80)
#define SCM_CFATR_WRITE (0x80)
#define SCM_CFATR_SZ32 (0x20)
#define SCM_CFATR_SZ16 (0x10)
#define SCM_CFATR_SZ08 (0x00)
#define SCM_CFATR_CACHE (0x08)
#define SCM_CFATR_MODE (0x02)
#define SCM_CFATR_TYPE (0x01)
/* *** Interrupt Controller (INTC) *** */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM_CWIC (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_RSVD1 (29)
#define INT0_LO_I2C (30)
#define INT0_LO_DSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_FEC0_TXF (36)
#define INT0_HI_FEC0_TXB (37)
#define INT0_HI_FEC0_UN (38)
#define INT0_HI_FEC0_RL (39)
#define INT0_HI_FEC0_RXF (40)
#define INT0_HI_FEC0_RXB (41)
#define INT0_HI_FEC0_MII (42)
#define INT0_HI_FEC0_LC (43)
#define INT0_HI_FEC0_HBERR (44)
#define INT0_HI_FEC0_GRA (45)
#define INT0_HI_FEC0_EBERR (46)
#define INT0_HI_FEC0_BABT (47)
#define INT0_HI_FEC0_BABR (48)
#define INT0_HI_FEC1_TXF (49)
#define INT0_HI_FEC1_TXB (50)
#define INT0_HI_FEC1_UN (51)
#define INT0_HI_FEC1_RL (52)
#define INT0_HI_FEC1_RXF (53)
#define INT0_HI_FEC1_RXB (54)
#define INT0_HI_FEC1_MII (55)
#define INT0_HI_FEC1_LC (56)
#define INT0_HI_FEC1_HBERR (57)
#define INT0_HI_FEC1_GRA (58)
#define INT0_HI_FEC1_EBERR (59)
#define INT0_HI_FEC1_BABT (60)
#define INT0_HI_FEC1_BABR (61)
#define INT0_HI_SCM_CFEI (62)
/* 0 - 24 reserved */
#define INT1_LO_EPORT1_FLAG0 (25)
#define INT1_LO_EPORT1_FLAG1 (26)
#define INT1_LO_EPORT1_FLAG2 (27)
#define INT1_LO_EPORT1_FLAG3 (28)
#define INT1_LO_EPORT1_FLAG4 (29)
#define INT1_LO_EPORT1_FLAG5 (30)
#define INT1_LO_EPORT1_FLAG6 (31)
#define INT1_LO_EPORT1_FLAG7 (32)
#define INT1_HI_DSPI_EOQF (33)
#define INT1_HI_DSPI_TFFF (34)
#define INT1_HI_DSPI_TCF (35)
#define INT1_HI_DSPI_TFUF (36)
#define INT1_HI_DSPI_RFDF (37)
#define INT1_HI_DSPI_RFOF (38)
#define INT1_HI_DSPI_RFOF_TFUF (39)
#define INT1_HI_RNG_EI (40)
#define INT1_HI_PLL_LOCF (41)
#define INT1_HI_PLL_LOLF (42)
#define INT1_HI_PIT0 (43)
#define INT1_HI_PIT1 (44)
#define INT1_HI_PIT2 (45)
#define INT1_HI_PIT3 (46)
#define INT1_HI_USBOTG_STS (47)
#define INT1_HI_USBHOST_STS (48)
#define INT1_HI_SSI (49)
/* 50 - 51 reserved */
#define INT1_HI_RTC (52)
#define INT1_HI_CCM_USBSTAT (53)
#define INT1_HI_CODEC_OR (54)
#define INT1_HI_CODEC_RF_TE (55)
#define INT1_HI_CODEC_ROE (56)
#define INT1_HI_CODEC_TUE (57)
/* 58 reserved */
#define INT1_HI_SIM1_DATA (59)
#define INT1_HI_SIM1_GENERAL (60)
/* 61 - 62 reserved */
#define INT1_HI_SDHC (63)
/* *** Reset Controller Module (RCM) *** */
#define RCM_RCR_SOFTRST (0x80)
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RSR_SOFT (0x20)
#define RCM_RSR_LOC (0x10)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_LOL (0x01)
/* *** Chip Configuration Module (CCM) *** */
#define CCM_CCR_CSC (0x0020)
#define CCM_CCR_BOOTPS (0x0010)
#define CCM_CCR_LOAD (0x0008)
#define CCM_CCR_OSC_MODE (0x0004)
#define CCM_CCR_SDR_MODE (0x0002)
#define CCM_CCR_RESERVED (0x0001)
#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012)
#define CCM_RCON_DDR_8BIT_SPLIT (0x0010)
#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002)
#define CCM_RCON_DDR_16BIT_SPLIT (0x0000)
#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
#define CCM_MISCCR_FECM (0x8000)
#define CCM_MISCCR_CDCSRC (0x4000)
#define CCM_MISCCR_PLL_LOCK (0x2000)
#define CCM_MISCCR_LIMP (0x1000)
#define CCM_MISCCR_BME (0x8000)
#define CCM_MISCCR_BMT_MASK (0xF8FF)
#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
#define CCM_MISCCR_BMT_512 (0x0700)
#define CCM_MISCCR_BMT_1024 (0x0600)
#define CCM_MISCCR_BMT_2048 (0x0500)
#define CCM_MISCCR_BMT_4096 (0x0400)
#define CCM_MISCCR_BMT_8192 (0x0300)
#define CCM_MISCCR_BMT_16384 (0x0200)
#define CCM_MISCCR_BMT_32768 (0x0100)
#define CCM_MISCCR_BMT_65536 (0x0000)
#define CCM_MISCCR_TIM_DMA (0x0020)
#define CCM_MISCCR_SSI_SRC (0x0010)
#define CCM_MISCCR_USBH_OC (0x0008)
#define CCM_MISCCR_USBO_OC (0x0004)
#define CCM_MISCCR_USB_PUE (0x0002)
#define CCM_MISCCR_USB_SRC (0x0001)
#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8)
#define CCM_CDR_SSIDIV(x) ((x) & 0xFF)
#define CCM_UOCSR_DPPD (0x2000)
#define CCM_UOCSR_DMPD (0x1000)
#define CCM_UOCSR_DRV_VBUS (0x0800)
#define CCM_UOCSR_CRG_VBUS (0x0400)
#define CCM_UOCSR_DCR_VBUS (0x0200)
#define CCM_UOCSR_DPPU (0x0100)
#define CCM_UOCSR_AVLD (0x0080)
#define CCM_UOCSR_BVLD (0x0040)
#define CCM_UOCSR_VVLD (0x0020)
#define CCM_UOCSR_SEND (0x0010)
#define CCM_UOCSR_PWRFLT (0x0008)
#define CCM_UOCSR_WKUP (0x0004)
#define CCM_UOCSR_UOMIE (0x0002)
#define CCM_UOCSR_XPDE (0x0001)
#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14)
#define CCM_UHCSR_DRV_VBUS (0x0010)
#define CCM_UHCSR_PWRFLT (0x0008)
#define CCM_UHCSR_WKUP (0x0004)
#define CCM_UHCSR_UHMIE (0x0002)
#define CCM_UHCSR_XPDE (0x0001)
#define CCM_CODCR_BGREN (0x8000)
#define CCM_CODCR_REGEN (0x0080)
#define CCM_MISC2_IGNLL (0x0008)
#define CCM_MISC2_DPS (0x0001)
/* *** General Purpose I/O (GPIO) *** */
#define GPIO_PDR_FBCTL ((x) & 0x0F)
#define GPIO_PDR_BE ((x) & 0x0F)
#define GPIO_PDR_CS32 (((x) & 0x03) << 4)
#define GPIO_PDR_CS10 (((x) & 0x03) << 4)
#define GPIO_PDR_DSPI ((x) & 0x7F)
#define GPIO_PDR_FEC0 ((x) & 0x7F)
#define GPIO_PDR_FECI2C ((x) & 0x3F)
#define GPIO_PDR_SIMP1 ((x) & 0x1F)
#define GPIO_PDR_SIMP0 ((x) & 0x1F)
#define GPIO_PDR_TIMER ((x) & 0x0F)
#define GPIO_PDR_UART ((x) & 0x3F)
#define GPIO_PDR_DEBUG (0x01)
#define GPIO_PDR_SDHC ((x) & 0x3F)
#define GPIO_PDR_SSI ((x) & 0x1F)
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_RWB (0x20)
#define GPIO_PAR_FBCTL_TS (0x18)
#define GPIO_PAR_BE3 (0x40)
#define GPIO_PAR_BE2 (0x10)
#define GPIO_PAR_BE1 (0x04)
#define GPIO_PAR_BE0 (0x01)
#define GPIO_PAR_CS5 (0x40)
#define GPIO_PAR_CS4 (0x10)
#define GPIO_PAR_CS1_MASK (0xF3)
#define GPIO_PAR_CS1_CS1 (0x0C)
#define GPIO_PAR_CS1_SDCS1 (0x08)
#define GPIO_PAR_CS0_MASK (0xFC)
#define GPIO_PAR_CS0_CS0 (0x03)
#define GPIO_PAR_CS0_CS4 (0x02)
#define GPIO_PAR_DSPIH_SIN_MASK (0x3F)
#define GPIO_PAR_DSPIH_SIN (0xC0)
#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80)
#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF)
#define GPIO_PAR_DSPIH_SOUT (0x30)
#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20)
#define GPIO_PAR_DSPIH_SCK_MASK (0xF3)
#define GPIO_PAR_DSPIH_SCK (0x0C)
#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08)
#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC)
#define GPIO_PAR_DSPIH_PCS0 (0x03)
#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02)
#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F)
#define GPIO_PAR_DSPIL_PCS1 (0xC0)
#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF)
#define GPIO_PAR_DSPIL_PCS2 (0x30)
#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20)
#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3)
#define GPIO_PAR_DSPIL_PCS3 (0x0C)
#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08)
#define GPIO_PAR_FEC1_7W_FEC (0x40)
#define GPIO_PAR_FEC1_RMII_FEC (0x10)
#define GPIO_PAR_FEC0_7W_FEC (0x04)
#define GPIO_PAR_FEC0_RMII_FEC (0x01)
/* GPIO_PAR_FECI2C */
#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F)
#define GPIO_PAR_FECI2C_MDC0 (0x80)
#define GPIO_PAR_FECI2C_MDIO0 (0x40)
#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF)
#define GPIO_PAR_FECI2C_MDC1 (0x20)
#define GPIO_PAR_FECI2C_MDIO1 (0x10)
#define GPIO_PAR_FECI2C_SDA_MASK (0xF3)
#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2)
#define GPIO_PAR_FECI2C_SDA_SDA (0x0C)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08)
#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04)
#define GPIO_PAR_FECI2C_SCL_MASK (0xFC)
#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03)
#define GPIO_PAR_FECI2C_SCL_SCL (0x03)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02)
#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01)
#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F)
#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF)
#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10)
#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC)
#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02)
#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3)
#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08)
#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40)
#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10)
#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04)
#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01)
#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40)
#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10)
#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04)
#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01)
#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F)
#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0)
#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80)
#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40)
#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF)
#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30)
#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20)
#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10)
#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3)
#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C)
#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08)
#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04)
#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC)
#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03)
#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02)
#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01)
#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F)
#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0)
#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80)
#define GPIO_PAR_SIMP0_DATA0 (0x10)
#define GPIO_PAR_SIMP0_VEN0 (0x08)
#define GPIO_PAR_SIMP0_RST0 (0x04)
#define GPIO_PAR_SIMP0_PD0 (0x02)
#define GPIO_PAR_SIMP0_CLK0 (0x01)
#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6)
#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TIN0(x) ((x) & 0x03)
#define GPIO_PAR_TIN3_MASK (0x3F)
#define GPIO_PAR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TIN3_IRQ03 (0x40)
#define GPIO_PAR_TIN2_MASK (0xCF)
#define GPIO_PAR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TIN2_IRQ02 (0x10)
#define GPIO_PAR_TIN1_MASK (0xF3)
#define GPIO_PAR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TIN1_DACK1 (0x04)
#define GPIO_PAR_TIN0_MASK (0xFC)
#define GPIO_PAR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01)
#define GPIO_PAR_UART_U2TXD (0x80)
#define GPIO_PAR_UART_U2RXD (0x40)
#define GPIO_PAR_UART_U0TXD (0x20)
#define GPIO_PAR_UART_U0RXD (0x10)
#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2)
#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03)
#define GPIO_PAR_UART_RTS0_MASK (0xF3)
#define GPIO_PAR_UART_RTS0_U0RTS (0x0C)
#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08)
#define GPIO_PAR_UART_CTS0_MASK (0xFC)
#define GPIO_PAR_UART_CTS0_U0CTS (0x03)
#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02)
#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01)
#define GPIO_PAR_DEBUG_ALLPST (0x80)
#define GPIO_PAR_SDHC_DATA3 (0x20)
#define GPIO_PAR_SDHC_DATA2 (0x10)
#define GPIO_PAR_SDHC_DATA1 (0x08)
#define GPIO_PAR_SDHC_DATA0 (0x04)
#define GPIO_PAR_SDHC_CMD (0x02)
#define GPIO_PAR_SDHC_CLK (0x01)
#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6)
#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4)
#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2)
#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03)
#define GPIO_PAR_SSIH_RXD_MASK (0x3F)
#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0)
#define GPIO_PAR_SSIH_RXD_U1RXD (0x40)
#define GPIO_PAR_SSIH_TXD_MASK (0xCF)
#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30)
#define GPIO_PAR_SSIH_TXD_U1TXD (0x10)
#define GPIO_PAR_SSIH_FS_MASK (0xF3)
#define GPIO_PAR_SSIH_FS_SSIFS (0x0C)
#define GPIO_PAR_SSIH_FS_U1RTS (0x04)
#define GPIO_PAR_SSIH_MCLK_MASK (0xFC)
#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03)
#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01)
#define GPIO_PAR_SSIL_MASK (0x3F)
#define GPIO_PAR_SSIL_BCLK (0xC0)
#define GPIO_PAR_SSIL_U1CTS (0x40)
#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCRn_MASK (0x1F)
#define GPIO_MSCR_MSCRn_SDR (0xE0)
#define GPIO_MSCR_MSCRn_25VDDR (0x60)
#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20)
#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00)
#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2)
#define GPIO_MSCR_MSCR5_MASK (0xE3)
#define GPIO_MSCR_MSCR5_SDR (0x1C)
#define GPIO_MSCR_MSCR5_25VDDR (0x0C)
#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04)
#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00)
#define GPIO_SRCR_DSPI_MASK (0xFC)
#define GPIO_SRCR_DSPI(x) ((x) & 0x03)
#define GPIO_SRCR_I2C_MASK (0xFC)
#define GPIO_SRCR_I2C(x) ((x) & 0x03)
#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3)
#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC)
#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03)
#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3)
#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC)
#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03)
#define GPIO_SRCR_TIMER_MASK (0xFC)
#define GPIO_SRCR_TIMER(x) ((x) & 0x03)
#define GPIO_SRCR_UART2_MASK (0xF3)
#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2)
#define GPIO_SRCR_UART0_MASK (0xFC)
#define GPIO_SRCR_UART0(x) ((x) & 0x03)
#define GPIO_SRCR_SDHC_MASK (0xFC)
#define GPIO_SRCR_SDHC(x) ((x) & 0x03)
#define GPIO_SRCR_SSI_MASK (0xFC)
#define GPIO_SRCR_SSI(x) ((x) & 0x03)
#define SRCR_HIGHEST (0x03)
#define SRCR_HIGH (0x02)
#define SRCR_LOW (0x01)
#define SRCR_LOWEST (0x00)
#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF)
#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4)
#define GPIO_DSCR_FEC_RMII0_MASK (0xF3)
#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2)
#define GPIO_DSCR_FEC_RMII1_MASK (0xFC)
#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03)
#define DSCR_50PF (0x03)
#define DSCR_30PF (0x02)
#define DSCR_20PF (0x01)
#define DSCR_10PF (0x00)
#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80)
#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40)
#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20)
#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10)
#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08)
#define GPIO_PCRH_SSI_PULLUP_EN (0x02)
#define GPIO_PCRH_SSI_PULLUP (0x01)
#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80)
#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40)
#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20)
#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10)
#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08)
#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04)
/* *** Phase Locked Loop (PLL) *** */
#define PLL_PCR_LOC_IRQ (0x00040000)
#define PLL_PCR_LOC_RE (0x00020000)
#define PLL_PCR_LOC_EN (0x00010000)
#define PLL_PCR_LOL_IRQ (0x00004000)
#define PLL_PCR_LOL_RE (0x00002000)
#define PLL_PCR_LOL_EN (0x00001000)
#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF)
#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8)
#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0)
#define PLL_PCR_FBDIV(x) ((x) & 0x3F)
#define PLL_PDR_OUTDIV4_MASK (0x0FFF)
#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12)
#define PLL_PDR_OUTDIV3_MASK (0xF0FF)
#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8)
#define PLL_PDR_OUTDIV2_MASK (0xFF0F)
#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4)
#define PLL_PDR_OUTDIV1_MASK (0xFFF0)
#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F)
#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x)
#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x)
#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x)
#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x)
#define PLL_PSR_LOCF (0x00000200)
#define PLL_PSR_LOC (0x00000100)
#define PLL_PSR_LOLF (0x00000040)
#define PLL_PSR_LOCKS (0x00000020)
#define PLL_PSR_LOCK (0x00000010)
#define PLL_PSR_MODE(x) ((x) & 0x07)
/* *** Real Time Clock *** */
#define RTC_OCEN_OSCBYP (0x00000010)
#define RTC_OCEN_CLKEN (0x00000008)
#endif /* m5301x_h */

347
include/asm-m68k/m5329.h
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@ -186,65 +186,6 @@
#define CFATR_MODE (0x02)
#define CFATR_TYPE (0x01)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSAR */
#define CSAR_BA(x) (((x)&0xFFFF)<<16)
/* Bit definitions and macros for FBCS_CSMR */
#define CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define CSMR_BAM_4G (0xFFFF0000)
#define CSMR_BAM_2G (0x7FFF0000)
#define CSMR_BAM_1G (0x3FFF0000)
#define CSMR_BAM_1024M (0x3FFF0000)
#define CSMR_BAM_512M (0x1FFF0000)
#define CSMR_BAM_256M (0x0FFF0000)
#define CSMR_BAM_128M (0x07FF0000)
#define CSMR_BAM_64M (0x03FF0000)
#define CSMR_BAM_32M (0x01FF0000)
#define CSMR_BAM_16M (0x00FF0000)
#define CSMR_BAM_8M (0x007F0000)
#define CSMR_BAM_4M (0x003F0000)
#define CSMR_BAM_2M (0x001F0000)
#define CSMR_BAM_1M (0x000F0000)
#define CSMR_BAM_1024K (0x000F0000)
#define CSMR_BAM_512K (0x00070000)
#define CSMR_BAM_256K (0x00030000)
#define CSMR_BAM_128K (0x00010000)
#define CSMR_BAM_64K (0x00000000)
#define CSMR_WP (0x00000100)
#define CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define CSCR_SWS(x) (((x)&0x3F)<<26)
#define CSCR_ASET(x) (((x)&0x03)<<20)
#define CSCR_SWSEN (0x00800000)
#define CSCR_ASET_4CLK (0x00300000)
#define CSCR_ASET_3CLK (0x00200000)
#define CSCR_ASET_2CLK (0x00100000)
#define CSCR_ASET_1CLK (0x00000000)
#define CSCR_RDAH(x) (((x)&0x03)<<18)
#define CSCR_RDAH_4CYC (0x000C0000)
#define CSCR_RDAH_3CYC (0x00080000)
#define CSCR_RDAH_2CYC (0x00040000)
#define CSCR_RDAH_1CYC (0x00000000)
#define CSCR_WRAH(x) (((x)&0x03)<<16)
#define CSCR_WDAH_4CYC (0x00003000)
#define CSCR_WDAH_3CYC (0x00002000)
#define CSCR_WDAH_2CYC (0x00001000)
#define CSCR_WDAH_1CYC (0x00000000)
#define CSCR_WS(x) (((x)&0x3F)<<10)
#define CSCR_SBM (0x00000200)
#define CSCR_AA (0x00000100)
#define CSCR_PS_MASK (0x000000C0)
#define CSCR_PS_32 (0x00000000)
#define CSCR_PS_16 (0x00000080)
#define CSCR_PS_8 (0x00000040)
#define CSCR_BEM (0x00000020)
#define CSCR_BSTR (0x00000010)
#define CSCR_BSTW (0x00000008)
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
@ -260,100 +201,6 @@
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
#define ERRSTAT_WAKINT (0x00000001)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
@ -411,200 +258,6 @@
/* 49 - 61 Reserved */
#define INT0_HI_SCM (62)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_ICONFIG */
#define INTC_ICFG_ELVLPRI7 (0x8000)
#define INTC_ICFG_ELVLPRI6 (0x4000)
#define INTC_ICFG_ELVLPRI5 (0x2000)
#define INTC_ICFG_ELVLPRI4 (0x1000)
#define INTC_ICFG_ELVLPRI3 (0x0800)
#define INTC_ICFG_ELVLPRI2 (0x0400)
#define INTC_ICFG_ELVLPRI1 (0x0200)
#define INTC_ICFG_EMASK (0x0020)
/* Bit definitions and macros for INTC_SIMR */
#define INTC_SIMR_SALL (0x40)
#define INTC_SIMR_SIMR(x) ((x)&0x3F)
/* Bit definitions and macros for INTC_CIMR */
#define INTC_CIMR_CALL (0x40)
#define INTC_CIMR_CIMR(x) ((x)&0x3F)
/* Bit definitions and macros for INTC_CLMASK */
#define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_SLMASK */
#define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICR */
#define INTC_ICR_IL(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_HALT (0x8000)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
#define QSPI_QAR_TRANS (0x0000)
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Pulse Width Modulation (PWM)
*********************************************************************/
/* Bit definitions and macros for PWM_E */
#define PWM_EN_PWME7 (0x80)
#define PWM_EN_PWME5 (0x20)
#define PWM_EN_PWME3 (0x08)
#define PWM_EN_PWME1 (0x02)
/* Bit definitions and macros for PWM_POL */
#define PWM_POL_PPOL7 (0x80)
#define PWM_POL_PPOL5 (0x20)
#define PWM_POL_PPOL3 (0x08)
#define PWM_POL_PPOL1 (0x02)
/* Bit definitions and macros for PWM_CLK */
#define PWM_CLK_PCLK7 (0x80)
#define PWM_CLK_PCLK5 (0x20)
#define PWM_CLK_PCLK3 (0x08)
#define PWM_CLK_PCLK1 (0x02)
/* Bit definitions and macros for PWM_PRCLK */
#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
#define PWM_PRCLK_PCKA(x) ((x)&0x07)
/* Bit definitions and macros for PWM_CAE */
#define PWM_CAE_CAE7 (0x80)
#define PWM_CAE_CAE5 (0x20)
#define PWM_CAE_CAE3 (0x08)
#define PWM_CAE_CAE1 (0x02)
/* Bit definitions and macros for PWM_CTL */
#define PWM_CTL_CON67 (0x80)
#define PWM_CTL_CON45 (0x40)
#define PWM_CTL_CON23 (0x20)
#define PWM_CTL_CON01 (0x10)
#define PWM_CTL_PSWAR (0x08)
#define PWM_CTL_PFRZ (0x04)
/* Bit definitions and macros for PWM_SDN */
#define PWM_SDN_IF (0x80)
#define PWM_SDN_IE (0x40)
#define PWM_SDN_RESTART (0x20)
#define PWM_SDN_LVL (0x10)
#define PWM_SDN_PWM7IN (0x04)
#define PWM_SDN_PWM7IL (0x02)
#define PWM_SDN_SDNEN (0x01)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/

337
include/asm-m68k/m5445x.h
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@ -114,325 +114,6 @@
#define INT1_HI_PCI_ASR (56)
#define INT1_HI_PLL_LOCKS (57)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for IMRH */
#define INTC_IMRH_INT_MASK32 (0x00000001)
#define INTC_IMRH_INT_MASK33 (0x00000002)
#define INTC_IMRH_INT_MASK34 (0x00000004)
#define INTC_IMRH_INT_MASK35 (0x00000008)
#define INTC_IMRH_INT_MASK36 (0x00000010)
#define INTC_IMRH_INT_MASK37 (0x00000020)
#define INTC_IMRH_INT_MASK38 (0x00000040)
#define INTC_IMRH_INT_MASK39 (0x00000080)
#define INTC_IMRH_INT_MASK40 (0x00000100)
#define INTC_IMRH_INT_MASK41 (0x00000200)
#define INTC_IMRH_INT_MASK42 (0x00000400)
#define INTC_IMRH_INT_MASK43 (0x00000800)
#define INTC_IMRH_INT_MASK44 (0x00001000)
#define INTC_IMRH_INT_MASK45 (0x00002000)
#define INTC_IMRH_INT_MASK46 (0x00004000)
#define INTC_IMRH_INT_MASK47 (0x00008000)
#define INTC_IMRH_INT_MASK48 (0x00010000)
#define INTC_IMRH_INT_MASK49 (0x00020000)
#define INTC_IMRH_INT_MASK50 (0x00040000)
#define INTC_IMRH_INT_MASK51 (0x00080000)
#define INTC_IMRH_INT_MASK52 (0x00100000)
#define INTC_IMRH_INT_MASK53 (0x00200000)
#define INTC_IMRH_INT_MASK54 (0x00400000)
#define INTC_IMRH_INT_MASK55 (0x00800000)
#define INTC_IMRH_INT_MASK56 (0x01000000)
#define INTC_IMRH_INT_MASK57 (0x02000000)
#define INTC_IMRH_INT_MASK58 (0x04000000)
#define INTC_IMRH_INT_MASK59 (0x08000000)
#define INTC_IMRH_INT_MASK60 (0x10000000)
#define INTC_IMRH_INT_MASK61 (0x20000000)
#define INTC_IMRH_INT_MASK62 (0x40000000)
#define INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for IMRL */
#define INTC_IMRL_INT_MASK0 (0x00000001)
#define INTC_IMRL_INT_MASK1 (0x00000002)
#define INTC_IMRL_INT_MASK2 (0x00000004)
#define INTC_IMRL_INT_MASK3 (0x00000008)
#define INTC_IMRL_INT_MASK4 (0x00000010)
#define INTC_IMRL_INT_MASK5 (0x00000020)
#define INTC_IMRL_INT_MASK6 (0x00000040)
#define INTC_IMRL_INT_MASK7 (0x00000080)
#define INTC_IMRL_INT_MASK8 (0x00000100)
#define INTC_IMRL_INT_MASK9 (0x00000200)
#define INTC_IMRL_INT_MASK10 (0x00000400)
#define INTC_IMRL_INT_MASK11 (0x00000800)
#define INTC_IMRL_INT_MASK12 (0x00001000)
#define INTC_IMRL_INT_MASK13 (0x00002000)
#define INTC_IMRL_INT_MASK14 (0x00004000)
#define INTC_IMRL_INT_MASK15 (0x00008000)
#define INTC_IMRL_INT_MASK16 (0x00010000)
#define INTC_IMRL_INT_MASK17 (0x00020000)
#define INTC_IMRL_INT_MASK18 (0x00040000)
#define INTC_IMRL_INT_MASK19 (0x00080000)
#define INTC_IMRL_INT_MASK20 (0x00100000)
#define INTC_IMRL_INT_MASK21 (0x00200000)
#define INTC_IMRL_INT_MASK22 (0x00400000)
#define INTC_IMRL_INT_MASK23 (0x00800000)
#define INTC_IMRL_INT_MASK24 (0x01000000)
#define INTC_IMRL_INT_MASK25 (0x02000000)
#define INTC_IMRL_INT_MASK26 (0x04000000)
#define INTC_IMRL_INT_MASK27 (0x08000000)
#define INTC_IMRL_INT_MASK28 (0x10000000)
#define INTC_IMRL_INT_MASK29 (0x20000000)
#define INTC_IMRL_INT_MASK30 (0x40000000)
#define INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for INTFRCH */
#define INTC_INTFRCH_INTFRC32 (0x00000001)
#define INTC_INTFRCH_INTFRC33 (0x00000002)
#define INTC_INTFRCH_INTFRC34 (0x00000004)
#define INTC_INTFRCH_INTFRC35 (0x00000008)
#define INTC_INTFRCH_INTFRC36 (0x00000010)
#define INTC_INTFRCH_INTFRC37 (0x00000020)
#define INTC_INTFRCH_INTFRC38 (0x00000040)
#define INTC_INTFRCH_INTFRC39 (0x00000080)
#define INTC_INTFRCH_INTFRC40 (0x00000100)
#define INTC_INTFRCH_INTFRC41 (0x00000200)
#define INTC_INTFRCH_INTFRC42 (0x00000400)
#define INTC_INTFRCH_INTFRC43 (0x00000800)
#define INTC_INTFRCH_INTFRC44 (0x00001000)
#define INTC_INTFRCH_INTFRC45 (0x00002000)
#define INTC_INTFRCH_INTFRC46 (0x00004000)
#define INTC_INTFRCH_INTFRC47 (0x00008000)
#define INTC_INTFRCH_INTFRC48 (0x00010000)
#define INTC_INTFRCH_INTFRC49 (0x00020000)
#define INTC_INTFRCH_INTFRC50 (0x00040000)
#define INTC_INTFRCH_INTFRC51 (0x00080000)
#define INTC_INTFRCH_INTFRC52 (0x00100000)
#define INTC_INTFRCH_INTFRC53 (0x00200000)
#define INTC_INTFRCH_INTFRC54 (0x00400000)
#define INTC_INTFRCH_INTFRC55 (0x00800000)
#define INTC_INTFRCH_INTFRC56 (0x01000000)
#define INTC_INTFRCH_INTFRC57 (0x02000000)
#define INTC_INTFRCH_INTFRC58 (0x04000000)
#define INTC_INTFRCH_INTFRC59 (0x08000000)
#define INTC_INTFRCH_INTFRC60 (0x10000000)
#define INTC_INTFRCH_INTFRC61 (0x20000000)
#define INTC_INTFRCH_INTFRC62 (0x40000000)
#define INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for INTFRCL */
#define INTC_INTFRCL_INTFRC0 (0x00000001)
#define INTC_INTFRCL_INTFRC1 (0x00000002)
#define INTC_INTFRCL_INTFRC2 (0x00000004)
#define INTC_INTFRCL_INTFRC3 (0x00000008)
#define INTC_INTFRCL_INTFRC4 (0x00000010)
#define INTC_INTFRCL_INTFRC5 (0x00000020)
#define INTC_INTFRCL_INTFRC6 (0x00000040)
#define INTC_INTFRCL_INTFRC7 (0x00000080)
#define INTC_INTFRCL_INTFRC8 (0x00000100)
#define INTC_INTFRCL_INTFRC9 (0x00000200)
#define INTC_INTFRCL_INTFRC10 (0x00000400)
#define INTC_INTFRCL_INTFRC11 (0x00000800)
#define INTC_INTFRCL_INTFRC12 (0x00001000)
#define INTC_INTFRCL_INTFRC13 (0x00002000)
#define INTC_INTFRCL_INTFRC14 (0x00004000)
#define INTC_INTFRCL_INTFRC15 (0x00008000)
#define INTC_INTFRCL_INTFRC16 (0x00010000)
#define INTC_INTFRCL_INTFRC17 (0x00020000)
#define INTC_INTFRCL_INTFRC18 (0x00040000)
#define INTC_INTFRCL_INTFRC19 (0x00080000)
#define INTC_INTFRCL_INTFRC20 (0x00100000)
#define INTC_INTFRCL_INTFRC21 (0x00200000)
#define INTC_INTFRCL_INTFRC22 (0x00400000)
#define INTC_INTFRCL_INTFRC23 (0x00800000)
#define INTC_INTFRCL_INTFRC24 (0x01000000)
#define INTC_INTFRCL_INTFRC25 (0x02000000)
#define INTC_INTFRCL_INTFRC26 (0x04000000)
#define INTC_INTFRCL_INTFRC27 (0x08000000)
#define INTC_INTFRCL_INTFRC28 (0x10000000)
#define INTC_INTFRCL_INTFRC29 (0x20000000)
#define INTC_INTFRCL_INTFRC30 (0x40000000)
#define INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for ICONFIG */
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for SIMR */
#define INTC_SIMR_SIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CIMR */
#define INTC_CIMR_CIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CLMASK */
#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for SLMASK */
#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
/* Bit definitions and macros for EPPAR */
#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_EPPAR_LEVEL (0)
#define EPORT_EPPAR_RISING (1)
#define EPORT_EPPAR_FALLING (2)
#define EPORT_EPPAR_BOTH (3)
#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA7_RISING (0x4000)
#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA6_RISING (0x1000)
#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA5_RISING (0x0400)
#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA4_RISING (0x0100)
#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA3_RISING (0x0040)
#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA2_RISING (0x0010)
#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA1_RISING (0x0004)
#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
/* Bit definitions and macros for EPDDR */
#define EPORT_EPDDR_EPDD1 (0x02)
#define EPORT_EPDDR_EPDD2 (0x04)
#define EPORT_EPDDR_EPDD3 (0x08)
#define EPORT_EPDDR_EPDD4 (0x10)
#define EPORT_EPDDR_EPDD5 (0x20)
#define EPORT_EPDDR_EPDD6 (0x40)
#define EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for EPIER */
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for EPDR */
#define EPORT_EPDR_EPD1 (0x02)
#define EPORT_EPDR_EPD2 (0x04)
#define EPORT_EPDR_EPD3 (0x08)
#define EPORT_EPDR_EPD4 (0x10)
#define EPORT_EPDR_EPD5 (0x20)
#define EPORT_EPDR_EPD6 (0x40)
#define EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for EPPDR */
#define EPORT_EPPDR_EPPD1 (0x02)
#define EPORT_EPPDR_EPPD2 (0x04)
#define EPORT_EPPDR_EPPD3 (0x08)
#define EPORT_EPPDR_EPPD4 (0x10)
#define EPORT_EPPDR_EPPD5 (0x20)
#define EPORT_EPPDR_EPPD6 (0x40)
#define EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for EPFR */
#define EPORT_EPFR_EPF1 (0x02)
#define EPORT_EPFR_EPF2 (0x04)
#define EPORT_EPFR_EPF3 (0x08)
#define EPORT_EPFR_EPF4 (0x10)
#define EPORT_EPFR_EPF5 (0x20)
#define EPORT_EPFR_EPF6 (0x40)
#define EPORT_EPFR_EPF7 (0x80)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
@ -1039,24 +720,6 @@
#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
/* Bit definitions and macros for RNGCR */
#define RNG_RNGCR_GO (0x00000001)
#define RNG_RNGCR_HA (0x00000002)
#define RNG_RNGCR_IM (0x00000004)
#define RNG_RNGCR_CI (0x00000008)
/* Bit definitions and macros for RNGSR */
#define RNG_RNGSR_SV (0x00000001)
#define RNG_RNGSR_LRS (0x00000002)
#define RNG_RNGSR_FUF (0x00000004)
#define RNG_RNGSR_EI (0x00000008)
#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/

68
include/asm-m68k/m547x_8x.h
View File

@ -305,74 +305,6 @@
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/

16
include/configs/EB+MCF-EV123.h
View File

@ -178,7 +178,7 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
@ -218,17 +218,13 @@
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE 2*1024*1024
#define CONFIG_SYS_CS0_WIDTH 16
#define CONFIG_SYS_CS0_RO 0
#define CONFIG_SYS_CS0_WS 6
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_CS3_BASE 0xE0000000
#define CONFIG_SYS_CS3_SIZE 1*1024*1024
#define CONFIG_SYS_CS3_WIDTH 16
#define CONFIG_SYS_CS3_RO 0
#define CONFIG_SYS_CS3_WS 6
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS3_MASK 0x000F0001
/*-----------------------------------------------------------------------
* Port configuration

153
include/configs/M52277EVB.h
View File

@ -40,7 +40,7 @@
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
@ -72,21 +72,50 @@
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_BMP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_HOSTNAME M52277EVB
#define CONFIG_HOSTNAME M52277EVB
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS \
"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate};" \
"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"upd=run load; run prog\0" \
"prog=prot off 0 0x3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"prog=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
"save\0" \
""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS \
"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate}\0" \
"upd=run load; run prog\0" \
"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
" " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
"era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
MK_STR(CONFIG_SYS_UBOOT_END) ";" \
"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
" ${filesize}; save\0" \
"updsbf=run loadsbf; run progsbf\0" \
"loadsbf=loadb ${loadaddr} ${baudrate};" \
"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"progsbf=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
""
#endif
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
@ -102,7 +131,7 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif
@ -122,30 +151,53 @@
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2
# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
DSPI_DCTAR_CPOL | \
DSPI_DCTAR_CPHA | \
DSPI_DCTAR_PCSSCK_1CLK | \
DSPI_DCTAR_PASC(0) | \
DSPI_DCTAR_PDT(0) | \
DSPI_DCTAR_CSSCK(0) | \
DSPI_DCTAR_ASC(0) | \
DSPI_DCTAR_PBR(0) | \
DSPI_DCTAR_DT(1) | \
DSPI_DCTAR_BR(1))
#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_SYS_INPUT_CLKSRC 16000000
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_PRAM 2048 /* 2048 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MBAR 0xFC000000
@ -155,17 +207,18 @@
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 16)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
/*-----------------------------------------------------------------------
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
@ -177,11 +230,16 @@
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x81810000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#ifdef CONFIG_CF_SBF
# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
@ -189,24 +247,40 @@
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
/*
* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#ifdef CONFIG_CF_SBF
# define CONFIG_ENV_IS_IN_SPI_FLASH
# define CONFIG_ENV_SPI_CS 2
#else
# define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define CONFIG_ENV_OVERWRITE 1
#undef CONFIG_ENV_IS_EMBEDDED
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
#define CONFIG_ENV_SECT_SIZE 0x8000
#ifdef CONFIG_SYS_STMICRO_BOOT
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_ENV_OFFSET 0x30000
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_SECT_SIZE 0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_SECT_SIZE 0x8000
#endif
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
@ -214,6 +288,7 @@
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CONFIG_SYS_FLASH_CHECKSUM
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
#endif
/*
@ -229,7 +304,7 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
@ -243,8 +318,14 @@
* CS5 - Available
*/
#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE 0x04000000
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE 0x00000000
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#endif
#endif /* _M52277EVB_H */

10
include/configs/M5235EVB.h
View File

@ -215,7 +215,7 @@
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@ -251,13 +251,13 @@
* CS7 - Available
*/
#ifdef NORFLASH_PS32BIT
# define CONFIG_SYS_CS0_BASE 0xFFC0
# define CONFIG_SYS_CS0_BASE 0xFFC00000
# define CONFIG_SYS_CS0_MASK 0x003f0001
# define CONFIG_SYS_CS0_CTRL 0x1D00
# define CONFIG_SYS_CS0_CTRL 0x00001D00
#else
# define CONFIG_SYS_CS0_BASE 0xFFE0
# define CONFIG_SYS_CS0_BASE 0xFFE00000
# define CONFIG_SYS_CS0_MASK 0x001f0001
# define CONFIG_SYS_CS0_CTRL 0x1D80
# define CONFIG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */

14
include/configs/M5249EVB.h
View File

@ -125,7 +125,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@ -170,15 +170,15 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CSAR0 0xffe0
#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CSAR1 0xe000
#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration

24
include/configs/M5253DEMO.h
View File

@ -90,7 +90,7 @@
#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) | 0x300)
# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
@ -202,7 +202,7 @@
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
@ -233,21 +233,13 @@
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
#define CONFIG_SYS_CSAR0 0xFF80
#define CONFIG_SYS_CSMR0 0x007F0021
#define CONFIG_SYS_CSCR0 0x1D80
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK 0x007F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
#define CONFIG_SYS_CSAR1 0xE000
#define CONFIG_SYS_CSMR1 0x00000001
#define CONFIG_SYS_CSCR1 0x3DD8
#define CONFIG_SYS_CSAR2 0
#define CONFIG_SYS_CSMR2 0
#define CONFIG_SYS_CSCR2 0
#define CONFIG_SYS_CSAR3 0
#define CONFIG_SYS_CSMR3 0
#define CONFIG_SYS_CSCR3 0
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK 0x00000001
#define CONFIG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration

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