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https://github.com/u-boot/u-boot.git
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Merge git://git.denx.de/u-boot-sunxi
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commit
abeb9d7897
@ -147,19 +147,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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oclk_dly = 0;
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sclk_dly = 5;
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#ifdef CONFIG_MACH_SUN9I
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} else if (hz <= 50000000) {
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} else if (hz <= 52000000) {
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oclk_dly = 5;
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sclk_dly = 4;
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} else {
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/* hz > 50000000 */
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/* hz > 52000000 */
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oclk_dly = 2;
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sclk_dly = 4;
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#else
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} else if (hz <= 50000000) {
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} else if (hz <= 52000000) {
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oclk_dly = 3;
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sclk_dly = 4;
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} else {
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/* hz > 50000000 */
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/* hz > 52000000 */
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oclk_dly = 1;
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sclk_dly = 4;
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#endif
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@ -188,15 +188,16 @@ static int mmc_update_clk(struct sunxi_mmc_priv *priv)
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{
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unsigned int cmd;
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unsigned timeout_msecs = 2000;
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unsigned long start = get_timer(0);
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cmd = SUNXI_MMC_CMD_START |
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SUNXI_MMC_CMD_UPCLK_ONLY |
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SUNXI_MMC_CMD_WAIT_PRE_OVER;
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writel(cmd, &priv->reg->cmd);
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while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
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if (!timeout_msecs--)
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if (get_timer(start) > timeout_msecs)
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return -1;
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udelay(1000);
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}
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/* clock update sets various irq status bits, clear these */
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@ -277,18 +278,21 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
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unsigned i;
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unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
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unsigned byte_cnt = data->blocksize * data->blocks;
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unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
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if (timeout_usecs < 2000000)
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timeout_usecs = 2000000;
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unsigned timeout_msecs = byte_cnt >> 8;
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unsigned long start;
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if (timeout_msecs < 2000)
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timeout_msecs = 2000;
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/* Always read / write data through the CPU */
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setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
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start = get_timer(0);
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for (i = 0; i < (byte_cnt >> 2); i++) {
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while (readl(&priv->reg->status) & status_bit) {
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if (!timeout_usecs--)
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if (get_timer(start) > timeout_msecs)
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return -1;
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udelay(1);
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}
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if (reading)
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@ -304,16 +308,16 @@ static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
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uint timeout_msecs, uint done_bit, const char *what)
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{
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unsigned int status;
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unsigned long start = get_timer(0);
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do {
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status = readl(&priv->reg->rint);
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if (!timeout_msecs-- ||
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if ((get_timer(start) > timeout_msecs) ||
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(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
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debug("%s timeout %x\n", what,
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status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
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return -ETIMEDOUT;
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}
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udelay(1000);
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} while (!(status & done_bit));
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return 0;
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@ -405,15 +409,16 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
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}
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if (cmd->resp_type & MMC_RSP_BUSY) {
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unsigned long start = get_timer(0);
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timeout_msecs = 2000;
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do {
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status = readl(&priv->reg->status);
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if (!timeout_msecs--) {
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if (get_timer(start) > timeout_msecs) {
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debug("busy timeout\n");
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error = -ETIMEDOUT;
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goto out;
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}
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udelay(1000);
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} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
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}
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