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MIPS: make cache operation mode configurable

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Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
This commit is contained in:
Daniel Schwierzeck 2011-07-27 13:22:38 +02:00 committed by Shinya Kuribayashi
parent 7185adb48e
commit ab2a98b117
1 changed files with 5 additions and 1 deletions
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6
arch/mips/cpu/mips32/start.S
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@ -27,6 +27,10 @@
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
@ -249,7 +253,7 @@ reset:
nop
/* ... and enable them */
li t0, CONF_CM_CACHABLE_NONCOHERENT
li t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
#endif