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ppc: Remove MPC8541CDS board
This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
5fe4c0cc6e
commit
a8571337d7
@ -44,11 +44,6 @@ config TARGET_P5040DS
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imply CMD_SATA
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imply PANIC_HANG
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config TARGET_MPC8541CDS
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bool "Support MPC8541CDS"
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select ARCH_MPC8541
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select FSL_VIA
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config TARGET_MPC8548CDS
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bool "Support MPC8548CDS"
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select ARCH_MPC8548
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@ -364,14 +359,6 @@ config ARCH_MPC8540
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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config ARCH_MPC8541
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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config ARCH_MPC8544
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bool
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select FSL_LAW
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@ -959,7 +946,6 @@ config SYS_CCSRBAR_DEFAULT
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ARCH_C29X || \
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ARCH_MPC8536 || \
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ARCH_MPC8540 || \
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ARCH_MPC8541 || \
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ARCH_MPC8544 || \
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ARCH_MPC8548 || \
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ARCH_MPC8555 || \
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@ -1193,7 +1179,6 @@ config SYS_FSL_NUM_LAWS
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ARCH_MPC8548 || \
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ARCH_MPC8568
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default 8 if ARCH_MPC8540 || \
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ARCH_MPC8541 || \
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ARCH_MPC8555 || \
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ARCH_MPC8560
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help
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@ -1267,7 +1252,7 @@ config SYS_FSL_IFC_CLK_DIV
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config SYS_FSL_LBC_CLK_DIV
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int "Divider of platform clock"
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depends on FSL_ELBC || ARCH_MPC8540 || \
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ARCH_MPC8548 || ARCH_MPC8541 || \
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ARCH_MPC8548 || \
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ARCH_MPC8555 || ARCH_MPC8560 || \
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ARCH_MPC8568
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@ -1286,7 +1271,6 @@ config FSL_VIA
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source "board/emulation/qemu-ppce500/Kconfig"
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source "board/freescale/corenet_ds/Kconfig"
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source "board/freescale/mpc8541cds/Kconfig"
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source "board/freescale/mpc8548cds/Kconfig"
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source "board/freescale/mpc8555cds/Kconfig"
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source "board/freescale/mpc8568mds/Kconfig"
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@ -301,8 +301,8 @@ int checkcpu (void)
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int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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/* Everything after the first generation of PQ3 parts has RSTCR */
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8555) || \
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defined(CONFIG_ARCH_MPC8560)
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unsigned long val, msr;
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/*
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@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
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pci_register_hose(hose);
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#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
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#if defined(CONFIG_TARGET_MPC8555CDS)
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/*
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* This is a SW workaround for an apparent HW problem
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* in the PCI controller on the MPC85555/41 CDS boards.
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@ -607,8 +607,8 @@ int get_clocks(void)
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560) || \
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defined(CONFIG_ARCH_MPC8555)
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gd->arch.i2c1_clk = sys_info.freq_systembus;
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#elif defined(CONFIG_ARCH_MPC8544)
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/*
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@ -77,7 +77,7 @@
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*/
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#define CPM_DATAONLY_BASE ((uint)128)
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#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
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#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
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#if defined(CONFIG_ARCH_MPC8555)
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#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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#else /* MPC8540, MPC8560 */
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@ -325,8 +325,7 @@ void lbc_sdram_init(void);
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#define LCRR_CLKDIV 0x0000001F
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#define LCRR_CLKDIV_SHIFT 0
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#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
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defined(CONFIG_ARCH_MPC8560)
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defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
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#define LCRR_CLKDIV_2 0x00000002
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#define LCRR_CLKDIV_4 0x00000004
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#define LCRR_CLKDIV_8 0x00000008
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@ -124,7 +124,6 @@ typedef struct ccsr_i2c {
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} ccsr_i2c_t;
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#if defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_ARCH_MPC8548) || \
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defined(CONFIG_ARCH_MPC8555)
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/* DUART Registers */
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@ -43,7 +43,6 @@ endif
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obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
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obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o
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obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
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obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
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@ -1,12 +0,0 @@
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if TARGET_MPC8541CDS
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config SYS_BOARD
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default "mpc8541cds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8541CDS"
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endif
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@ -1,7 +0,0 @@
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MPC8541CDS BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/mpc8541cds/
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F: include/configs/MPC8541CDS.h
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F: configs/MPC8541CDS_defconfig
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F: configs/MPC8541CDS_legacy_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc8541cds.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -1,53 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 6;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@ -1,41 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
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* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -1,429 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2004, 2011 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <pci.h>
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#include <vsprintf.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <fsl_ddr_sdram.h>
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#include <ioports.h>
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#include <spd_sdram.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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void local_bus_init(void);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
||||
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
||||
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
||||
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
char buf[32];
|
||||
|
||||
/* PCI slot in USER bits CSR[6:7] by convention. */
|
||||
uint pci_slot = get_pci_slot ();
|
||||
|
||||
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
|
||||
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
|
||||
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
|
||||
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
|
||||
|
||||
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
|
||||
|
||||
uint cpu_board_rev = get_cpu_board_revision ();
|
||||
|
||||
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
|
||||
get_board_version (), pci_slot);
|
||||
|
||||
printf ("CPU Board Revision %d.%d (0x%04x)\n",
|
||||
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
|
||||
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
|
||||
|
||||
printf("PCI1: %d bit, %s MHz, %s\n",
|
||||
(pci1_32) ? 32 : 64,
|
||||
strmhz(buf, pci1_speed),
|
||||
pci1_clk_sel ? "sync" : "async");
|
||||
|
||||
if (pci_dual) {
|
||||
printf("PCI2: 32 bit, 66 MHz, %s\n",
|
||||
pci2_clk_sel ? "sync" : "async");
|
||||
} else {
|
||||
printf("PCI2: disabled\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
local_bus_init ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
void
|
||||
local_bus_init(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
||||
|
||||
uint clkdiv;
|
||||
uint lbc_hz;
|
||||
sys_info_t sysinfo;
|
||||
uint temp_lbcdll;
|
||||
|
||||
/*
|
||||
* Errata LBC11.
|
||||
* Fix Local Bus clock glitch when DLL is enabled.
|
||||
*
|
||||
* If localbus freq is < 66MHz, DLL bypass mode must be used.
|
||||
* If localbus freq is > 133MHz, DLL can be safely enabled.
|
||||
* Between 66 and 133, the DLL is enabled with an override workaround.
|
||||
*/
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
clkdiv = lbc->lcrr & LCRR_CLKDIV;
|
||||
lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
|
||||
|
||||
if (lbc_hz < 66) {
|
||||
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
|
||||
|
||||
} else if (lbc_hz >= 133) {
|
||||
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
|
||||
|
||||
} else {
|
||||
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
|
||||
udelay(200);
|
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the
|
||||
* override bits.
|
||||
*/
|
||||
temp_lbcdll = gur->lbcdllcr;
|
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
||||
asm("sync;isync;msync");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus.
|
||||
*/
|
||||
void lbc_sdram_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
|
||||
|
||||
uint idx;
|
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
||||
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
|
||||
uint cpu_board_rev;
|
||||
uint lsdmr_common;
|
||||
|
||||
puts("LBC SDRAM: ");
|
||||
print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
|
||||
"\n ");
|
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers
|
||||
*/
|
||||
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
|
||||
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
|
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
|
||||
asm("msync");
|
||||
|
||||
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
|
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
|
||||
asm("msync");
|
||||
|
||||
/*
|
||||
* Determine which address lines to use baed on CPU board rev.
|
||||
*/
|
||||
cpu_board_rev = get_cpu_board_revision();
|
||||
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
|
||||
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
|
||||
lsdmr_common |= LSDMR_BSMA1617;
|
||||
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
|
||||
lsdmr_common |= LSDMR_BSMA1516;
|
||||
} else {
|
||||
/*
|
||||
* Assume something unable to identify itself is
|
||||
* really old, and likely has lines 16/17 mapped.
|
||||
*/
|
||||
lsdmr_common |= LSDMR_BSMA1617;
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue PRECHARGE ALL command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue 8 AUTO REFRESH commands.
|
||||
*/
|
||||
for (idx = 0; idx < 8; idx++) {
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue 8 MODE-set command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue NORMAL OP command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(200); /* Overkill. Must wait > 200 bus cycles */
|
||||
|
||||
#endif /* enable SDRAM init */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it.
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{ config_table: pci_mpc85xxcds_config_table,},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_mpc85xx_init(hose);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = hose[0].last_busno - hose[0].first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = hose[1].last_busno - hose[1].first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -1,95 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI1 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
* 0xa0000000 256M PCI2 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded
|
||||
* 0xb0000000 256M PCI2 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 16M PCI1 IO
|
||||
* 0xe300_0000 16M PCI2 IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded
|
||||
* 0xf8000000 1M CADMUS registers
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -1,40 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xfff80000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8541CDS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_REGINFO=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xFFFC0000
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,41 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xfff80000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8541CDS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_REGINFO=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xFFFC0000
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1866,7 +1866,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
|
||||
unsigned int clk_adjust; /* Clock adjust */
|
||||
unsigned int ss_en = 0; /* Source synchronous enable */
|
||||
|
||||
#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
|
||||
#if defined(CONFIG_ARCH_MPC8555)
|
||||
/* Per FSL Application Note: AN2805 */
|
||||
ss_en = 1;
|
||||
#endif
|
||||
|
||||
@ -48,7 +48,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
||||
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
|
||||
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
|
||||
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
|
||||
#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
|
||||
#if defined(CONFIG_ARCH_MPC8555)
|
||||
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,384 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2004, 2011 Freescale Semiconductor.
|
||||
*/
|
||||
|
||||
/*
|
||||
* mpc8541cds board configuration file
|
||||
*
|
||||
* Please refer to doc/README.mpc85xxcds for more info.
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_clock_freq(void);
|
||||
#endif
|
||||
#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xe0000000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
|
||||
#define CONFIG_DDR_SPD
|
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
|
||||
|
||||
/*
|
||||
* Make sure required options are set
|
||||
*/
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
* Two banks, 8M each, using the CFI driver.
|
||||
* Boot from BR0/OR0 bank at 0xff00_0000
|
||||
* Alternate BR1/OR1 bank at 0xff80_0000
|
||||
*
|
||||
* BR0, BR1:
|
||||
* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
|
||||
* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
|
||||
* Port Size = 16 bits = BRx[19:20] = 10
|
||||
* Use GPCM = BRx[24:26] = 000
|
||||
* Valid = BRx[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
|
||||
* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
|
||||
*
|
||||
* OR0, OR1:
|
||||
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
|
||||
* Reserved ORx[17:18] = 11, confusion here?
|
||||
* CSNT = ORx[20] = 1
|
||||
* ACS = half cycle delay = ORx[21:22] = 11
|
||||
* SCY = 6 = ORx[24:27] = 0110
|
||||
* TRLX = use relaxed timing = ORx[29] = 1
|
||||
* EAD = use external address latch delay = OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xff801001
|
||||
#define CONFIG_SYS_BR1_PRELIM 0xff001001
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xff806e65
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM.
|
||||
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
|
||||
*
|
||||
* For BR2, need:
|
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
|
||||
* port-size = 32-bits = BR2[19:20] = 11
|
||||
* no parity checking = BR2[21:22] = 00
|
||||
* SDRAM for MSEL = BR2[24:26] = 011
|
||||
* Valid = BR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
|
||||
*
|
||||
* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
|
||||
* FIXME: the top 17 bits of BR2.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0001861
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
||||
*
|
||||
* For OR2, need:
|
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100
|
||||
* XAM, OR2[17:18] = 11
|
||||
* 9 columns OR2[19-21] = 010
|
||||
* 13 rows OR2[23-25] = 100
|
||||
* EAD set for extra time OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
|
||||
|
||||
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
|
||||
|
||||
/*
|
||||
* Common settings for all Local Bus SDRAM commands.
|
||||
* At run time, either BSMA1516 (for CPU 1.1)
|
||||
* or BSMA1617 (for CPU 1.0) (old)
|
||||
* is OR'ed in too.
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
|
||||
| LSDMR_PRETOACT7 \
|
||||
| LSDMR_ACTTORW7 \
|
||||
| LSDMR_BL8 \
|
||||
| LSDMR_WRC4 \
|
||||
| LSDMR_CL3 \
|
||||
| LSDMR_RFEN \
|
||||
)
|
||||
|
||||
/*
|
||||
* The CADMUS registers are connected to CS3 on CDS.
|
||||
* The new memory map places CADMUS at 0xf8000000.
|
||||
*
|
||||
* For BR3, need:
|
||||
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
|
||||
* port-size = 8-bits = BR[19:20] = 01
|
||||
* no parity checking = BR[21:22] = 00
|
||||
* GPMC for MSEL = BR[24:26] = 000
|
||||
* Valid = BR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
|
||||
*
|
||||
* For OR3, need:
|
||||
* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
|
||||
* disable buffer ctrl OR[19] = 0
|
||||
* CSNT OR[20] = 1
|
||||
* ACS OR[21:22] = 11
|
||||
* XACS OR[23] = 1
|
||||
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
|
||||
* SETA OR[28] = 0
|
||||
* TRLX OR[29] = 1
|
||||
* EHTR OR[30] = 1
|
||||
* EAD extra time OR[31] = 1
|
||||
*
|
||||
* 0 4 8 12 16 20 24 28
|
||||
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
|
||||
*/
|
||||
|
||||
#define CONFIG_FSL_CADMUS
|
||||
|
||||
#define CADMUS_BASE_ADDR 0xf8000000
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xf8000801
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_CCID
|
||||
#define CONFIG_SYS_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
|
||||
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
|
||||
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
|
||||
#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
|
||||
#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#ifdef CONFIG_LEGACY
|
||||
#define BRIDGE_ID 17
|
||||
#define VIA_ID 2
|
||||
#else
|
||||
#define BRIDGE_ID 28
|
||||
#define VIA_ID 4
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_MPC85XX_PCI2
|
||||
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
/* The mac addresses for all ethernet interface */
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.253
|
||||
|
||||
#define CONFIG_HOSTNAME "unknown"
|
||||
#define CONFIG_ROOTPATH "/nfsroot"
|
||||
#define CONFIG_BOOTFILE "your.uImage"
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS1\0" \
|
||||
"ramdiskaddr=600000\0" \
|
||||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=your.fdt.dtb\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user