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* Update PK1C20 board for Nios-II 5.0
Patch from Scott McNutt, 11 Aug 2005 -Update base addresses for standard configuration -Eliminate use of CACHE_BYPASS in board code
This commit is contained in:
Heiko Schocher
parent
7fd392c2d0
commit
a83531bb62
@ -2,14 +2,19 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Update PK1C20 board for Nios-II 5.0
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Patch from Scott McNutt, 11 Aug 2005
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-Update base addresses for standard configuration
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-Eliminate use of CACHE_BYPASS in board code
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* Add EPCS Controller bootrom work-around for Nios-II
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Patch from Scott McNutt 11, Aug 2005
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Patch from Scott McNutt, 11 Aug 2005
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-When booting from an epcs controller, the epcs bootrom may leave the
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slave select in an asserted state causing soft reset hang. This
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patch ensures slave select is negated at reset.
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* Fix I/O Macros and mini-app stubs for Nios-II
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Patch from Scott McNutt 11, Aug 2005
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Patch from Scott McNutt, 11 Aug 2005
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-Fix asm/io.h macros
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-Eliminate use of CACHE_BYPASS in cpu code
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-Eliminate assembler warnings
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@ -26,7 +26,7 @@
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#if defined(CONFIG_NIOS)
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#include <nios.h>
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#else
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#include <nios2.h>
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#include <asm/io.h>
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#endif
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#define SECTSZ (64 * 1024)
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@ -56,9 +56,8 @@ unsigned long flash_init (void)
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void flash_print_info (flash_info_t * info)
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{
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int i, k;
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unsigned long size;
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int erased;
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volatile unsigned char *flash;
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unsigned long *addr;
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printf (" Size: %ld KB in %d Sectors\n",
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info->size >> 10, info->sector_count);
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@ -66,14 +65,10 @@ void flash_print_info (flash_info_t * info)
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for (i = 0; i < info->sector_count; ++i) {
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/* Check if whole sector is erased */
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if (i != (info->sector_count - 1))
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size = info->start[i + 1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
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for (k = 0; k < size; k++) {
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if (*flash++ != 0xff) {
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addr = (unsigned long *) info->start[i];
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for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
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if ( readl(addr++) != (unsigned long)-1) {
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erased = 0;
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break;
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}
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@ -83,7 +78,7 @@ void flash_print_info (flash_info_t * info)
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s%s",
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CACHE_NO_BYPASS(info->start[i]),
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info->start[i],
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erased ? " E" : " ",
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info->protect[i] ? "RO " : " ");
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}
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@ -95,9 +90,8 @@ void flash_print_info (flash_info_t * info)
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
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CACHE_BYPASS(info->start[0]);
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volatile CFG_FLASH_WORD_SIZE *addr2;
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unsigned char *addr = (unsigned char *) info->start[0];
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unsigned char *addr2;
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int prot, sect;
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ulong start;
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@ -127,19 +121,18 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
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*/
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr2 = (CFG_FLASH_WORD_SIZE *)
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CACHE_BYPASS((info->start[sect]));
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*addr = 0xaa;
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*addr = 0x55;
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*addr = 0x80;
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*addr = 0xaa;
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*addr = 0x55;
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*addr2 = 0x30;
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addr2 = (unsigned char *) info->start[sect];
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writeb (addr, 0xaa);
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writeb (addr, 0x55);
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writeb (addr, 0x80);
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writeb (addr, 0xaa);
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writeb (addr, 0x55);
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writeb (addr2, 0x30);
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/* Now just wait for 0xff & provide some user
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* feedback while we wait.
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*/
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start = get_timer (0);
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while (*addr2 != 0xff) {
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while ( readb (addr2) != 0xff) {
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udelay (1000 * 1000);
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putc ('.');
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if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
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@ -163,27 +156,27 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
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vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
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vu_char *cmd = (vu_char *) info->start[0];
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vu_char *dst = (vu_char *) addr;
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unsigned char b;
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ulong start;
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while (cnt) {
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/* Check for sufficient erase */
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b = *src;
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if ((*dst & b) != b) {
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printf ("%02x : %02x\n", *dst, b);
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if ((readb (dst) & b) != b) {
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printf ("%02x : %02x\n", readb (dst), b);
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return (2);
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}
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*cmd = 0xaa;
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*cmd = 0x55;
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*cmd = 0xa0;
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*dst = b;
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writeb (cmd, 0xaa);
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writeb (cmd, 0x55);
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writeb (cmd, 0xa0);
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writeb (dst, b);
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/* Verify write */
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start = get_timer (0);
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while (*dst != b) {
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while (readb (dst) != b) {
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if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
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return 1;
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}
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@ -21,7 +21,7 @@
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0x018e0000
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TEXT_BASE = 0x01fc0000
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PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
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PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
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@ -22,7 +22,7 @@
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*/
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#include <common.h>
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#include <nios2.h>
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#include <asm/io.h>
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#include <nios2-io.h>
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#include <status_led.h>
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@ -33,30 +33,30 @@ static led_id_t val = 0;
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void __led_init (led_id_t mask, int state)
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{
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nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
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nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
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if (state == STATUS_LED_ON)
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val &= ~mask;
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else
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val |= mask;
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pio->data = val;
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writel (&pio->data, val);
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}
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void __led_set (led_id_t mask, int state)
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{
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nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
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nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
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if (state == STATUS_LED_ON)
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val &= ~mask;
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else
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val |= mask;
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pio->data = val;
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writel (&pio->data, val);
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}
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void __led_toggle (led_id_t mask)
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{
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nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
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nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
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val ^= mask;
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pio->data = val;
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writel (&pio->data, val);
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}
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@ -32,7 +32,7 @@
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#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
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#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
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#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */
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#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
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/*------------------------------------------------------------------------
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@ -51,7 +51,7 @@
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#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
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#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
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#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
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#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */
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#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
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#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
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/*------------------------------------------------------------------------
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@ -61,7 +61,7 @@
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* -Global data is placed below the heap.
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* -The stack is placed below global data (&grows down).
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
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#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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@ -95,9 +95,9 @@
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* CONSOLE
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CONSOLE_JTAG)
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#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
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#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
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#else
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#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */
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#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
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#endif
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#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
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@ -110,9 +110,9 @@
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* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
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* epcs device access is enabled. The base address is the epcs
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* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
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* The register base is currently at offset 0x400 from the memory base.
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* The register base is currently at offset 0x600 from the memory base.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */
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#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
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/*------------------------------------------------------------------------
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* DEBUG
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@ -126,7 +126,7 @@
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* registers, we can slow it down to 10 msec using TMRCNT. If the default
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* period is acceptable, TMRCNT can be left undefined.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
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#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
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#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
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#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
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#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
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@ -137,7 +137,7 @@
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* must implement its own led routines -- leds are, after all,
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* board-specific, no?
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*----------------------------------------------------------------------*/
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#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */
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#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
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#define CONFIG_STATUS_LED /* Enable status driver */
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#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
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@ -150,7 +150,7 @@
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* way out to avoid changes there -- define the base address to ensure
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* cache bypass so there's no need to monkey with inx/outx macros.
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*----------------------------------------------------------------------*/
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#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */
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#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
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#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
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#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
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#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
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