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NAND FSL UPM: driver re-write using the hwcontrol callback
This is a re-write of the NAND FSL UPM driver using the more universal
hwcontrol callback (instead of the cmdfunc callback). Here is a brief
list of furher modifications:
- For the time being, the UPM setup writing the UPM array has been
removed from the driver and must now be done by the board specific
code.
- The bus width definition in "struct fsl_upm_nand" is now in bits to
comply with the corresponding Linux driver and 8, 16 and 32 bit
accesses are supported.
- chip->dev_read is only set if fun->dev_ready != NULL, which is
required for boards not connecting the R/B pin.
- A few issue have been fixed with MxMR bit manipulation like in the
corresponding Linux driver.
Note: I think the "io_addr" field of "struct fsl_upm" could be removed
as well, because the address is already determined by
"nand->IO_ADDR_[RW]", but I'm not 100% sure.
This patch has been tested on a TQM8548 modules with the NAND chip
Micron MT29F8G08FABWP.
This patch is based on the following patches posted to this list a few
minutes ago:
PPC: add accessor macros to clear and set bits in one shot
83xx/85xx/86xx: add more MxMR local bus definitions
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
This commit is contained in:
Wolfgang Grandegger
Andrew Fleming-AFLEMING
parent
6beecfbb54
commit
a75a57ef6e
@ -20,102 +20,56 @@
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#include <linux/mtd/fsl_upm.h>
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#include <nand.h>
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#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
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#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
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#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
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#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
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static int fsl_upm_in_pattern;
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static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
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{
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out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
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clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
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}
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static void fsl_upm_end_pattern(struct fsl_upm *upm)
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{
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out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
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while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
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clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
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while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
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eieio();
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}
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static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
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{
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out_be32(upm->mar, cmd << (32 - width * 8));
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out_8(upm->io_addr, 0x0);
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}
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static void fsl_upm_setup(struct fsl_upm *upm)
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{
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int i;
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/* write upm array */
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out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
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for (i = 0; i < 64; i++) {
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out_be32(upm->mdr, upm->array[i]);
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out_be32(upm->mar, cmd << (32 - width));
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switch (width) {
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case 8:
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out_8(upm->io_addr, 0x0);
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break;
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case 16:
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out_be16(upm->io_addr, 0x0);
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break;
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case 32:
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out_be32(upm->io_addr, 0x0);
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break;
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}
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/* normal operation */
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out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
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while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
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eieio();
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}
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static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
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int page_addr)
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static void nand_hwcontrol (struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_upm_nand *fun = chip->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->oobblock) {
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/* OOB area */
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column -= mtd->oobblock;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
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}
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fsl_upm_run_pattern(&fun->upm, fun->width, command);
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fsl_upm_end_pattern(&fun->upm);
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fsl_upm_in_pattern++;
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break;
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case NAND_CTL_SETALE:
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fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
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if (column != -1)
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fsl_upm_run_pattern(&fun->upm, fun->width, column);
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if (page_addr != -1) {
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fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
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fsl_upm_run_pattern(&fun->upm, fun->width,
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(page_addr >> 8) & 0xFF);
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if (chip->chipsize > (32 << 20)) {
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fsl_upm_run_pattern(&fun->upm, fun->width,
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(page_addr >> 16) & 0x0f);
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}
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}
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fsl_upm_in_pattern++;
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break;
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case NAND_CTL_CLRCLE:
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case NAND_CTL_CLRALE:
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fsl_upm_end_pattern(&fun->upm);
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if (fun->wait_pattern) {
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/*
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* Some boards/chips needs this. At least on MPC8360E-RDK we
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* need it. Probably weird chip, because I don't see any need
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* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
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* 0-2 unexpected busy states per block read.
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*/
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while (!fun->dev_ready())
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debug("unexpected busy state\n");
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fsl_upm_in_pattern--;
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break;
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}
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}
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@ -123,7 +77,24 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *chip = mtd->priv;
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if (fsl_upm_in_pattern) {
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struct fsl_upm_nand *fun = chip->priv;
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fsl_upm_run_pattern(&fun->upm, fun->width, byte);
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/*
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* Some boards/chips needs this. At least on MPC8360E-RDK we
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* need it. Probably weird chip, because I don't see any need
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* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
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* 0-2 unexpected busy states per block read.
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*/
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if (fun->wait_pattern) {
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while (!fun->dev_ready())
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debug("unexpected busy state\n");
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}
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} else {
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out_8(chip->IO_ADDR_W, byte);
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}
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}
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static u8 nand_read_byte(struct mtd_info *mtd)
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@ -164,10 +135,6 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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return 0;
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}
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static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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}
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static int nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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@ -178,22 +145,19 @@ static int nand_dev_ready(struct mtd_info *mtd)
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int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
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{
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/* yet only 8 bit accessors implemented */
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if (fun->width != 1)
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if (fun->width != 8 && fun->width != 16 && fun->width != 32)
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return -ENOSYS;
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fsl_upm_setup(&fun->upm);
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chip->priv = fun;
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chip->chip_delay = fun->chip_delay;
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chip->eccmode = NAND_ECC_SOFT;
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chip->cmdfunc = fun_cmdfunc;
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chip->hwcontrol = nand_hwcontrol;
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chip->read_byte = nand_read_byte;
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chip->read_buf = nand_read_buf;
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chip->write_byte = nand_write_byte;
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chip->write_buf = nand_write_buf;
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chip->verify_buf = nand_verify_buf;
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if (fun->dev_ready)
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chip->dev_ready = nand_dev_ready;
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return 0;
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@ -16,7 +16,6 @@
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#include <linux/mtd/nand.h>
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struct fsl_upm {
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const u32 *array;
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void __iomem *mdr;
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void __iomem *mxmr;
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void __iomem *mar;
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