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ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
This commit is contained in:
Allen Martin
Simon Glass
parent
754204b5c2
commit
a6c7b46181
@ -6,6 +6,15 @@ choice
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config TARGET_JETSON_TK1
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bool "NVIDIA Tegra124 Jetson TK1 board"
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config TARGET_NYAN_BIG
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bool "Google/NVIDIA Nyan-big Chrombook"
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help
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Nyan Big is a Tegra124 clamshell board that is very similar
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to venice2, but it has a different panel, the sdcard CD and WP
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sense are flipped, and it has a different revision of the AS3722
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PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
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(13.3-inch HD, NVIDIA Tegra K1, 2GB).
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config TARGET_VENICE2
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bool "NVIDIA Tegra124 Venice2"
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@ -15,6 +24,7 @@ config SYS_SOC
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default "tegra124"
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source "board/nvidia/jetson-tk1/Kconfig"
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source "board/nvidia/nyan-big/Kconfig"
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source "board/nvidia/venice2/Kconfig"
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endif
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@ -31,6 +31,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra30-tec-ng.dtb \
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tegra114-dalmore.dtb \
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tegra124-jetson-tk1.dtb \
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tegra124-nyan-big.dtb \
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tegra124-venice2.dtb
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dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ph1-sld3-ref.dtb \
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365
arch/arm/dts/tegra124-nyan-big.dts
Normal file
365
arch/arm/dts/tegra124-nyan-big.dts
Normal file
@ -0,0 +1,365 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "tegra124.dtsi"
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/ {
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model = "Acer Chromebook 13 CB5-311";
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compatible = "google,nyan-big", "nvidia,tegra124";
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aliases {
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console = &uarta;
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i2c0 = "/i2c@7000d000";
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i2c1 = "/i2c@7000c000";
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i2c2 = "/i2c@7000c400";
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i2c3 = "/i2c@7000c500";
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i2c4 = "/i2c@7000c700";
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i2c5 = "/i2c@7000d100";
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rtc0 = "/i2c@0,7000d000/pmic@40";
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rtc1 = "/rtc@0,7000e000";
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sdhci0 = "/sdhci@700b0600";
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sdhci1 = "/sdhci@700b0400";
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spi0 = "/spi@7000d400";
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spi1 = "/spi@7000da00";
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usb0 = "/usb@7d000000";
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usb1 = "/usb@7d008000";
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};
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memory {
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reg = <0x80000000 0x80000000>;
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};
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serial@70006000 {
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/* Debug connector on the bottom of the board near SD card. */
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status = "okay";
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};
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pwm@7000a000 {
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status = "okay";
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};
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i2c@7000c000 {
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status = "okay";
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clock-frequency = <100000>;
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acodec: audio-codec@10 {
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compatible = "maxim,max98090";
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reg = <0x10>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
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};
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temperature-sensor@4c {
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compatible = "ti,tmp451";
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reg = <0x4c>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
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#thermal-sensor-cells = <1>;
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};
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};
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i2c@7000c400 {
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status = "okay";
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clock-frequency = <100000>;
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};
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i2c@7000c500 {
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status = "okay";
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clock-frequency = <400000>;
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tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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};
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};
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hdmi_ddc: i2c@7000c700 {
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status = "okay";
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clock-frequency = <100000>;
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};
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <400000>;
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pmic: pmic@40 {
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compatible = "ams,as3722";
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reg = <0x40>;
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interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
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ams,system-power-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&as3722_default>;
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as3722_default: pinmux {
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gpio0 {
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pins = "gpio0";
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function = "gpio";
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bias-pull-down;
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};
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gpio1 {
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pins = "gpio1";
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function = "gpio";
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bias-pull-up;
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};
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gpio2_4_7 {
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pins = "gpio2", "gpio4", "gpio7";
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function = "gpio";
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bias-pull-up;
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};
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gpio3_6 {
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pins = "gpio3", "gpio6";
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bias-high-impedance;
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};
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gpio5 {
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pins = "gpio5";
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function = "clk32k-out";
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bias-pull-down;
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};
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};
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};
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};
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spi@7000d400 {
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status = "okay";
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cros_ec: cros-ec@0 {
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compatible = "google,cros-ec-spi";
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spi-max-frequency = <3000000>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
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reg = <0>;
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google,cros-ec-spi-msg-delay = <2000>;
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i2c-tunnel {
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compatible = "google,cros-ec-i2c-tunnel";
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#address-cells = <1>;
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#size-cells = <0>;
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google,remote-bus = <0>;
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charger: bq24735@9 {
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compatible = "ti,bq24735";
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reg = <0x9>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA_GPIO(J, 0)
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GPIO_ACTIVE_HIGH>;
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ti,ac-detect-gpios = <&gpio
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TEGRA_GPIO(J, 0)
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GPIO_ACTIVE_HIGH>;
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};
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battery: sbs-battery@b {
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compatible = "sbs,sbs-battery";
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reg = <0xb>;
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sbs,i2c-retry-count = <2>;
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sbs,poll-retry-count = <10>;
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power-supplies = <&charger>;
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};
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};
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};
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};
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spi@7000da00 {
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status = "okay";
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spi-max-frequency = <25000000>;
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flash@0 {
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compatible = "winbond,w25q32dw";
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reg = <0>;
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};
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};
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pmc@7000e400 {
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <0>;
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nvidia,cpu-pwr-good-time = <500>;
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nvidia,cpu-pwr-off-time = <300>;
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nvidia,core-pwr-good-time = <641 3845>;
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nvidia,core-pwr-off-time = <61036>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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};
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hda@70030000 {
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status = "okay";
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};
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sdhci@700b0000 { /* WiFi/BT on this bus */
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status = "okay";
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power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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};
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sdhci@700b0400 { /* SD Card on this bus */
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status = "okay";
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cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
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power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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no-1-8-v;
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};
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sdhci@700b0600 { /* eMMC on this bus */
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status = "okay";
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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};
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ahub@70300000 {
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i2s@70301100 {
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status = "okay";
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};
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};
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usb@7d000000 { /* Rear external USB port. */
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status = "okay";
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};
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usb-phy@7d000000 {
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status = "okay";
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};
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usb@7d004000 { /* Internal webcam. */
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status = "okay";
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};
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usb-phy@7d004000 {
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status = "okay";
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};
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usb@7d008000 { /* Left external USB port. */
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status = "okay";
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};
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usb-phy@7d008000 {
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status = "okay";
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
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pwms = <&pwm 1 1000000>;
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default-brightness-level = <224>;
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brightness-levels =
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< 0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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256>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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lid {
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label = "Lid";
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gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
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linux,input-type = <5>;
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linux,code = <KEY_RESERVED>;
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debounce-interval = <1>;
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gpio-key,wakeup;
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};
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power {
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label = "Power";
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gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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debounce-interval = <30>;
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gpio-key,wakeup;
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};
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};
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panel: panel {
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compatible = "auo,b133xtn01";
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backlight = <&backlight>;
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};
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sound {
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compatible = "nvidia,tegra-audio-max98090-nyan-big",
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"nvidia,tegra-audio-max98090";
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nvidia,model = "Acer Chromebook 13";
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nvidia,audio-routing =
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"Headphones", "HPR",
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"Headphones", "HPL",
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"Speakers", "SPKR",
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"Speakers", "SPKL",
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"Mic Jack", "MICBIAS",
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"DMICL", "Int Mic",
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"DMICR", "Int Mic",
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"IN34", "Mic Jack";
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nvidia,i2s-controller = <&tegra_i2s1>;
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nvidia,audio-codec = <&acodec>;
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clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
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<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
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<&tegra_car TEGRA124_CLK_EXTERN1>;
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clock-names = "pll_a", "pll_a_out0", "mclk";
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nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
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};
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};
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#include "cros-ec-keyboard.dtsi"
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24
board/nvidia/nyan-big/Kconfig
Normal file
24
board/nvidia/nyan-big/Kconfig
Normal file
@ -0,0 +1,24 @@
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if TARGET_NYAN_BIG
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config SYS_CPU
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string
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default "arm720t" if SPL_BUILD
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default "armv7" if !SPL_BUILD
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config SYS_BOARD
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string
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default "nyan-big"
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config SYS_VENDOR
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string
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default "nvidia"
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config SYS_SOC
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string
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default "tegra124"
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config SYS_CONFIG_NAME
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string
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default "nyan-big"
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endif
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6
board/nvidia/nyan-big/MAINTAINERS
Normal file
6
board/nvidia/nyan-big/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
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NORRIN BOARD
|
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M: Allen Martin <amartin@nvidia.com>
|
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S: Maintained
|
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F: board/nvidia/nyan-big/
|
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F: include/configs/nyan-big.h
|
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F: configs/nyan-big_defconfig
|
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9
board/nvidia/nyan-big/Makefile
Normal file
9
board/nvidia/nyan-big/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2014
|
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# NVIDIA Corporation <www.nvidia.com>
|
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#
|
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# SPDX-License-Identifier: GPL-2.0+
|
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#
|
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|
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obj-y += ../venice2/as3722_init.o
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obj-y += nyan-big.o
|
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27
board/nvidia/nyan-big/nyan-big.c
Normal file
27
board/nvidia/nyan-big/nyan-big.c
Normal file
@ -0,0 +1,27 @@
|
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/*
|
||||
* (C) Copyright 2014
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
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* SPDX-License-Identifier: GPL-2.0+
|
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*/
|
||||
|
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#include <common.h>
|
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#include <asm/arch/gpio.h>
|
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#include <asm/arch/pinmux.h>
|
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#include "pinmux-config-nyan-big.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
gpio_config_table(nyan_big_gpio_inits,
|
||||
ARRAY_SIZE(nyan_big_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(nyan_big_pingrps,
|
||||
ARRAY_SIZE(nyan_big_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(nyan_big_drvgrps,
|
||||
ARRAY_SIZE(nyan_big_drvgrps));
|
||||
}
|
||||
287
board/nvidia/nyan-big/pinmux-config-nyan-big.h
Normal file
287
board/nvidia/nyan-big/pinmux-config-nyan-big.h
Normal file
@ -0,0 +1,287 @@
|
||||
/*
|
||||
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
|
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#define _PINMUX_CONFIG_NYAN_BIG_H_
|
||||
|
||||
#define GPIO_INIT(_gpio, _init) \
|
||||
{ \
|
||||
.gpio = GPIO_P##_gpio, \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
|
||||
/* gpio, init_val */
|
||||
GPIO_INIT(A0, IN),
|
||||
GPIO_INIT(C7, IN),
|
||||
GPIO_INIT(G0, IN),
|
||||
GPIO_INIT(G1, IN),
|
||||
GPIO_INIT(G2, IN),
|
||||
GPIO_INIT(G3, IN),
|
||||
GPIO_INIT(H2, IN),
|
||||
GPIO_INIT(H4, IN),
|
||||
GPIO_INIT(H6, IN),
|
||||
GPIO_INIT(H7, OUT1),
|
||||
GPIO_INIT(I0, IN),
|
||||
GPIO_INIT(I1, IN),
|
||||
GPIO_INIT(I5, OUT1),
|
||||
GPIO_INIT(I6, IN),
|
||||
GPIO_INIT(I7, IN),
|
||||
GPIO_INIT(J0, IN),
|
||||
GPIO_INIT(J7, IN),
|
||||
GPIO_INIT(K1, OUT0),
|
||||
GPIO_INIT(K2, IN),
|
||||
GPIO_INIT(K4, OUT0),
|
||||
GPIO_INIT(K6, OUT0),
|
||||
GPIO_INIT(K7, IN),
|
||||
GPIO_INIT(N7, IN),
|
||||
GPIO_INIT(P2, OUT0),
|
||||
GPIO_INIT(Q0, IN),
|
||||
GPIO_INIT(Q2, IN),
|
||||
GPIO_INIT(Q3, IN),
|
||||
GPIO_INIT(Q6, IN),
|
||||
GPIO_INIT(Q7, IN),
|
||||
GPIO_INIT(R0, OUT0),
|
||||
GPIO_INIT(R1, IN),
|
||||
GPIO_INIT(R4, IN),
|
||||
GPIO_INIT(R7, IN),
|
||||
GPIO_INIT(S3, OUT0),
|
||||
GPIO_INIT(S4, OUT0),
|
||||
GPIO_INIT(S7, IN),
|
||||
GPIO_INIT(T1, IN),
|
||||
GPIO_INIT(U4, IN),
|
||||
GPIO_INIT(U5, IN),
|
||||
GPIO_INIT(U6, IN),
|
||||
GPIO_INIT(V0, IN),
|
||||
GPIO_INIT(W3, IN),
|
||||
GPIO_INIT(X1, IN),
|
||||
GPIO_INIT(X4, IN),
|
||||
GPIO_INIT(X7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config nyan_big_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_NYAN_BIG_H */
|
||||
@ -18,7 +18,7 @@
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#ifdef CONFIG_TARGET_JETSON_TK1
|
||||
#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#else
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
|
||||
|
||||
5
configs/nyan-big_defconfig
Normal file
5
configs/nyan-big_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TEGRA=y
|
||||
+S:CONFIG_TEGRA124=y
|
||||
+S:CONFIG_TARGET_NYAN_BIG=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
|
||||
79
include/configs/nyan-big.h
Normal file
79
include/configs/nyan-big.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* (C) Copyright 2014
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include "tegra124-common.h"
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra124 (Nyan-big) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA_ENABLE_UARTA
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_TEGRA
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* SD/MMC */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_TEGRA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
|
||||
#define CONFIG_TEGRA114_SPI_CTRLS 6
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
||||
|
||||
/* USB Host support */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_TEGRA
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* USB networking support */
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
|
||||
/* General networking support */
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
#include "tegra-common-usb-gadget.h"
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user