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avr32: add atngw100mkii board
This patch is derived from an older patch provided by atmel in its buildroot-avr32-v3.0.0.tar.bz2 Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
This commit is contained in:
Andreas Bießmann
parent
93691842e8
commit
a420dfe2b0
@ -1112,6 +1112,7 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
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Andreas Bießmann <andreas.devel@googlemail.com>
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grasshopper AT32AP7000
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atngw100mkii AT32AP7000
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Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
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40
board/atmel/atngw100mkii/Makefile
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40
board/atmel/atngw100mkii/Makefile
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@ -0,0 +1,40 @@
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#
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# Copyright (C) 2005-2006 Atmel Corporation
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#
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# See file CREDITS for list of people who contributed to this project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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include $(TOPDIR)/config.mk
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LIB := $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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156
board/atmel/atngw100mkii/atngw100mkii.c
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156
board/atmel/atngw100mkii/atngw100mkii.c
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@ -0,0 +1,156 @@
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/*
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* Copyright (C) 2010 Atmel Corporation
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*
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* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <spi.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/portmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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{
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/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
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.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
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.virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
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.nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
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.phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
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.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
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.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
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| MMU_VMR_CACHE_WRBACK,
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},
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};
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 10,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 6,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
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| HMATRIX_BIT(EBI_NAND_ENABLE));
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portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
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PORTMUX_DRIVE_HIGH);
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
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| PORTMUX_DRIVE_MIN);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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#if defined(CONFIG_MACB)
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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#if defined(CONFIG_ATMEL_SPI)
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portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
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#endif
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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unsigned long expected_size;
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unsigned long actual_size;
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void *sdram_base;
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sdram_base = uncached(EBI_SDRAM_BASE);
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expected_size = sdram_init(sdram_base, &sdram_config);
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actual_size = get_ram_size(sdram_base, expected_size);
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return actual_size;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bi)
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{
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macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
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macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
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return 0;
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}
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#endif
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
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}
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#endif /* CONFIG_ATMEL_SPI */
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@ -302,6 +302,7 @@ tec arm armv7:arm720t tec avionic
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paz00 arm armv7:arm720t paz00 compal tegra20
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trimslice arm armv7:arm720t trimslice compulab tegra20
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atngw100 avr32 at32ap - atmel at32ap700x
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atngw100mkii avr32 at32ap - atmel at32ap700x
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atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
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atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
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atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
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209
include/configs/atngw100mkii.h
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209
include/configs/atngw100mkii.h
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@ -0,0 +1,209 @@
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/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
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*
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* Configuration settings for the AVR32 Network Gateway
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AVR32
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_ATNGW100MKII
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/*
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* Timer clock frequency. We're using the CPU-internal COUNT register
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* for this, so this is equivalent to the CPU core clock frequency
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*/
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#define CONFIG_SYS_HZ 1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
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* and the PBA bus to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 20000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 7
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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/*
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* Set the CPU running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
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*/
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#define CONFIG_SYS_CLKDIV_CPU 0
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/*
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* Set the HSB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
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*/
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#define CONFIG_SYS_CLKDIV_HSB 1
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/*
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* Set the PBA running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBA 2
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/*
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* Set the PBB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
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#define CONFIG_SYS_NR_VM_REGIONS 3
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"root=mtd:main rootfstype=jffs2"
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#define CONFIG_BOOTCOMMAND \
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"fsload 0x10400000 /uImage; bootm"
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_AUTOBOOT
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* After booting the board for the first time, new ethernet addresses
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* should be generated and assigned to the environment variables
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* "ethaddr" and "eth1addr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_NET_MULTI
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/*
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* BOOTP/DHCP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_MII
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_XIMG
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
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#define CONFIG_ATMEL_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#endif /* __CONFIG_H */
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