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spi:fsl-quadspi support bank register read write
To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Peng Fan
Jagannadha Sutradharudu Teki
parent
653cda8f66
commit
a235878387
@ -33,6 +33,12 @@
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#define SEQID_PP 6
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#define SEQID_RDID 7
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#define SEQID_BE_4K 8
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#ifdef CONFIG_SPI_FLASH_BAR
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#define SEQID_BRRD 9
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#define SEQID_BRWR 10
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#define SEQID_RDEAR 11
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#define SEQID_WREAR 12
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#endif
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/* QSPI CMD */
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#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
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@ -44,6 +50,14 @@
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#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
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/* Used for Micron, winbond and Macronix flashes */
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#define QSPI_CMD_WREAR 0xc5 /* EAR register write */
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#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
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/* Used for Spansion flashes only. */
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#define QSPI_CMD_BRRD 0x16 /* Bank register read */
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#define QSPI_CMD_BRWR 0x17 /* Bank register write */
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/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
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#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
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#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
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@ -114,6 +128,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Fast Read */
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lut_base = SEQID_FAST_READ * 4;
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#ifdef CONFIG_SPI_FLASH_BAR
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#else
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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@ -124,6 +143,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
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OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
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INSTR1(LUT_ADDR));
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#endif
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qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
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INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
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INSTR1(LUT_READ));
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@ -141,6 +161,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Erase a sector */
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lut_base = SEQID_SE * 4;
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#ifdef CONFIG_SPI_FLASH_BAR
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#else
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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@ -149,6 +174,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#endif
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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@ -163,6 +189,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Page Program */
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lut_base = SEQID_PP * 4;
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#ifdef CONFIG_SPI_FLASH_BAR
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#else
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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@ -171,6 +202,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#endif
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#ifdef CONFIG_MX6SX
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/*
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* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
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@ -200,6 +232,32 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#ifdef CONFIG_SPI_FLASH_BAR
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/*
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* BRRD BRWR RDEAR WREAR are all supported, because it is hard to
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* dynamically check whether to set BRRD BRWR or RDEAR WREAR during
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* initialization.
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*/
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lut_base = SEQID_BRRD * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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lut_base = SEQID_BRWR * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
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lut_base = SEQID_RDEAR * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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lut_base = SEQID_WREAR * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
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#endif
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/* Lock the LUT */
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qspi_write32(®s->lutkey, LUT_KEY_VALUE);
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qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK);
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@ -293,6 +351,47 @@ int spi_claim_bus(struct spi_slave *slave)
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return 0;
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}
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#ifdef CONFIG_SPI_FLASH_BAR
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/* Bank register read/write, EAR register read/write */
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static void qspi_op_rdbank(struct fsl_qspi *qspi, u8 *rxbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 reg, mcr_reg, data, seqid;
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mcr_reg = qspi_read32(®s->mcr);
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qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
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qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
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qspi_write32(®s->sfar, qspi->amba_base);
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if (qspi->cur_seqid == QSPI_CMD_BRRD)
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seqid = SEQID_BRRD;
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else
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seqid = SEQID_RDEAR;
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qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
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/* Wait previous command complete */
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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while (1) {
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reg = qspi_read32(®s->rbsr);
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if (reg & QSPI_RBSR_RDBFL_MASK) {
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data = qspi_read32(®s->rbdr[0]);
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data = qspi_endian_xchg(data);
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memcpy(rxbuf, &data, len);
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qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
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QSPI_MCR_CLR_RXF_MASK);
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break;
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}
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}
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qspi_write32(®s->mcr, mcr_reg);
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}
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#endif
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static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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@ -371,10 +470,10 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
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qspi_write32(®s->mcr, mcr_reg);
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}
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static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
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static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 mcr_reg, data, reg, status_reg;
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u32 mcr_reg, data, reg, status_reg, seqid;
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int i, size, tx_size;
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u32 to_or_from = 0;
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@ -404,22 +503,39 @@ static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
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qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK);
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}
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/* Default is page programming */
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seqid = SEQID_PP;
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#ifdef CONFIG_SPI_FLASH_BAR
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if (qspi->cur_seqid == QSPI_CMD_BRWR)
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seqid = SEQID_BRWR;
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else if (qspi->cur_seqid == QSPI_CMD_WREAR)
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seqid = SEQID_WREAR;
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#endif
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to_or_from = qspi->sf_addr + qspi->amba_base;
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qspi_write32(®s->sfar, to_or_from);
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tx_size = (len > TX_BUFFER_SIZE) ?
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TX_BUFFER_SIZE : len;
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size = (tx_size + 3) / 4;
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size = tx_size / 4;
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for (i = 0; i < size; i++) {
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data = qspi_endian_xchg(*txbuf);
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memcpy(&data, txbuf, 4);
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data = qspi_endian_xchg(data);
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qspi_write32(®s->tbdr, data);
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txbuf++;
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txbuf += 4;
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}
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qspi_write32(®s->ipcr,
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(SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size);
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size = tx_size % 4;
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if (size) {
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data = 0;
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memcpy(&data, txbuf, size);
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data = qspi_endian_xchg(data);
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qspi_write32(®s->tbdr, data);
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}
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qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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@ -495,16 +611,18 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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{
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struct fsl_qspi *qspi = to_qspi_spi(slave);
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u32 bytes = DIV_ROUND_UP(bitlen, 8);
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static u32 pp_sfaddr;
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static u32 wr_sfaddr;
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u32 txbuf;
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if (dout) {
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memcpy(&txbuf, dout, 4);
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qspi->cur_seqid = *(u8 *)dout;
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if (flags & SPI_XFER_BEGIN) {
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qspi->cur_seqid = *(u8 *)dout;
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memcpy(&txbuf, dout, 4);
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}
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if (flags == SPI_XFER_END) {
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qspi->sf_addr = pp_sfaddr;
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qspi_op_pp(qspi, (u32 *)dout, bytes);
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qspi->sf_addr = wr_sfaddr;
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qspi_op_write(qspi, (u8 *)dout, bytes);
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return 0;
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}
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@ -514,9 +632,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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(qspi->cur_seqid == QSPI_CMD_BE_4K)) {
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qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
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qspi_op_erase(qspi);
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} else if (qspi->cur_seqid == QSPI_CMD_PP) {
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pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
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} else if (qspi->cur_seqid == QSPI_CMD_PP)
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wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
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#ifdef CONFIG_SPI_FLASH_BAR
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else if ((qspi->cur_seqid == QSPI_CMD_BRWR) ||
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(qspi->cur_seqid == QSPI_CMD_WREAR)) {
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wr_sfaddr = 0;
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}
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#endif
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}
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if (din) {
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@ -526,6 +649,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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qspi_op_rdid(qspi, din, bytes);
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else if (qspi->cur_seqid == QSPI_CMD_RDSR)
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qspi_op_rdsr(qspi, din);
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#ifdef CONFIG_SPI_FLASH_BAR
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else if ((qspi->cur_seqid == QSPI_CMD_BRRD) ||
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(qspi->cur_seqid == QSPI_CMD_RDEAR)) {
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qspi->sf_addr = 0;
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qspi_op_rdbank(qspi, din, bytes);
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}
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#endif
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}
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return 0;
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