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u-boot-imx-20210409

Browse Source 
-------------------
 
 - Secure Boot :
 	- HAB for MX8M / MX7ULP
 	- CAAM fixes
 - Fixes for imxrt1020
 - Fixes for USDHC driver
 - Fixes for Toradex (Colibri / Apalis)
 - Switch to DM for several boards
 	- mx23 olinuxo
 	- usbarmory
 	- marsboard / riotboard
 	- Gateworks GW Ventana
 - NXP upstream patches (LPDDR / CAAM / HAB)
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
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Merge tag 'u-boot-imx-20210409' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20210409
-------------------

- Secure Boot :
	- HAB for MX8M / MX7ULP
	- CAAM fixes
- Fixes for imxrt1020
- Fixes for USDHC driver
- Fixes for Toradex (Colibri / Apalis)
- Switch to DM for several boards
	- mx23 olinuxo
	- usbarmory
	- marsboard / riotboard
	- Gateworks GW Ventana
- NXP upstream patches (LPDDR / CAAM / HAB)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
This commit is contained in:
Tom Rini 2021-04-09 07:41:32 -04:00
commit a1e95e3805
192 changed files with 21399 additions and 2105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/Kconfig
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@ -839,6 +839,9 @@ config ARCH_IMX8
config ARCH_IMX8M config ARCH_IMX8M
bool "NXP i.MX8M platform" bool "NXP i.MX8M platform"
select ARM64 select ARM64
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select DM select DM
select SUPPORT_SPL select SUPPORT_SPL
imply CMD_DM imply CMD_DM
@ -875,6 +878,9 @@ config ARCH_MX31
config ARCH_MX7ULP config ARCH_MX7ULP
bool "NXP MX7ULP" bool "NXP MX7ULP"
select CPU_V7A select CPU_V7A
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS select ROM_UNIFIED_SECTIONS
imply MXC_GPIO imply MXC_GPIO
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD

39
arch/arm/dts/Makefile
View File

@ -653,6 +653,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
dtb-$(CONFIG_MX23) += \ dtb-$(CONFIG_MX23) += \
imx23-evk.dtb imx23-evk.dtb
dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \
imx23-olinuxino.dtb
dtb-$(CONFIG_MX28) += \ dtb-$(CONFIG_MX28) += \
imx28-xea.dtb imx28-xea.dtb
@ -662,7 +665,8 @@ dtb-$(CONFIG_MX51) += \
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
imx53-qsb.dtb \ imx53-qsb.dtb \
imx53-kp.dtb \ imx53-kp.dtb \
imx53-m53menlo.dtb imx53-m53menlo.dtb \
imx53-usbarmory.dtb
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \ dtb-y += \
@ -673,6 +677,20 @@ dtb-y += \
imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \
imx6dl-dhcom-pdk2.dtb \ imx6dl-dhcom-pdk2.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
imx6dl-gw54xx.dtb \
imx6dl-gw551x.dtb \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
imx6dl-gw5907.dtb \
imx6dl-gw5910.dtb \
imx6dl-gw5912.dtb \
imx6dl-gw5913.dtb \
imx6dl-hummingboard2.dtb \ imx6dl-hummingboard2.dtb \
imx6dl-hummingboard2-emmc-som-v15.dtb \ imx6dl-hummingboard2-emmc-som-v15.dtb \
imx6dl-hummingboard2-som-v15.dtb \ imx6dl-hummingboard2-som-v15.dtb \
@ -687,6 +705,8 @@ dtb-y += \
imx6dl-mamoj.dtb \ imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \ imx6dl-pico.dtb \
imx6dl-udoo.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \ imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \ imx6dl-sabresd.dtb \
imx6dl-wandboard-revd1.dtb \ imx6dl-wandboard-revd1.dtb \
@ -702,6 +722,20 @@ dtb-y += \
imx6q-cubox-i-som-v15.dtb \ imx6q-cubox-i-som-v15.dtb \
imx6q-dhcom-pdk2.dtb \ imx6q-dhcom-pdk2.dtb \
imx6q-display5.dtb \ imx6q-display5.dtb \
imx6q-gw51xx.dtb \
imx6q-gw52xx.dtb \
imx6q-gw53xx.dtb \
imx6q-gw54xx.dtb \
imx6q-gw551x.dtb \
imx6q-gw552x.dtb \
imx6q-gw553x.dtb \
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
imx6q-gw5907.dtb \
imx6q-gw5910.dtb \
imx6q-gw5912.dtb \
imx6q-gw5913.dtb \
imx6q-hummingboard2.dtb \ imx6q-hummingboard2.dtb \
imx6q-hummingboard2-emmc-som-v15.dtb \ imx6q-hummingboard2-emmc-som-v15.dtb \
imx6q-hummingboard2-som-v15.dtb \ imx6q-hummingboard2-som-v15.dtb \
@ -713,6 +747,7 @@ dtb-y += \
imx6q-icore-rqs.dtb \ imx6q-icore-rqs.dtb \
imx6q-kp.dtb \ imx6q-kp.dtb \
imx6q-logicpd.dtb \ imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mba6a.dtb \ imx6q-mba6a.dtb \
imx6q-mba6b.dtb \ imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\ imx6q-mccmon6.dtb\
@ -720,6 +755,7 @@ dtb-y += \
imx6q-novena.dtb \ imx6q-novena.dtb \
imx6q-pico.dtb \ imx6q-pico.dtb \
imx6q-phytec-mira-rdk-nand.dtb \ imx6q-phytec-mira-rdk-nand.dtb \
imx6q-udoo.dtb \
imx6q-sabreauto.dtb \ imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \ imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \ imx6q-sabresd.dtb \
@ -799,6 +835,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-verdin.dtb \ imx8mm-verdin.dtb \
phycore-imx8mm.dtb \ phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \ imx8mn-ddr4-evk.dtb \
imx8mn-evk.dtb \
imx8mq-evk.dtb \ imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \ imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \

5
arch/arm/dts/imx23-olinuxino-u-boot.dtsi Normal file
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@ -0,0 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
&ssp0 {
non-removable;
};

131
arch/arm/dts/imx23-olinuxino.dts Normal file
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@ -0,0 +1,131 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"
/ {
model = "i.MX23 Olinuxino Low Cost Board";
compatible = "olimex,imx23-olinuxino", "fsl,imx23";
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x04000000>;
};
apb@80000000 {
apbh@80000000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
bus-width = <4>;
broken-cd;
status = "okay";
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_ALE__GPIO_0_17
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
led_pin_gpio2_1: led_gpio2_1@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__GPIO_2_1
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
ssp1: spi@80034000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
};
};
apbx@80040000 {
lradc@80050000 {
status = "okay";
};
i2c: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_b>;
status = "okay";
};
duart: serial@80070000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
auart0: serial@8006c000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
dr_mode = "host";
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
gpio = <&gpio0 17 0>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio2_1>;
user {
label = "green";
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
};
};
};

225
arch/arm/dts/imx53-usbarmory.dts Normal file
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@ -0,0 +1,225 @@
/*
* USB armory MkI device tree file
* https://inversepath.com/usbarmory
*
* Copyright (C) 2015, Inverse Path
* Andrej Rosano <andrej@inversepath.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx53.dtsi"
/ {
model = "Inverse Path USB armory";
compatible = "inversepath,imx53-usbarmory", "fsl,imx53";
};
/ {
chosen {
stdout-path = &uart1;
};
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user {
label = "LED";
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
/*
* Not every i.MX53 P/N supports clock > 800MHz.
* As USB armory does not mount a specific P/N set a safe clock upper limit.
*/
&cpu0 {
operating-points = <
/* kHz */
166666 850000
400000 900000
800000 1050000
>;
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
status = "okay";
};
&iomuxc {
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_i2c1_pmic: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0x80
MX53_PAD_EIM_D28__I2C1_SDA 0x80
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4
>;
};
/*
* UART mode pin header configuration
* 3 - GPIO5[26], pull-down 100K
* 4 - GPIO5[27], pull-down 100K
* 5 - TX, pull-up 100K
* 6 - RX, pull-up 100K
* 7 - GPIO5[30], pull-down 100K
*/
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0
MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0
>;
};
};
&i2c1 {
pinctrl-0 = <&pinctrl_i2c1_pmic>;
status = "okay";
ltc3589: pmic@34 {
compatible = "lltc,ltc3589-2";
reg = <0x34>;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <591930>;
regulator-max-microvolt = <1224671>;
lltc,fb-voltage-divider = <100000 158000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <704123>;
regulator-max-microvolt = <1456803>;
lltc,fb-voltage-divider = <180000 191000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1341250>;
regulator-max-microvolt = <2775000>;
lltc,fb-voltage-divider = <270000 100000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
bb_out_reg: bb-out {
regulator-min-microvolt = <3387341>;
regulator-max-microvolt = <3387341>;
lltc,fb-voltage-divider = <511000 158000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <1306329>;
regulator-max-microvolt = <1306329>;
lltc,fb-voltage-divider = <100000 158000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <704123>;
regulator-max-microvolt = <1456806>;
lltc,fb-voltage-divider = <180000 191000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-boot-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3200000>;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

13
arch/arm/dts/imx6dl-gw51xx.dts Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw51xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
};

71
arch/arm/dts/imx6dl-gw52xx.dts Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw52xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi1>;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu1_csi1: ipu1_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
>;
};
};

71
arch/arm/dts/imx6dl-gw53xx.dts Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw53xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi1>;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu1_csi1: ipu1_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw54xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi1>;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu1_csi1: ipu1_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0
>;
};
};

55
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/*
* Copyright 2014 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw551x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X";
compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl";
};

14
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
};

55
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/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw553x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X";
compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl";
};

55
arch/arm/dts/imx6dl-gw560x.dts Normal file
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw560x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X";
compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl";
};

55
arch/arm/dts/imx6dl-gw5903.dts Normal file
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5903.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903";
compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl";
};

55
arch/arm/dts/imx6dl-gw5904.dts Normal file
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5904.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904";
compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl";
};

14
arch/arm/dts/imx6dl-gw5907.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5907.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
};

14
arch/arm/dts/imx6dl-gw5910.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5910.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
};

13
arch/arm/dts/imx6dl-gw5912.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5912.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
};

14
arch/arm/dts/imx6dl-gw5913.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw5913.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
};

8
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// SPDX-License-Identifier: GPL-2.0+
/ {
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc3;
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Iain Paton <ipaton0@gmail.com>
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "RIoTboard i.MX6S";
compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
chosen {
stdout-path = "serial1:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
led0: user1 {
label = "user1";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6-riotboard-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg_vbus: regulator-usbotgvbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&clks {
fsl,pmic-stby-poweroff;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-handle = <&rgmii_phy>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8035 PHY */
rgmii_phy: ethernet-phy@4 {
reg = <4>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
};
};
};
&gpio1 {
gpio-line-names =
"", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
"I2C3_SDA", "I2C4_SCL",
"I2C4_SDA", "", "", "", "", "", "", "",
"", "PWM3", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "USB_OTG_VBUS", "",
"UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
"UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
"GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
"CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
"CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
"CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
};
&gpio5 {
gpio-line-names =
"", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
"GPIO5_07",
"GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
"CSPI2_CS0", "CSPI2_CLK", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio7 {
gpio-line-names =
"SD3_CD", "SD3_WP", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
pmic: pf0100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <16 8>;
fsl,pmic-stby-poweroff;
regulators {
reg_vddcore: sw1ab { /* VDDARM_IN */
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c { /* VDDSOC_IN */
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 { /* VDDHIGH_IN */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_vtt: sw4 { /* MIPI conn */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_5v_600mA: swbst { /* not used */
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr { /* VREF_DDR */
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 { /* not used */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 { /* not used */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&clks 116>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
imx6-riotboard {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-udoo.dtsi"
/ {
model = "Udoo i.MX6 Dual-lite Board";
compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw51xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX";
compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw52xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu2_csi1>;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu2_csi1: ipu2_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
>;
};
};
&sata {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw53xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu2_csi1>;
};
&sata {
status = "okay";
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu2_csi1: ipu2_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw54xx.dtsi"
#include <dt-bindings/media/tda1997x.h>
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_codec>;
simple-audio-card,frame-master = <&sound_codec>;
sound_cpu: simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
sound_codec: simple-audio-card,codec {
sound-dai = <&hdmi_receiver>;
};
};
};
&i2c3 {
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
hdmi_receiver: hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&sw4_reg>;
DVDD-supply = <&sw4_reg>;
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same cycle
* which we map to VP[15:08]<->CSI_DATA[19:12]
*/
nxp,vidout-portcfg =
/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu2_csi1>;
};
&sata {
status = "okay";
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>;
};
pinctrl_ipu1_csi0: ipu1_csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ipu2_csi1: ipu2_csi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
>;
};
pinctrl_tda1997x: tda1997xgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
>;
};
};

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/*
* Copyright 2014 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw551x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW551X";
compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};

55
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/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw553x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW553X";
compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q";
};

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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw560x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW560X";
compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};

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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5903.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5903";
compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q";
};

59
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5904.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5904";
compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5907.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5910.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
};

13
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5912.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw5913.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
};

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// SPDX-License-Identifier: GPL-2.0+
/ {
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc3;
};
};

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/*
* Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Embest MarS Board i.MX6Dual";
compatible = "embest,imx6q-marsboard", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user1 {
label = "imx6:green:user1";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
user2 {
label = "imx6:green:user2";
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
m25p80@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-handle = <&rgmii_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8035 PHY */
rgmii_phy: ethernet-phy@4 {
reg = <4>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
/* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
/* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
/* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
/* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
/* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
/* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
/* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
/* RGMII_nRST */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0
/* AR8035 interrupt */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009
>;
};
};

4
arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi
View File

@ -40,3 +40,7 @@
&m25p80 { &m25p80 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&gpmi {
fsl,legacy-bch-geometry;
};

18
arch/arm/dts/imx6q-udoo.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-udoo.dtsi"
/ {
model = "Udoo i.MX6 Quad Board";
compatible = "udoo,imx6q-udoo", "fsl,imx6q";
};
&sata {
status = "okay";
};

638
arch/arm/dts/imx6qdl-gw51xx.dtsi Normal file
View File

@ -0,0 +1,638 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
reg_1p8v: sw2 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw4 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
reg_2p5v: ldo2 {
regulator-name = "vdd2p5";
regulator-min-microvolt = <2490375>;
regulator-max-microvolt = <2490375>;
lltc,fb-voltage-divider = <487000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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arch/arm/dts/imx6qdl-gw52xx.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_1p0v: regulator-1p0v {
compatible = "regulator-fixed";
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
reg_1p8v: sw2 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw4 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
reg_2p5v: ldo2 {
regulator-name = "vdd2p5";
regulator-min-microvolt = <2490375>;
regulator-max-microvolt = <2490375>;
lltc,fb-voltage-divider = <487000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_AUD_1P8: Audio codec */
reg_aud_1p8v: ldo3 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};
touchscreen: egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio7>;
interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
accel@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v; /* firmware will remove if board revision supports */
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>;
};
pinctrl_ecspi3: escpi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

772
arch/arm/dts/imx6qdl-gw53xx.dtsi Normal file
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@ -0,0 +1,772 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_1p0v: regulator-1p0v {
compatible = "regulator-fixed";
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
reg_1p8v: sw2 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw4 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
reg_2p5v: ldo2 {
regulator-name = "vdd2p5";
regulator-min-microvolt = <2490375>;
regulator-max-microvolt = <2490375>;
lltc,fb-voltage-divider = <487000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_AUD_1P8: Audio codec */
reg_aud_1p8v: ldo3 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};
touchscreen: egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
interrupts = <11 2>;
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
accel@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v; /* firmware will remove if board revision supports */
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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arch/arm/dts/imx6qdl-gw54xx.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_1p0v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound-analog {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
status = "okay";
ssi2 {
fsl,audmux-port = <1>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
IMX_AUDMUX_V2_PTCR_SYN)
IMX_AUDMUX_V2_PDCR_RXDSEL(4)
>;
};
aud5 {
fsl,audmux-port = <4>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
};
fan-controller@2c {
compatible = "gw,gsc-fan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2c>;
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&sw4_reg>;
VDDIO-supply = <&reg_3p3v>;
};
touchscreen: egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio7>;
interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
accel@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default", "state_dio";
pinctrl-0 = <&pinctrl_pwm4_backlight>;
pinctrl-1 = <&pinctrl_pwm4_dio>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v; /* firmware will remove if board revision supports */
status = "okay";
};
&wdog1 {
status = "disabled";
};
&wdog2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_ecspi2: escpi2grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4_backlight: pwm4grpbacklight {
fsl,pins = <
/* LVDS_PWM J6.5 */
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_pwm4_dio: pwm4grpdio {
fsl,pins = <
/* DIO3 J16.4 */
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
>;
};
};

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/*
* Copyright 2014 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/tda1997x.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_codec>;
simple-audio-card,frame-master = <&sound_codec>;
sound_cpu: simple-audio-card,cpu {
sound-dai = <&ssi1>;
};
sound_codec: simple-audio-card,codec {
sound-dai = <&hdmi_receiver>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
status = "okay";
ssi1 {
fsl,audmux-port = <0>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
IMX_AUDMUX_V2_PTCR_SYN)
IMX_AUDMUX_V2_PDCR_RXDSEL(4)
>;
};
aud5 {
fsl,audmux-port = <4>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8a";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0b";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw2 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_3P3 (1+R1/R2 = 1.281) */
reg_3p3: sw4 {
regulator-name = "vdd3p3";
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <3647000>;
lltc,fb-voltage-divider = <200000 56200>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
reg_1p8a: ldo2 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1816125>;
regulator-max-microvolt = <1816125>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8b: HDMI In analog */
reg_1p8b: ldo3 {
regulator-name = "vdd1p8b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
gpio_exp: pca9555@24 {
compatible = "nxp,pca9555";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi_receiver: hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3>;
AVDD-supply = <&reg_1p8b>;
DVDD-supply = <&reg_1p8a>;
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same cycle
* which we map to VP[15:08]<->CSI_DATA[19:12]
*/
nxp,vidout-portcfg =
/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&ssi1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0
MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1_csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_tda1997x: tda1997xgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
reg_1p0v: regulator-1p0v {
compatible = "regulator-fixed";
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
reg_1p8v: sw2 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw4 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
reg_2p5v: ldo2 {
regulator-name = "vdd2p5";
regulator-min-microvolt = <2490375>;
regulator-max-microvolt = <2490375>;
lltc,fb-voltage-divider = <487000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay"; };
&usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_5p0v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8a";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0b";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_an1";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
magn@1c {
compatible = "st,lsm9ds1-magn";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
st,drdy-int-pin = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio7>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
};
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw2 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_3P3 (1+R1/R2 = 1.281) */
reg_3p3v: sw4 {
regulator-name = "vdd3p3";
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <3647000>;
lltc,fb-voltage-divider = <200000 56200>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
reg_1p8a: ldo2 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1816125>;
regulator-max-microvolt = <1816125>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8b: microSD VDD_1P8 */
reg_1p8b: ldo3 {
regulator-name = "vdd1p8b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
adv7180: camera@20 {
compatible = "adi,adv7180";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7180>;
reg = <0x20>;
powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_adv7180: adv7180grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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arch/arm/dts/imx6qdl-gw560x.dtsi Normal file
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc2;
mmc1 = &usdhc3;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <100>;
};
backlight-keypad {
compatible = "gpio-backlight";
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
default-on;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "12P0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_1p4v: regulator-vddsoc {
compatible = "regulator-fixed";
regulator-name = "vdd_soc";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
channel@26 {
gw,mode = <1>;
reg = <0x26>;
label = "vdd_gps";
};
channel@29 {
gw,mode = <1>;
reg = <0x29>;
label = "vdd_an2";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
ds1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};
magn@1c {
compatible = "st,lsm9ds1-magn";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
};
tca8418: keypad@34 {
compatible = "ti,tca8418";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keypad>;
reg = <0x34>;
interrupt-parent = <&gpio5>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
MATRIX_KEY(0x00, 0x00, BTN_1)
MATRIX_KEY(0x01, 0x01, BTN_2)
MATRIX_KEY(0x01, 0x00, BTN_3)
MATRIX_KEY(0x02, 0x00, BTN_4)
MATRIX_KEY(0x00, 0x03, BTN_5)
MATRIX_KEY(0x00, 0x02, BTN_6)
MATRIX_KEY(0x01, 0x03, BTN_7)
MATRIX_KEY(0x01, 0x02, BTN_8)
MATRIX_KEY(0x02, 0x02, BTN_9)
>;
keypad,num-rows = <4>;
keypad,num-columns = <4>;
};
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x3c>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw2 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.931) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <796551>;
regulator-max-microvolt = <1544827>;
lltc,fb-voltage-divider = <243000 261000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <&reg_vdd_arm>;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
reg_1p8v: sw4 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
reg_1p0v: ldo2 {
regulator-name = "vdd1p0";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1050000>;
lltc,fb-voltage-divider = <78700 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_AUD_1P8: Audio codec */
reg_aud_1p8v: ldo3 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
st,drdy-int-pin = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts: touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio5>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};
};
&ldb {
fsl,dual-channel;
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
/* AUD4 */
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
/* AUD6 */
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
>;
};
pinctrl_ecspi3: escpi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
>;
};
pinctrl_flexcan: flexcangrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
>;
};
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

796
arch/arm/dts/imx6qdl-gw5903.dtsi Normal file
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@ -0,0 +1,796 @@
/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
chosen {
stdout-path = &uart2;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <100>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 30 0>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_12p0: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "12P0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-tlv320";
model = "imx-tlv320";
ssi-controller = <&ssi1>;
audio-codec = <&tlv320aic3105>;
/* routing of sink, source */
audio-routing =
/* TLV320 LINE1L pin <-> Mic Jack connector */
"LINE1L", "Mic Jack",
/* board Headphone Jack <-> HPOUT */
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Mic Jack", "Mic Bias";
mux-int-port = <1>;
mux-ext-port = <6>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
dts1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
reg_1p8v: sw1 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw2 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <&reg_vdd_arm>;
};
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw4 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <&reg_vdd_soc>;
};
/* VDD_1P0 (1+R1/R2 = 1.38): */
reg_1p0v: ldo2 {
regulator-name = "vdd1p0";
regulator-min-microvolt = <1002777>;
regulator-max-microvolt = <1002777>;
lltc,fb-voltage-divider = <100000 261000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
tlv320aic3105: codec@18 {
compatible = "ti,tlv320aic3x";
reg = <0x18>;
reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_CKO>;
ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
/* Regulators */
DRVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&reg_1p8v>;
};
accelerometer@1d {
compatible = "fsl,mma8451";
reg = <0x1d>;
interrupt-parent = <&gpio7>;
interrupts = <11 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "INT2";
};
/* headphone detect */
ts3a227e@3b {
compatible = "ti,ts3a227e";
reg = <0x3b>;
interrupt-parent = <&gpio5>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
ti,micbias = <4>; /* 2.5V micbias */
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: g101evn010 {
clock-frequency = <68930000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_3p3v>;
non-removable;
bus-width = <4>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
max-frequency = <100000000>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
non-removable;
vmmc-supply = <&reg_3p3v>;
keep-power-in-suspend;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
/* I2C3 */
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
/* Headphone Detect */
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */
/* Codec */
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */
/* Touch Controller */
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */
/* Stow Sensor */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */
MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

814
arch/arm/dts/imx6qdl-gw5904.dtsi Normal file
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/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
reg_1p0v: regulator-1p0v {
compatible = "regulator-fixed";
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "marvell,mv88e6085";
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec>;
};
};
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
dts1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
magn@1c {
compatible = "st,lsm9ds1-magn";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
};
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_SOC (1+R1/R2 = 1.635) */
reg_vdd_soc: sw1 {
regulator-name = "vddsoc";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
reg_1p8v: sw2 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.635) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <674400>;
regulator-max-microvolt = <1308000>;
lltc,fb-voltage-divider = <127000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw4 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
reg_2p5v: ldo2 {
regulator-name = "vdd2p5";
regulator-min-microvolt = <2490375>;
regulator-max-microvolt = <2490375>;
lltc,fb-voltage-divider = <487000 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
st,drdy-int-pin = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts: touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
uart-has-rtscts;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
non-removable;
vmmc-supply = <&reg_3p3v>;
keep-power-in-suspend;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_an1";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
adc@48 {
compatible = "ti,ads1015";
reg = <0x48>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
ti,gain = <0>;
ti,datarate = <5>;
};
channel@5 {
reg = <5>;
ti,gain = <0>;
ti,datarate = <5>;
};
channel@6 {
reg = <6>;
ti,gain = <0>;
ti,datarate = <5>;
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
};
chosen {
stdout-path = &uart2;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_wl: regulator-wl {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl>;
compatible = "regulator-fixed";
regulator-name = "wl";
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <800000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <22100 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_3p0";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_arm";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_soc";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_1p5";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_1p8";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_1p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_an1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
accel@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio7>;
interrupts = <13 0>;
interrupt-names = "INT1";
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
/* off-board RS232 */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* serial console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* cc1352 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
/* Sterling-LWB Bluetooth */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
};
};
/* GPS */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_5p0v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbh1 {
status = "okay";
};
/* Sterling-LWB SDIO WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_wl>;
non-removable;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_accel: accelmuxgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
>;
};
pinctrl_bten: btengrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
>;
};
pinctrl_ecspi3: escpi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_wl: regwlgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

609
arch/arm/dts/imx6qdl-gw5912.dtsi Normal file
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@ -0,0 +1,609 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_vbus: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
gw,mode = <0>;
reg = <0x00>;
label = "temp";
};
channel@2 {
gw,mode = <1>;
reg = <0x02>;
label = "vdd_vin";
};
channel@5 {
gw,mode = <1>;
reg = <0x05>;
label = "vdd_3p3";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@b {
gw,mode = <1>;
reg = <0x0b>;
label = "vdd_5p0";
};
channel@e {
gw,mode = <1>;
reg = <0xe>;
label = "vdd_arm";
};
channel@11 {
gw,mode = <1>;
reg = <0x11>;
label = "vdd_soc";
};
channel@14 {
gw,mode = <1>;
reg = <0x14>;
label = "vdd_3p0";
};
channel@17 {
gw,mode = <1>;
reg = <0x17>;
label = "vdd_1p5";
};
channel@1d {
gw,mode = <1>;
reg = <0x1d>;
label = "vdd_1p8";
};
channel@20 {
gw,mode = <1>;
reg = <0x20>;
label = "vdd_1p0";
};
channel@23 {
gw,mode = <1>;
reg = <0x23>;
label = "vdd_2p5";
};
};
fan-controller@a {
compatible = "gw,gsc-fan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0a>;
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
accel@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio7>;
interrupts = <13 0>;
interrupt-names = "INT1";
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v; /* firmware will remove if board revision supports */
status = "okay";
};
&wdog1 {
status = "disabled";
};
&wdog2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_accel: accelmuxgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
>;
};
pinctrl_ecspi2: escpi2grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
>;
};
};

501
arch/arm/dts/imx6qdl-gw5913.dtsi Normal file
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@ -0,0 +1,501 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key-erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <800000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <22100 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_arm";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_soc";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_1p5";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_1p0";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_3p0";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_an1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbh1 {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

7
arch/arm/dts/imx6qdl-udoo-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
aliases {
mmc0 = &usdhc3;
};
};

324
arch/arm/dts/imx6qdl-udoo.dtsi Normal file
View File

@ -0,0 +1,324 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
/ {
aliases {
backlight = &backlight;
panelchan = &panelchan;
panel7 = &panel7;
touchscreenp7 = &touchscreenp7;
};
chosen {
stdout-path = &uart2;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpio1 4 0>;
default-on;
status = "disabled";
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio2 4 0>;
pinctrl-0 = <&pinctrl_power_off>;
pinctrl-names = "default";
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
panel7: panel7 {
/*
* in reality it is a -20t (parallel) model,
* but with LVDS bridge chip attached,
* so it is equivalent to -19t model in drive
* characteristics
*/
compatible = "urt,umsh-8596md-19t";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
power-supply = <&reg_panel>;
backlight = <&backlight>;
status = "disabled";
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_h1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
gpio = <&gpio7 12 0>;
};
reg_panel: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd_panel";
enable-active-high;
gpio = <&gpio1 2 0>;
};
};
sound {
compatible = "fsl,imx6q-udoo-ac97",
"fsl,imx-audio-ac97";
model = "fsl,imx6q-udoo-ac97";
audio-cpu = <&ssi1>;
audio-routing =
"RX", "Mic Jack",
"Headphone Jack", "TX";
mux-int-port = <1>;
mux-ext-port = <6>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreenp7: touchscreenp7@55 {
compatible = "sitronix,st1232";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreenp7>;
reg = <0x55>;
interrupt-parent = <&gpio1>;
interrupts = <13 8>;
gpios = <&gpio1 15 0>;
status = "disabled";
};
};
&iomuxc {
imx6q-udoo {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70
>;
};
pinctrl_power_off: poweroffgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30
>;
};
pinctrl_touchscreenp7: touchscreenp7grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh: usbhgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
>;
};
pinctrl_usbotg: usbotg {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_ac97_running: ac97running {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
pinctrl_ac97_warm_reset: ac97warmreset {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
pinctrl_ac97_reset: ac97reset {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
};
};
&ldb {
status = "okay";
panelchan: lvds-channel@0 {
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks IMX6QDL_CLK_CKO>;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
status = "okay";
};
&audmux {
status = "okay";
};
&ssi1 {
cell-index = <0>;
fsl,mode = "ac97-slave";
pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset";
pinctrl-0 = <&pinctrl_ac97_running>;
pinctrl-1 = <&pinctrl_ac97_reset>;
pinctrl-2 = <&pinctrl_ac97_warm_reset>;
ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>;
status = "okay";
};

118
arch/arm/dts/imx8mm-evk-u-boot.dtsi
View File

@ -4,11 +4,22 @@
*/ */
/ { / {
binman: binman {
multiple-images;
};
wdt-reboot { wdt-reboot {
compatible = "wdt-reboot"; compatible = "wdt-reboot";
wdt = <&wdog1>; wdt = <&wdog1>;
u-boot,dm-spl; u-boot,dm-spl;
}; };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
}; };
&{/soc@0} { &{/soc@0} {
@ -102,6 +113,7 @@
u-boot,dm-spl; u-boot,dm-spl;
sd-uhs-sdr104; sd-uhs-sdr104;
sd-uhs-ddr50; sd-uhs-ddr50;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
}; };
&usdhc3 { &usdhc3 {
@ -114,11 +126,11 @@
u-boot,dm-spl; u-boot,dm-spl;
}; };
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
u-boot,dm-spl; u-boot,dm-spl;
}; };
@ -137,3 +149,105 @@
&wdog1 { &wdog1 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
};
};
flash {
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x920000>;
entry = <0x920000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
};

127
arch/arm/dts/imx8mm-evk.dtsi
View File

@ -126,115 +126,120 @@
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
status = "okay"; status = "okay";
pmic@4b { pmic: pca9450@25 {
compatible = "rohm,bd71847"; reg = <0x25>;
reg = <0x4b>; compatible = "nxp,pca9450a";
pinctrl-names = "default"; /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>; pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>; gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators { regulators {
buck1_reg: BUCK1 { #address-cells = <1>;
regulator-name = "buck1"; #size-cells = <0>;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>; pca9450,pmic-buck2-uses-i2c-dvs;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-ramp-delay = <1250>; regulator-ramp-delay = <3125>;
}; };
buck2_reg: BUCK2 { buck2_reg: regulator@1 {
regulator-name = "buck2"; reg = <1>;
regulator-min-microvolt = <700000>; regulator-compatible = "buck2";
regulator-max-microvolt = <1300000>; regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-ramp-delay = <1250>; regulator-ramp-delay = <3125>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
}; };
buck3_reg: BUCK3 { buck3_reg: regulator@2 {
// BUCK5 in datasheet reg = <2>;
regulator-name = "buck3"; regulator-compatible = "buck3";
regulator-min-microvolt = <700000>; regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <2187500>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
buck4_reg: BUCK4 { buck4_reg: regulator@3 {
// BUCK6 in datasheet reg = <3>;
regulator-name = "buck4"; regulator-compatible = "buck4";
regulator-min-microvolt = <3000000>; regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3400000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
buck5_reg: BUCK5 { buck5_reg: regulator@4 {
// BUCK7 in datasheet reg = <4>;
regulator-name = "buck5"; regulator-compatible = "buck5";
regulator-min-microvolt = <1605000>; regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1995000>; regulator-max-microvolt = <3400000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
buck6_reg: BUCK6 { buck6_reg: regulator@5 {
// BUCK8 in datasheet reg = <5>;
regulator-name = "buck6"; regulator-compatible = "buck6";
regulator-min-microvolt = <800000>; regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>; regulator-max-microvolt = <3400000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo1_reg: LDO1 { ldo1_reg: regulator@6 {
regulator-name = "ldo1"; reg = <6>;
regulator-compatible = "ldo1";
regulator-min-microvolt = <1600000>; regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo2_reg: LDO2 { ldo2_reg: regulator@7 {
regulator-name = "ldo2"; reg = <7>;
regulator-compatible = "ldo2";
regulator-min-microvolt = <800000>; regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>; regulator-max-microvolt = <1150000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo3_reg: LDO3 { ldo3_reg: regulator@8 {
regulator-name = "ldo3"; reg = <8>;
regulator-min-microvolt = <1800000>; regulator-compatible = "ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo4_reg: LDO4 { ldo4_reg: regulator@9 {
regulator-name = "ldo4"; reg = <9>;
regulator-min-microvolt = <900000>; regulator-compatible = "ldo4";
regulator-max-microvolt = <1800000>; regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo6_reg: LDO6 { ldo5_reg: regulator@10 {
regulator-name = "ldo6"; reg = <10>;
regulator-min-microvolt = <900000>; regulator-compatible = "ldo5";
regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-boot-on; regulator-max-microvolt = <3300000>;
regulator-always-on;
}; };
}; };
}; };
}; };

71
arch/arm/dts/imx8mn-beacon-baseboard.dtsi
View File

@ -34,6 +34,15 @@
}; };
}; };
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 { reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vsd_3v3"; regulator-name = "vsd_3v3";
@ -53,6 +62,20 @@
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
};
}; };
&ecspi2 { &ecspi2 {
@ -98,6 +121,44 @@
interrupt-parent = <&gpio4>; interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>; interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
}; };
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "xclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
}; };
&snvs_pwrkey { &snvs_pwrkey {
@ -177,6 +238,16 @@
>; >;
}; };
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

63
arch/arm/dts/imx8mn-beacon-som.dtsi
View File

@ -4,6 +4,12 @@
*/ */
/ { / {
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
spi0 = &flexspi;
};
usdhc1_pwrseq: usdhc1_pwrseq { usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
pinctrl-names = "default"; pinctrl-names = "default";
@ -36,11 +42,39 @@
cpu-supply = <&buck2_reg>; cpu-supply = <&buck2_reg>;
}; };
/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
&a53_opp_table {
opp-1200000000 {
opp-microvolt = <950000>;
};
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-800M {
opp-hz = /bits/ 64 <800000000>;
};
};
};
&fec1 { &fec1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>; pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
phy-handle = <&ethphy0>; phy-handle = <&ethphy0>;
phy-supply = <&buck6_reg>;
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
fsl,magic-packet; fsl,magic-packet;
status = "okay"; status = "okay";
@ -56,6 +90,22 @@
}; };
}; };
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 { &i2c1 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -184,7 +234,7 @@
reg = <0x50>; reg = <0x50>;
}; };
rtc@51 { rtc: rtc@51 {
compatible = "nxp,pcf85263"; compatible = "nxp,pcf85263";
reg = <0x51>; reg = <0x51>;
}; };
@ -285,6 +335,17 @@
>; >;
}; };
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_pmic: pmicirqgrp { pinctrl_pmic: pmicirqgrp {
fsl,pins = < fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141

115
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
View File

@ -4,11 +4,21 @@
*/ */
/ { / {
binman: binman {
multiple-images;
};
wdt-reboot { wdt-reboot {
compatible = "wdt-reboot"; compatible = "wdt-reboot";
wdt = <&wdog1>; wdt = <&wdog1>;
u-boot,dm-spl; u-boot,dm-spl;
}; };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
}; };
&{/soc@0} { &{/soc@0} {
@ -19,6 +29,9 @@
&clk { &clk {
u-boot,dm-spl; u-boot,dm-spl;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
}; };
&osc_24m { &osc_24m {
@ -110,3 +123,105 @@
&wdog1 { &wdog1 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "ddr4_imem_1d_201810.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "ddr4_dmem_1d_201810.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "ddr4_imem_2d_201810.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "ddr4_dmem_2d_201810.bin";
size = <0x4000>;
};
};
flash {
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x960000>;
entry = <0x960000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
};

128
arch/arm/dts/imx8mn-evk-u-boot.dtsi Normal file
View File

@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include "imx8mn-ddr4-evk-u-boot.dtsi"
&i2c1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
};
};
flash {
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x960000>;
entry = <0x960000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
};

128
arch/arm/dts/imx8mn-evk.dts Normal file
View File

@ -0,0 +1,128 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mn.dtsi"
#include "imx8mn-evk.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "NXP i.MX8MNano EVK board";
compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
pmic: pca9450@25 {
compatible = "nxp,pca9450b";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1{
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

46
arch/arm/dts/imx8mn.dtsi
View File

@ -241,10 +241,12 @@
}; };
soc@0 { soc@0 {
compatible = "simple-bus"; compatible = "fsl,imx8mn-soc", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>; ranges = <0x0 0x0 0x0 0x3e000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 { aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus"; compatible = "fsl,aips-bus", "simple-bus";
@ -253,7 +255,7 @@
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
spba: bus@30000000 { spba: spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus"; compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -531,9 +533,17 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
imx8mn_uid: unique-id@410 {
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 { cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>; reg = <0x10 4>;
}; };
fec_mac_address: mac-address@90 {
reg = <0x90 6>;
};
}; };
anatop: anatop@30360000 { anatop: anatop@30360000 {
@ -581,7 +591,9 @@
<&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_NOC>,
<&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_AUDIO_AHB>,
<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MN_SYS_PLL3>; <&clk IMX8MN_SYS_PLL3>,
<&clk IMX8MN_AUDIO_PLL1>,
<&clk IMX8MN_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_ARM_PLL_OUT>, <&clk IMX8MN_ARM_PLL_OUT>,
<&clk IMX8MN_SYS_PLL3_OUT>, <&clk IMX8MN_SYS_PLL3_OUT>,
@ -589,7 +601,9 @@
assigned-clock-rates = <0>, <0>, <0>, assigned-clock-rates = <0>, <0>, <0>,
<400000000>, <400000000>,
<400000000>, <400000000>,
<600000000>; <600000000>,
<393216000>,
<361267200>;
}; };
src: reset-controller@30390000 { src: reset-controller@30390000 {
@ -875,6 +889,19 @@
status = "disabled"; status = "disabled";
}; };
flexspi: spi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8mm-fspi";
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
<&clk IMX8MN_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
status = "disabled";
};
sdma1: dma-controller@30bd0000 { sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>; reg = <0x30bd0000 0x10000>;
@ -903,13 +930,18 @@
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
<&clk IMX8MN_CLK_ENET_TIMER>, <&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>, <&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_TIMER>; <&clk IMX8MN_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>, <&clk IMX8MN_SYS_PLL2_100M>,
<&clk IMX8MN_SYS_PLL2_125M>; <&clk IMX8MN_SYS_PLL2_125M>,
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; <&clk IMX8MN_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>; fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>; fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled"; status = "disabled";
}; };

112
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View File

@ -4,11 +4,21 @@
*/ */
/ { / {
binman: binman {
multiple-images;
};
wdt-reboot { wdt-reboot {
compatible = "wdt-reboot"; compatible = "wdt-reboot";
wdt = <&wdog1>; wdt = <&wdog1>;
u-boot,dm-spl; u-boot,dm-spl;
}; };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
}; };
&{/soc@0} { &{/soc@0} {
@ -145,3 +155,105 @@
phy-reset-duration = <15>; phy-reset-duration = <15>;
phy-reset-post-delay = <100>; phy-reset-post-delay = <100>;
}; };
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem_202006.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem_202006.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
size = <0x4000>;
};
};
flash {
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x970000>;
entry = <0x970000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
};

13
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -40,10 +40,13 @@
#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
#define MXC_CPU_IMX8MP 0x182/* dummy ID */ #define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */
#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ #define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ #define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ #define MXC_CPU_IMX8MP 0x185/* dummy ID */
#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
@ -59,9 +62,11 @@
#define CHIP_REV_1_0 0x10 #define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11 #define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12 #define CHIP_REV_1_2 0x12
#define CHIP_REV_1_3 0x13
#define CHIP_REV_1_5 0x15 #define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20 #define CHIP_REV_2_0 0x20
#define CHIP_REV_2_1 0x21 #define CHIP_REV_2_1 0x21
#define CHIP_REV_2_2 0x22
#define CHIP_REV_2_5 0x25 #define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30 #define CHIP_REV_3_0 0x30

11
arch/arm/include/asm/arch-imx8/image.h
View File

@ -53,4 +53,15 @@ struct signature_block_hdr {
u16 signature_offset; u16 signature_offset;
u32 reserved; u32 reserved;
} __packed; } __packed;
struct generate_key_blob_hdr {
u8 version;
u8 length_lsb;
u8 length_msb;
u8 tag;
u8 flags;
u8 size;
u8 algorithm;
u8 mode;
} __packed;
#endif #endif

1
arch/arm/include/asm/arch-imx8m/clock.h
View File

@ -275,3 +275,4 @@ void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int set_clk_enet(enum enet_freq type); int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type); int set_clk_eqos(enum enet_freq type);
void hab_caam_clock_enable(unsigned char enable);

21
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -65,6 +65,16 @@
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
#define FEC_QUIRK_ENET_MAC #define FEC_QUIRK_ENET_MAC
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
#define CONFIG_SYS_FSL_SEC_OFFSET (0)
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !defined(__ASSEMBLY__) #if !defined(__ASSEMBLY__)
#include <asm/types.h> #include <asm/types.h>
#include <linux/bitops.h> #include <linux/bitops.h>
@ -120,6 +130,16 @@ struct ocotp_regs {
} bank[0]; } bank[0];
}; };
#ifdef CONFIG_IMX8MP
struct fuse_bank0_regs {
u32 lock;
u32 rsvd0[7];
u32 uid_low;
u32 rsvd1[3];
u32 uid_high;
u32 rsvd2[3];
};
#else
struct fuse_bank0_regs { struct fuse_bank0_regs {
u32 lock; u32 lock;
u32 rsvd0[3]; u32 rsvd0[3];
@ -128,6 +148,7 @@ struct fuse_bank0_regs {
u32 uid_high; u32 uid_high;
u32 rsvd2[7]; u32 rsvd2[7];
}; };
#endif
struct fuse_bank1_regs { struct fuse_bank1_regs {
u32 tester3; u32 tester3;

8
arch/arm/include/asm/arch-mx6/mx6ull_pins.h
View File

@ -326,7 +326,7 @@ enum {
MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 6, 0),
MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
@ -363,7 +363,7 @@ enum {
MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 5, 0),
MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
@ -373,7 +373,7 @@ enum {
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 6, 0),
MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
@ -1012,7 +1012,7 @@ enum {
MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 7, 0),
MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),

12
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View File

@ -16,6 +16,8 @@
#define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_SIZE (SZ_32K)
#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE
#define OCRAM_0_BASE (0x2F000000) #define OCRAM_0_BASE (0x2F000000)
#define OCRAM_0_SIZE (SZ_128K) #define OCRAM_0_SIZE (SZ_128K)
#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
@ -224,6 +226,16 @@
#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))

37
arch/arm/include/asm/mach-imx/hab.h
View File

@ -18,8 +18,6 @@
*/ */
#define IVT_HEADER_MAGIC 0xD1 #define IVT_HEADER_MAGIC 0xD1
#define IVT_TOTAL_LENGTH 0x20 #define IVT_TOTAL_LENGTH 0x20
#define IVT_HEADER_V1 0x40
#define IVT_HEADER_V2 0x41
struct __packed ivt_header { struct __packed ivt_header {
uint8_t magic; uint8_t magic;
@ -44,6 +42,15 @@ struct __packed hab_hdr {
u8 par; /* Parameters field */ u8 par; /* Parameters field */
}; };
/* Default event structure */
struct __packed evt_def {
struct hab_hdr hdr; /* Header */
uint32_t sts; /* Status */
uint32_t ctx; /* Default context */
uint8_t *data; /* Default data location */
size_t bytes; /* Size of default data */
};
/* -------- start of HAB API updates ------------*/ /* -------- start of HAB API updates ------------*/
/* The following are taken from HAB4 SIS */ /* The following are taken from HAB4 SIS */
@ -165,6 +172,22 @@ typedef void hapi_clock_init_t(void);
#define HAB_ENG_RTL 0x77 /* RTL simulation engine */ #define HAB_ENG_RTL 0x77 /* RTL simulation engine */
#define HAB_ENG_SW 0xff /* Software engine */ #define HAB_ENG_SW 0xff /* Software engine */
#ifdef CONFIG_ARM64
#ifdef CONFIG_IMX8MQ
#define HAB_RVT_BASE 0x00000880
#else
#define HAB_RVT_BASE 0x00000900
#endif
#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08))
#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10))
#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18))
#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20))
#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40))
#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48))
#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50))
#else
#ifdef CONFIG_ROM_UNIFIED_SECTIONS #ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define HAB_RVT_BASE 0x00000100 #define HAB_RVT_BASE 0x00000100
#else #else
@ -172,7 +195,7 @@ typedef void hapi_clock_init_t(void);
#define HAB_RVT_BASE_OLD 0x00000094 #define HAB_RVT_BASE_OLD 0x00000094
#define HAB_RVT_BASE ((is_mx6dqp()) ? \ #define HAB_RVT_BASE ((is_mx6dqp()) ? \
HAB_RVT_BASE_NEW : \ HAB_RVT_BASE_NEW : \
(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_3)) ? \
HAB_RVT_BASE_NEW : \ HAB_RVT_BASE_NEW : \
(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD) HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD)
@ -186,6 +209,8 @@ typedef void hapi_clock_init_t(void);
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) #define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
#define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28)) #define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28))
#endif /*CONFIG_ARM64*/
#define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
@ -199,6 +224,12 @@ typedef void hapi_clock_init_t(void);
#define IVT_SIZE 0x20 #define IVT_SIZE 0x20
#define CSF_PAD_SIZE 0x2000 #define CSF_PAD_SIZE 0x2000
#define HAB_TAG_EVT 0xDB
#define HAB_TAG_EVT_DEF 0x0C
#define HAB_MAJ_VER 0x40
#define HAB_MAJ_MASK 0xF0
/* ----------- end of HAB API updates ------------*/ /* ----------- end of HAB API updates ------------*/
int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,

6
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -60,12 +60,16 @@ struct bd_info;
#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))

44
arch/arm/mach-imx/Kconfig
View File

@ -43,9 +43,9 @@ config USE_IMXIMG_PLUGIN
config IMX_HAB config IMX_HAB
bool "Support i.MX HAB features" bool "Support i.MX HAB features"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M
select FSL_CAAM if HAS_CAAM select FSL_CAAM if HAS_CAAM
imply CMD_DEKBLOB imply CMD_DEKBLOB if HAS_CAAM
help help
This option enables the support for secure boot (HAB). This option enables the support for secure boot (HAB).
See doc/imx/habv4/* for more details. See doc/imx/habv4/* for more details.
@ -75,12 +75,43 @@ config CMD_BMODE
config CMD_DEKBLOB config CMD_DEKBLOB
bool "Support the 'dek_blob' command" bool "Support the 'dek_blob' command"
select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP
select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M
select IMX_SECO_DEK_ENCAP if ARCH_IMX8
help help
This enables the 'dek_blob' command which is used with the This enables the 'dek_blob' command which is used with the
Freescale secure boot mechanism. This command encapsulates and Freescale secure boot mechanism. This command encapsulates and
creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for
more information. more information.
config IMX_CAAM_DEK_ENCAP
bool "Support the DEK blob encapsulation with CAAM U-Boot driver"
help
This enables the DEK blob encapsulation with the U-Boot CAAM driver.
This option is only available on imx6, imx7 and imx7ulp.
config IMX_OPTEE_DEK_ENCAP
select TEE
select OPTEE
bool "Support the DEK blob encapsulation with OP-TEE"
help
This enabled the DEK blob encapsulation with OP-TEE. The communication
with OP-TEE is done through a SMC call and OP-TEE shared memory. This
option is available on imx8mm.
config IMX_SECO_DEK_ENCAP
bool "Support the DEK blob encapsulation with SECO"
help
This enabled the DEK blob encapsulation with the SECO API. This option
is only available on imx8.
config CMD_PRIBLOB
bool "Support the set_priblob_bitfield command"
depends on HAS_CAAM && IMX_HAB
help
This option enables the priblob command which can be used
to set the priblob setting to 0x3.
config CMD_HDMIDETECT config CMD_HDMIDETECT
bool "Support the 'hdmidet' command" bool "Support the 'hdmidet' command"
help help
@ -99,6 +130,15 @@ config CMD_NANDBCB
This is similar to kobs-ng, which is used in Linux as separate This is similar to kobs-ng, which is used in Linux as separate
rootfs package. rootfs package.
config FSL_MFGPROT
bool "Support the 'mfgprot' command"
depends on IMX_HAB && ARCH_MX7
help
This option enables the manufacturing protection command
which can be used has a protection feature for Manufacturing
process. With this tool is possible to authenticate the
chip to the OEM's server.
config NXP_BOARD_REVISION config NXP_BOARD_REVISION
bool "Read NXP board revision from fuses" bool "Read NXP board revision from fuses"
depends on ARCH_MX6 || ARCH_MX7 depends on ARCH_MX6 || ARCH_MX7

3
arch/arm/mach-imx/Makefile
View File

@ -16,6 +16,7 @@ endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o obj-y += cpu.o
endif endif
@ -29,12 +30,14 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif endif
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt)) ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
obj-y += misc.o obj-y += misc.o
obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += spl.o
endif endif
ifeq ($(SOC),$(filter $(SOC),mx7)) ifeq ($(SOC),$(filter $(SOC),mx7))
obj-y += cpu.o obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
endif endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7))
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o

262
arch/arm/mach-imx/cmd_dek.c
View File

@ -14,6 +14,12 @@
#include <fsl_sec.h> #include <fsl_sec.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <mapmem.h> #include <mapmem.h>
#include <tee.h>
#ifdef CONFIG_IMX_SECO_DEK_ENCAP
#include <asm/arch/sci/sci.h>
#include <asm/arch/image.h>
#endif
#include <cpu_func.h>
/** /**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key * blob_dek() - Encapsulate the DEK as a blob using CAM's Key
@ -23,16 +29,20 @@
* *
* Returns zero on success,and negative on error. * Returns zero on success,and negative on error.
*/ */
static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) #ifdef CONFIG_IMX_CAAM_DEK_ENCAP
static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
{ {
int ret = 0; u8 *src_ptr, *dst_ptr;
u32 jr_size = 4;
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); src_ptr = map_sysmem(src_addr, len / 8);
if (out_jr_size != jr_size) { dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len / 8));
hab_caam_clock_enable(1);
hab_caam_clock_enable(1);
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init(); sec_init();
}
if (!((len == 128) | (len == 192) | (len == 256))) { if (!((len == 128) | (len == 192) | (len == 256))) {
debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
@ -40,10 +50,237 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
} }
len /= 8; len /= 8;
ret = blob_dek(src, dst, len); return blob_dek(src_ptr, dst_ptr, len);
}
#endif /* CONFIG_IMX_CAAM_DEK_ENCAP */
#ifdef CONFIG_IMX_OPTEE_DEK_ENCAP
#define PTA_DEK_BLOB_PTA_UUID {0xef477737, 0x0db1, 0x4a9d, \
{0x84, 0x37, 0xf2, 0xf5, 0x35, 0xc0, 0xbd, 0x92} }
#define OPTEE_BLOB_HDR_SIZE 8
static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
{
struct udevice *dev = NULL;
struct tee_shm *shm_input, *shm_output;
struct tee_open_session_arg arg = {0};
struct tee_invoke_arg arg_func = {0};
const struct tee_optee_ta_uuid uuid = PTA_DEK_BLOB_PTA_UUID;
struct tee_param param[4] = {0};
int ret;
/* Get tee device */
dev = tee_find_device(NULL, NULL, NULL, NULL);
if (!dev) {
printf("Cannot get OP-TEE device\n");
return -1;
}
/* Set TA UUID */
tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
/* Open TA session */
ret = tee_open_session(dev, &arg, 0, NULL);
if (ret < 0) {
printf("Cannot open session with PTA Blob 0x%X\n", ret);
return -1;
}
/* Allocate shared input and output buffers for TA */
ret = tee_shm_register(dev, (void *)(ulong)src_addr, len / 8, 0x0, &shm_input);
if (ret < 0) {
printf("Cannot register input shared memory 0x%X\n", ret);
goto error;
}
ret = tee_shm_register(dev, (void *)(ulong)dst_addr,
BLOB_SIZE(len / 8) + OPTEE_BLOB_HDR_SIZE,
0x0, &shm_output);
if (ret < 0) {
printf("Cannot register output shared memory 0x%X\n", ret);
goto error;
}
param[0].u.memref.shm = shm_input;
param[0].u.memref.size = shm_input->size;
param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
param[1].u.memref.shm = shm_output;
param[1].u.memref.size = shm_output->size;
param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
param[2].attr = TEE_PARAM_ATTR_TYPE_NONE;
param[3].attr = TEE_PARAM_ATTR_TYPE_NONE;
arg_func.func = 0;
arg_func.session = arg.session;
/* Generate DEK blob */
arg_func.session = arg.session;
ret = tee_invoke_func(dev, &arg_func, 4, param);
if (ret < 0)
printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
error:
/* Free shared memory */
tee_shm_free(shm_input);
tee_shm_free(shm_output);
/* Close session */
ret = tee_close_session(dev, arg.session);
if (ret < 0)
printf("Cannot close session with PTA DEK Blob 0x%X\n", ret);
return ret; return ret;
} }
#endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */
#ifdef CONFIG_IMX_SECO_DEK_ENCAP
#define DEK_BLOB_KEY_ID 0x0
#define AHAB_PRIVATE_KEY 0x81
#define AHAB_VERSION 0x00
#define AHAB_MODE_CBC 0x67
#define AHAB_ALG_AES 0x55
#define AHAB_128_AES_KEY 0x10
#define AHAB_192_AES_KEY 0x18
#define AHAB_256_AES_KEY 0x20
#define AHAB_FLAG_KEK 0x80
#define AHAB_DEK_BLOB 0x01
#define DEK_BLOB_HDR_SIZE 8
#define SECO_PT 2U
static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
{
sc_err_t err;
sc_rm_mr_t mr_input, mr_output;
struct generate_key_blob_hdr hdr;
u8 in_size, out_size;
u8 *src_ptr, *dst_ptr;
int ret = 0;
int i;
/* Set sizes */
in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
/* Get src and dst virtual addresses */
src_ptr = map_sysmem(src_addr, in_size);
dst_ptr = map_sysmem(dst_addr, out_size);
/* Check addr input */
if (!(src_ptr && dst_ptr)) {
debug("src_addr or dst_addr invalid\n");
return -1;
}
/* Build key header */
hdr.version = AHAB_VERSION;
hdr.length_lsb = sizeof(struct generate_key_blob_hdr) + len / 8;
hdr.length_msb = 0x00;
hdr.tag = AHAB_PRIVATE_KEY;
hdr.flags = AHAB_DEK_BLOB;
hdr.algorithm = AHAB_ALG_AES;
hdr.mode = AHAB_MODE_CBC;
switch (len) {
case 128:
hdr.size = AHAB_128_AES_KEY;
break;
case 192:
hdr.size = AHAB_192_AES_KEY;
break;
case 256:
hdr.size = AHAB_256_AES_KEY;
break;
default:
/* Not supported */
debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
return -1;
}
/* Build input message */
memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
(void *)src_ptr, len / 8);
memcpy((void *)src_ptr, (void *)&hdr,
sizeof(struct generate_key_blob_hdr));
/* Flush the cache before triggering the CAAM DMA */
flush_dcache_range(src_addr, src_addr + in_size);
/* Find input memory region */
err = sc_rm_find_memreg((-1), &mr_input, src_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
ALIGN(src_addr + in_size, CONFIG_SYS_CACHELINE_SIZE));
if (err) {
printf("Error: find memory region 0x%X\n", src_addr);
return -ENOMEM;
}
/* Find output memory region */
err = sc_rm_find_memreg((-1), &mr_output, dst_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
ALIGN(dst_addr + out_size, CONFIG_SYS_CACHELINE_SIZE));
if (err) {
printf("Error: find memory region 0x%X\n", dst_addr);
return -ENOMEM;
}
/* Set memory region permissions for SECO */
err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT,
SC_RM_PERM_FULL);
if (err) {
printf("Set permission failed for input memory region\n");
ret = -EPERM;
goto error;
}
err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT,
SC_RM_PERM_FULL);
if (err) {
printf("Set permission failed for output memory region\n");
ret = -EPERM;
goto error;
}
/* Flush output data before SECO operation */
flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
roundup(out_size, ARCH_DMA_MINALIGN)));
/* Generate DEK blob */
err = sc_seco_gen_key_blob((-1), 0x0, src_addr, dst_addr, out_size);
if (err) {
ret = -EPERM;
goto error;
}
/* Invalidate output buffer */
invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
roundup(out_size, ARCH_DMA_MINALIGN)));
printf("DEK Blob\n");
for (i = 0; i < DEK_BLOB_HDR_SIZE + BLOB_SIZE(len / 8); i++)
printf("%02X", dst_ptr[i]);
printf("\n");
error:
/* Remove memory region permission to SECO */
err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT,
SC_RM_PERM_NONE);
if (err) {
printf("Error: remove permission failed for input\n");
ret = -EPERM;
}
err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT,
SC_RM_PERM_NONE);
if (err) {
printf("Error: remove permission failed for output\n");
ret = -EPERM;
}
return ret;
}
#endif /* CONFIG_IMX_SECO_DEK_ENCAP */
/** /**
* do_dek_blob() - Handle the "dek_blob" command-line command * do_dek_blob() - Handle the "dek_blob" command-line command
@ -59,8 +296,6 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]) char *const argv[])
{ {
uint32_t src_addr, dst_addr, len; uint32_t src_addr, dst_addr, len;
uint8_t *src_ptr, *dst_ptr;
int ret = 0;
if (argc != 4) if (argc != 4)
return CMD_RET_USAGE; return CMD_RET_USAGE;
@ -69,12 +304,7 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc,
dst_addr = simple_strtoul(argv[2], NULL, 16); dst_addr = simple_strtoul(argv[2], NULL, 16);
len = simple_strtoul(argv[3], NULL, 10); len = simple_strtoul(argv[3], NULL, 10);
src_ptr = map_sysmem(src_addr, len/8); return blob_encap_dek(src_addr, dst_addr, len);
dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
ret = blob_encap_dek(src_ptr, dst_ptr, len);
return ret;
} }
/***************************************************/ /***************************************************/

150
arch/arm/mach-imx/cmd_mfgprot.c Normal file
View File

@ -0,0 +1,150 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* These commands enable the use of the CAAM MPPubK-generation and MPSign
* functions in supported i.MX devices.
*/
#include <asm/byteorder.h>
#include <asm/arch/clock.h>
#include <linux/compiler.h>
#include <command.h>
#include <common.h>
#include <environment.h>
#include <fsl_sec.h>
#include <mapmem.h>
#include <memalign.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* do_mfgprot() - Handle the "mfgprot" command-line command
* @cmdtp: Command data struct pointer
* @flag: Command flag
* @argc: Command-line argument count
* @argv: Array of command-line arguments
*
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr;
char *pubk, *sign, *sel;
int m_size, i, ret;
u32 m_addr;
pubk = "pubk";
sign = "sign";
sel = argv[1];
/* Enable HAB clock */
hab_caam_clock_enable(1);
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
if (strcmp(sel, pubk) == 0) {
dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES);
if (!dst_ptr)
return -ENOMEM;
ret = gen_mppubk(dst_ptr);
if (ret) {
free(dst_ptr);
return ret;
}
/* Output results */
puts("Public key:\n");
for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++)
printf("%02X", (dst_ptr)[i]);
puts("\n");
free(dst_ptr);
} else if (strcmp(sel, sign) == 0) {
if (argc != 4)
return CMD_RET_USAGE;
m_addr = simple_strtoul(argv[2], NULL, 16);
m_size = simple_strtoul(argv[3], NULL, 10);
m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE);
if (!m_ptr)
return -ENOMEM;
dgst_ptr = malloc_cache_aligned(FSL_CAAM_MP_MES_DGST_BYTES);
if (!dgst_ptr) {
ret = -ENOMEM;
goto free_m;
}
c_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES);
if (!c_ptr) {
ret = -ENOMEM;
goto free_dgst;
}
d_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES);
if (!d_ptr) {
ret = -ENOMEM;
goto free_c;
}
ret = sign_mppubk(m_ptr, m_size, dgst_ptr, c_ptr, d_ptr);
if (ret)
goto free_d;
/* Output results */
puts("Message: ");
for (i = 0; i < m_size; i++)
printf("%02X ", (m_ptr)[i]);
puts("\n");
puts("Message Representative Digest(SHA-256):\n");
for (i = 0; i < FSL_CAAM_MP_MES_DGST_BYTES; i++)
printf("%02X", (dgst_ptr)[i]);
puts("\n");
puts("Signature:\n");
puts("C:\n");
for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++)
printf("%02X", (c_ptr)[i]);
puts("\n");
puts("d:\n");
for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++)
printf("%02X", (d_ptr)[i]);
puts("\n");
free_d:
free(d_ptr);
free_c:
free(c_ptr);
free_dgst:
free(dgst_ptr);
free_m:
unmap_sysmem(m_ptr);
} else {
return CMD_RET_USAGE;
}
return ret;
}
/***************************************************/
static char mfgprot_help_text[] =
"Usage:\n"
"Print the public key for Manufacturing Protection\n"
"\tmfgprot pubk\n"
"Generates a Manufacturing Protection signature\n"
"\tmfgprot sign <data_addr> <size>";
U_BOOT_CMD(
mfgprot, 4, 1, do_mfgprot,
"Manufacturing Protection\n",
mfgprot_help_text
);

8
arch/arm/mach-imx/cpu.c
View File

@ -117,7 +117,13 @@ const char *get_imx_type(u32 imxtype)
case MXC_CPU_IMX8MNDL: case MXC_CPU_IMX8MNDL:
return "8MNano DualLite"; /* Dual-core Lite version */ return "8MNano DualLite"; /* Dual-core Lite version */
case MXC_CPU_IMX8MNSL: case MXC_CPU_IMX8MNSL:
return "8MNano SoloLite"; /* Single-core Lite version */ return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
case MXC_CPU_IMX8MNUQ:
return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
case MXC_CPU_IMX8MNUD:
return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
case MXC_CPU_IMX8MNUS:
return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
case MXC_CPU_IMX8MM: case MXC_CPU_IMX8MM:
return "8MMQ"; /* Quad-core version of the imx8mm */ return "8MMQ"; /* Quad-core version of the imx8mm */
case MXC_CPU_IMX8MML: case MXC_CPU_IMX8MML:

417
arch/arm/mach-imx/hab.c
View File

@ -10,10 +10,14 @@
#include <mapmem.h> #include <mapmem.h>
#include <image.h> #include <image.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/global_data.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/mach-imx/hab.h> #include <asm/mach-imx/hab.h>
#include <linux/arm-smccc.h>
DECLARE_GLOBAL_DATA_PTR;
#define ALIGN_SIZE 0x1000 #define ALIGN_SIZE 0x1000
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
@ -21,7 +25,13 @@
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60
#define IS_HAB_ENABLED_BIT \ #define IS_HAB_ENABLED_BIT \
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) ((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M)) ? 0x2000000 : 0x2))
#ifdef CONFIG_MX7ULP
#define HAB_M4_PERSISTENT_START ((soc_rev() >= CHIP_REV_2_0) ? 0x20008040 : \
0x20008180)
#define HAB_M4_PERSISTENT_BYTES 0xB80
#endif
static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr) static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
{ {
@ -41,13 +51,200 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr)
if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH)
result = ivt_header_error("bad length", ivt_hdr); result = ivt_header_error("bad length", ivt_hdr);
if (ivt_hdr->version != IVT_HEADER_V1 && if ((ivt_hdr->version & HAB_MAJ_MASK) != HAB_MAJ_VER)
ivt_hdr->version != IVT_HEADER_V2)
result = ivt_header_error("bad version", ivt_hdr); result = ivt_header_error("bad version", ivt_hdr);
return result; return result;
} }
#ifdef CONFIG_ARM64
#define FSL_SIP_HAB 0xC2000007
#define FSL_SIP_HAB_AUTHENTICATE 0x00
#define FSL_SIP_HAB_ENTRY 0x01
#define FSL_SIP_HAB_EXIT 0x02
#define FSL_SIP_HAB_REPORT_EVENT 0x03
#define FSL_SIP_HAB_REPORT_STATUS 0x04
#define FSL_SIP_HAB_FAILSAFE 0x05
#define FSL_SIP_HAB_CHECK_TARGET 0x06
static volatile gd_t *gd_save;
#endif
static inline void save_gd(void)
{
#ifdef CONFIG_ARM64
gd_save = gd;
#endif
}
static inline void restore_gd(void)
{
#ifdef CONFIG_ARM64
/*
* Make will already error that reserving x18 is not supported at the
* time of writing, clang: error: unknown argument: '-ffixed-x18'
*/
__asm__ volatile("mov x18, %0\n" : : "r" (gd_save));
#endif
}
enum hab_status hab_rvt_report_event(enum hab_status status, u32 index,
u8 *event, size_t *bytes)
{
enum hab_status ret;
hab_rvt_report_event_t *hab_rvt_report_event_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_report_event_func = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_EVENT, (unsigned long)index,
(unsigned long)event, (unsigned long)bytes, 0, 0, 0, &res);
return (enum hab_status)res.a0;
}
#endif
save_gd();
ret = hab_rvt_report_event_func(status, index, event, bytes);
restore_gd();
return ret;
}
enum hab_status hab_rvt_report_status(enum hab_config *config, enum hab_state *state)
{
enum hab_status ret;
hab_rvt_report_status_t *hab_rvt_report_status_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_report_status_func = (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_STATUS, (unsigned long)config,
(unsigned long)state, 0, 0, 0, 0, &res);
return (enum hab_status)res.a0;
}
#endif
save_gd();
ret = hab_rvt_report_status_func(config, state);
restore_gd();
return ret;
}
enum hab_status hab_rvt_entry(void)
{
enum hab_status ret;
hab_rvt_entry_t *hab_rvt_entry_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_entry_func = (hab_rvt_entry_t *)HAB_RVT_ENTRY;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_ENTRY, 0, 0, 0, 0, 0, 0, &res);
return (enum hab_status)res.a0;
}
#endif
save_gd();
ret = hab_rvt_entry_func();
restore_gd();
return ret;
}
enum hab_status hab_rvt_exit(void)
{
enum hab_status ret;
hab_rvt_exit_t *hab_rvt_exit_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_exit_func = (hab_rvt_exit_t *)HAB_RVT_EXIT;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_EXIT, 0, 0, 0, 0, 0, 0, &res);
return (enum hab_status)res.a0;
}
#endif
save_gd();
ret = hab_rvt_exit_func();
restore_gd();
return ret;
}
void hab_rvt_failsafe(void)
{
hab_rvt_failsafe_t *hab_rvt_failsafe_func;
hab_rvt_failsafe_func = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_FAILSAFE, 0, 0, 0, 0, 0, 0, NULL);
return;
}
#endif
save_gd();
hab_rvt_failsafe_func();
restore_gd();
}
enum hab_status hab_rvt_check_target(enum hab_target type, const void *start,
size_t bytes)
{
enum hab_status ret;
hab_rvt_check_target_t *hab_rvt_check_target_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_check_target_func = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_CHECK_TARGET, (unsigned long)type,
(unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res);
return (enum hab_status)res.a0;
}
#endif
save_gd();
ret = hab_rvt_check_target_func(type, start, bytes);
restore_gd();
return ret;
}
void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset,
void **start, size_t *bytes, hab_loader_callback_f_t loader)
{
void *ret;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image_func;
struct arm_smccc_res res __maybe_unused;
hab_rvt_authenticate_image_func = (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE;
#if defined(CONFIG_ARM64)
if (current_el() != 3) {
/* call sip */
arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_AUTHENTICATE, (unsigned long)ivt_offset,
(unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res);
return (void *)res.a0;
}
#endif
save_gd();
ret = hab_rvt_authenticate_image_func(cid, ivt_offset, start, bytes, loader);
restore_gd();
return ret;
}
#if !defined(CONFIG_SPL_BUILD) #if !defined(CONFIG_SPL_BUILD)
#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
@ -253,12 +450,6 @@ static int get_hab_status(void)
size_t bytes = sizeof(event_data); /* Event size in bytes */ size_t bytes = sizeof(event_data); /* Event size in bytes */
enum hab_config config = 0; enum hab_config config = 0;
enum hab_state state = 0; enum hab_state state = 0;
hab_rvt_report_event_t *hab_rvt_report_event;
hab_rvt_report_status_t *hab_rvt_report_status;
hab_rvt_report_event = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT;
hab_rvt_report_status =
(hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS;
if (imx_hab_is_enabled()) if (imx_hab_is_enabled())
puts("\nSecure boot enabled\n"); puts("\nSecure boot enabled\n");
@ -270,8 +461,8 @@ static int get_hab_status(void)
printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
config, state); config, state);
/* Display HAB Error events */ /* Display HAB events */
while (hab_rvt_report_event(HAB_FAILURE, index, event_data, while (hab_rvt_report_event(HAB_STS_ANY, index, event_data,
&bytes) == HAB_SUCCESS) { &bytes) == HAB_SUCCESS) {
puts("\n"); puts("\n");
printf("--------- HAB Event %d -----------------\n", printf("--------- HAB Event %d -----------------\n",
@ -292,15 +483,99 @@ static int get_hab_status(void)
return 0; return 0;
} }
#ifdef CONFIG_MX7ULP
static int get_record_len(struct record *rec)
{
return (size_t)((rec->len[0] << 8) + (rec->len[1]));
}
static int get_hab_status_m4(void)
{
unsigned int index = 0;
uint8_t event_data[128];
size_t record_len, offset = 0;
enum hab_config config = 0;
enum hab_state state = 0;
if (imx_hab_is_enabled())
puts("\nSecure boot enabled\n");
else
puts("\nSecure boot disabled\n");
/*
* HAB in both A7 and M4 gather the security state
* and configuration of the chip from
* shared SNVS module
*/
hab_rvt_report_status(&config, &state);
printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
config, state);
struct record *rec = (struct record *)(HAB_M4_PERSISTENT_START);
record_len = get_record_len(rec);
/* Check if HAB persistent memory is valid */
if (rec->tag != HAB_TAG_EVT_DEF ||
record_len != sizeof(struct evt_def) ||
(rec->par & HAB_MAJ_MASK) != HAB_MAJ_VER) {
puts("\nERROR: Invalid HAB persistent memory\n");
return 1;
}
/* Parse events in HAB M4 persistent memory region */
while (offset < HAB_M4_PERSISTENT_BYTES) {
rec = (struct record *)(HAB_M4_PERSISTENT_START + offset);
record_len = get_record_len(rec);
if (rec->tag == HAB_TAG_EVT) {
memcpy(&event_data, rec, record_len);
puts("\n");
printf("--------- HAB Event %d -----------------\n",
index + 1);
puts("event data:\n");
display_event(event_data, record_len);
puts("\n");
index++;
}
offset += record_len;
/* Ensure all records start on a word boundary */
if ((offset % 4) != 0)
offset = offset + (4 - (offset % 4));
}
if (!index)
puts("No HAB Events Found!\n\n");
return 0;
}
#endif
static int do_hab_status(struct cmd_tbl *cmdtp, int flag, int argc, static int do_hab_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]) char *const argv[])
{ {
#ifdef CONFIG_MX7ULP
if ((argc > 2)) {
cmd_usage(cmdtp);
return 1;
}
if (strcmp("m4", argv[1]) == 0)
get_hab_status_m4();
else
get_hab_status();
#else
if ((argc != 1)) { if ((argc != 1)) {
cmd_usage(cmdtp); cmd_usage(cmdtp);
return 1; return 1;
} }
get_hab_status(); get_hab_status();
#endif
return 0; return 0;
} }
@ -353,14 +628,11 @@ static int do_authenticate_image(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_hab_failsafe(struct cmd_tbl *cmdtp, int flag, int argc, static int do_hab_failsafe(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]) char *const argv[])
{ {
hab_rvt_failsafe_t *hab_rvt_failsafe;
if (argc != 1) { if (argc != 1) {
cmd_usage(cmdtp); cmd_usage(cmdtp);
return 1; return 1;
} }
hab_rvt_failsafe = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE;
hab_rvt_failsafe(); hab_rvt_failsafe();
return 0; return 0;
@ -406,11 +678,20 @@ error:
return ret; return ret;
} }
#ifdef CONFIG_MX7ULP
U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 2, do_hab_status,
"display HAB status and events",
"hab_status - A7 HAB event and status\n"
"hab_status m4 - M4 HAB event and status"
);
#else
U_BOOT_CMD( U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
"display HAB status", "display HAB status",
"" ""
); );
#endif
U_BOOT_CMD( U_BOOT_CMD(
hab_auth_img, 4, 0, do_authenticate_image, hab_auth_img, 4, 0, do_authenticate_image,
@ -493,7 +774,7 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes)
return false; return false;
} }
csf_hdr = (u8 *)ivt->csf; csf_hdr = (u8 *)(ulong)ivt->csf;
/* Verify if CSF Header exist */ /* Verify if CSF Header exist */
if (*csf_hdr != HAB_CMD_HDR) { if (*csf_hdr != HAB_CMD_HDR) {
@ -542,6 +823,48 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes)
return true; return true;
} }
/*
* Validate IVT structure of the image being authenticated
*/
static int validate_ivt(struct ivt *ivt_initial)
{
struct ivt_header *ivt_hdr = &ivt_initial->hdr;
if ((ulong)ivt_initial & 0x3) {
puts("Error: Image's start address is not 4 byte aligned\n");
return 0;
}
/* Check IVT fields before allowing authentication */
if ((!verify_ivt_header(ivt_hdr)) && \
(ivt_initial->entry != 0x0) && \
(ivt_initial->reserved1 == 0x0) && \
(ivt_initial->self == \
(uint32_t)((ulong)ivt_initial & 0xffffffff)) && \
(ivt_initial->csf != 0x0) && \
(ivt_initial->reserved2 == 0x0)) {
/* Report boot failure if DCD pointer is found in IVT */
if (ivt_initial->dcd != 0x0)
puts("Error: DCD pointer must be 0\n");
else
return 1;
}
puts("Error: Invalid IVT structure\n");
debug("\nAllowed IVT structure:\n");
debug("IVT HDR = 0x4X2000D1\n");
debug("IVT ENTRY = 0xXXXXXXXX\n");
debug("IVT RSV1 = 0x0\n");
debug("IVT DCD = 0x0\n"); /* Recommended */
debug("IVT BOOT_DATA = 0xXXXXXXXX\n"); /* Commonly 0x0 */
debug("IVT SELF = 0xXXXXXXXX\n"); /* = ddr_start + ivt_offset */
debug("IVT CSF = 0xXXXXXXXX\n");
debug("IVT RSV2 = 0x0\n");
/* Invalid IVT structure */
return 0;
}
bool imx_hab_is_enabled(void) bool imx_hab_is_enabled(void)
{ {
struct imx_sec_config_fuse_t *fuse = struct imx_sec_config_fuse_t *fuse =
@ -561,29 +884,16 @@ bool imx_hab_is_enabled(void)
int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
uint32_t ivt_offset) uint32_t ivt_offset)
{ {
uint32_t load_addr = 0; ulong load_addr = 0;
size_t bytes; size_t bytes;
uint32_t ivt_addr = 0; ulong ivt_addr = 0;
int result = 1; int result = 1;
ulong start; ulong start;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
hab_rvt_check_target_t *hab_rvt_check_target;
struct ivt *ivt; struct ivt *ivt;
struct ivt_header *ivt_hdr;
enum hab_status status; enum hab_status status;
hab_rvt_authenticate_image = if (!imx_hab_is_enabled())
(hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE;
hab_rvt_entry = (hab_rvt_entry_t *)HAB_RVT_ENTRY;
hab_rvt_exit = (hab_rvt_exit_t *)HAB_RVT_EXIT;
hab_rvt_check_target = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET;
if (!imx_hab_is_enabled()) {
puts("hab fuse not enabled\n"); puts("hab fuse not enabled\n");
return 0;
}
printf("\nAuthenticate image from DDR location 0x%x...\n", printf("\nAuthenticate image from DDR location 0x%x...\n",
ddr_start); ddr_start);
@ -591,27 +901,13 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
hab_caam_clock_enable(1); hab_caam_clock_enable(1);
/* Calculate IVT address header */ /* Calculate IVT address header */
ivt_addr = ddr_start + ivt_offset; ivt_addr = (ulong) (ddr_start + ivt_offset);
ivt = (struct ivt *)ivt_addr; ivt = (struct ivt *)ivt_addr;
ivt_hdr = &ivt->hdr;
/* Verify IVT header bugging out on error */ /* Verify IVT header bugging out on error */
if (verify_ivt_header(ivt_hdr)) if (!validate_ivt(ivt))
goto hab_authentication_exit; goto hab_authentication_exit;
/* Verify IVT body */
if (ivt->self != ivt_addr) {
printf("ivt->self 0x%08x pointer is 0x%08x\n",
ivt->self, ivt_addr);
goto hab_authentication_exit;
}
/* Verify if IVT DCD pointer is NULL */
if (ivt->dcd) {
puts("Error: DCD pointer must be NULL\n");
goto hab_authentication_exit;
}
start = ddr_start; start = ddr_start;
bytes = image_size; bytes = image_size;
@ -624,14 +920,14 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
goto hab_exit_failure_print_status; goto hab_exit_failure_print_status;
} }
status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes); status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes);
if (status != HAB_SUCCESS) { if (status != HAB_SUCCESS) {
printf("HAB check target 0x%08x-0x%08x fail\n", printf("HAB check target 0x%08x-0x%08lx fail\n",
ddr_start, ddr_start + bytes); ddr_start, ddr_start + (ulong)bytes);
goto hab_exit_failure_print_status; goto hab_exit_failure_print_status;
} }
#ifdef DEBUG #ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); printf("\nivt_offset = 0x%x, ivt addr = 0x%lx\n", ivt_offset, ivt_addr);
printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry,
ivt->dcd, ivt->csf); ivt->dcd, ivt->csf);
puts("Dumping IVT\n"); puts("Dumping IVT\n");
@ -649,6 +945,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
printf("\tstart = 0x%08lx\n", start); printf("\tstart = 0x%08lx\n", start);
printf("\tbytes = 0x%x\n", bytes); printf("\tbytes = 0x%x\n", bytes);
#endif #endif
#ifndef CONFIG_ARM64
/* /*
* If the MMU is enabled, we have to notify the ROM * If the MMU is enabled, we have to notify the ROM
* code, or it won't flush the caches when needed. * code, or it won't flush the caches when needed.
@ -676,8 +974,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
writel(1, MX6SL_PU_IROM_MMU_EN_VAR); writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
} }
} }
#endif
load_addr = (uint32_t)hab_rvt_authenticate_image( load_addr = (ulong)hab_rvt_authenticate_image(
HAB_CID_UBOOT, HAB_CID_UBOOT,
ivt_offset, (void **)&start, ivt_offset, (void **)&start,
(size_t *)&bytes, NULL); (size_t *)&bytes, NULL);
@ -693,8 +992,20 @@ hab_exit_failure_print_status:
hab_authentication_exit: hab_authentication_exit:
if (load_addr != 0) if (load_addr != 0 || !imx_hab_is_enabled())
result = 0; result = 0;
return result; return result;
} }
int authenticate_image(u32 ddr_start, u32 raw_image_size)
{
u32 ivt_offset;
size_t bytes;
ivt_offset = (raw_image_size + ALIGN_SIZE - 1) &
~(ALIGN_SIZE - 1);
bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
return imx_hab_authenticate_image(ddr_start, bytes, ivt_offset);
}

1
arch/arm/mach-imx/imx8/Kconfig
View File

@ -2,6 +2,7 @@ if ARCH_IMX8
config AHAB_BOOT config AHAB_BOOT
bool "Support i.MX8 AHAB features" bool "Support i.MX8 AHAB features"
imply CMD_DEKBLOB
help help
This option enables the support for AHAB secure boot. This option enables the support for AHAB secure boot.

11
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -2,6 +2,7 @@ if ARCH_IMX8M
config IMX8M config IMX8M
bool bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS select ROM_UNIFIED_SECTIONS
config IMX8MQ config IMX8MQ
@ -39,6 +40,7 @@ config TARGET_IMX8MQ_PHANBELL
config TARGET_IMX8MM_EVK config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board" bool "imx8mm LPDDR4 EVK board"
select BINMAN
select IMX8MM select IMX8MM
select SUPPORT_SPL select SUPPORT_SPL
select IMX8M_LPDDR4 select IMX8M_LPDDR4
@ -49,14 +51,23 @@ config TARGET_IMX8MM_VENICE
select SUPPORT_SPL select SUPPORT_SPL
select IMX8M_LPDDR4 select IMX8M_LPDDR4
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_DDR4_EVK config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board" bool "imx8mn DDR4 EVK board"
select BINMAN
select IMX8MN select IMX8MN
select SUPPORT_SPL select SUPPORT_SPL
select IMX8M_DDR4 select IMX8M_DDR4
config TARGET_IMX8MP_EVK config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board" bool "imx8mp LPDDR4 EVK board"
select BINMAN
select IMX8MP select IMX8MP
select SUPPORT_SPL select SUPPORT_SPL
select IMX8M_LPDDR4 select IMX8M_LPDDR4

8
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -21,6 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 get_root_clk(enum clk_root_index clock_id); static u32 get_root_clk(enum clk_root_index clock_id);
#ifdef CONFIG_IMX_HAB
void hab_caam_clock_enable(unsigned char enable)
{
/* The CAAM clock is always on for iMX8M */
}
#endif
void enable_ocotp_clk(unsigned char enable) void enable_ocotp_clk(unsigned char enable)
{ {
clock_enable(CCGR_OCOTP, !!enable); clock_enable(CCGR_OCOTP, !!enable);

7
arch/arm/mach-imx/imx8m/clock_imx8mq.c
View File

@ -310,6 +310,13 @@ static u32 get_root_clk(enum clk_root_index clock_id)
return root_src_clk / (post_podf + 1) / (pre_podf + 1); return root_src_clk / (post_podf + 1) / (pre_podf + 1);
} }
#ifdef CONFIG_IMX_HAB
void hab_caam_clock_enable(unsigned char enable)
{
/* The CAAM clock is always on for iMX8M */
}
#endif
#ifdef CONFIG_MXC_OCOTP #ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable) void enable_ocotp_clk(unsigned char enable)
{ {

190
arch/arm/mach-imx/imx8m/soc.c
View File

@ -104,6 +104,13 @@ static struct mm_region imx8m_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* OCRAM_S */
.virt = 0x180000UL,
.phys = 0x180000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, { }, {
/* TCM */ /* TCM */
.virt = 0x7C0000UL, .virt = 0x7C0000UL,
@ -324,18 +331,30 @@ static u32 get_cpu_variant_type(u32 type)
} else if (type == MXC_CPU_IMX8MN) { } else if (type == MXC_CPU_IMX8MN) {
switch (value & 0x3) { switch (value & 0x3) {
case 2: case 2:
if (value & 0x1000000) if (value & 0x1000000) {
return MXC_CPU_IMX8MNDL; if (value & 0x10000000) /* MIPI DSI */
else return MXC_CPU_IMX8MNUD;
else
return MXC_CPU_IMX8MNDL;
} else {
return MXC_CPU_IMX8MND; return MXC_CPU_IMX8MND;
}
case 3: case 3:
if (value & 0x1000000) if (value & 0x1000000) {
return MXC_CPU_IMX8MNSL; if (value & 0x10000000) /* MIPI DSI */
else return MXC_CPU_IMX8MNUS;
else
return MXC_CPU_IMX8MNSL;
} else {
return MXC_CPU_IMX8MNS; return MXC_CPU_IMX8MNS;
}
default: default:
if (value & 0x1000000) if (value & 0x1000000) {
return MXC_CPU_IMX8MNL; if (value & 0x10000000) /* MIPI DSI */
return MXC_CPU_IMX8MNUQ;
else
return MXC_CPU_IMX8MNL;
}
break; break;
} }
} else if (type == MXC_CPU_IMX8MP) { } else if (type == MXC_CPU_IMX8MP) {
@ -398,7 +417,16 @@ u32 get_cpu_rev(void)
* 0xff0055aa is magic number for B1. * 0xff0055aa is magic number for B1.
*/ */
if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
reg = CHIP_REV_2_1; /*
* B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
* so have to check ROM to distinguish them
*/
rom_version = readl((void __iomem *)ROM_VERSION_B0);
rom_version &= 0xff;
if (rom_version == CHIP_REV_2_2)
reg = CHIP_REV_2_2;
else
reg = CHIP_REV_2_1;
} else { } else {
rom_version = rom_version =
readl((void __iomem *)ROM_VERSION_A0); readl((void __iomem *)ROM_VERSION_A0);
@ -468,7 +496,7 @@ int arch_cpu_init(void)
if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() || is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
is_imx8mnsl() || is_imx8mpd()) { is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
/* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */ /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
@ -477,7 +505,7 @@ int arch_cpu_init(void)
writel(0x1, &pgc_core2->pgcr); writel(0x1, &pgc_core2->pgcr);
writel(0x1, &pgc_core3->pgcr); writel(0x1, &pgc_core3->pgcr);
if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) { if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
writel(0x1, &pgc_core1->pgcr); writel(0x1, &pgc_core1->pgcr);
writel(0xE, &gpc->cpu_pgc_dn_trg); writel(0xE, &gpc->cpu_pgc_dn_trg);
} else { } else {
@ -616,7 +644,8 @@ static int disable_mipi_dsi_nodes(void *blob)
"/mipi_dsi_bridge@30A00000", "/mipi_dsi_bridge@30A00000",
"/dsi_phy@30A00300", "/dsi_phy@30A00300",
"/soc@0/bus@30800000/mipi_dsi@30a00000", "/soc@0/bus@30800000/mipi_dsi@30a00000",
"/soc@0/bus@30800000/dphy@30a00300" "/soc@0/bus@30800000/dphy@30a00300",
"/soc@0/bus@30800000/mipi-dsi@30a00000",
}; };
return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
@ -644,7 +673,8 @@ static int check_mipi_dsi_nodes(void *blob)
{ {
static const char * const lcdif_path[] = { static const char * const lcdif_path[] = {
"/lcdif@30320000", "/lcdif@30320000",
"/soc@0/bus@30000000/lcdif@30320000" "/soc@0/bus@30000000/lcdif@30320000",
"/soc@0/bus@30000000/lcd-controller@30320000"
}; };
static const char * const mipi_dsi_path[] = { static const char * const mipi_dsi_path[] = {
"/mipi_dsi@30A00000", "/mipi_dsi@30A00000",
@ -652,11 +682,13 @@ static int check_mipi_dsi_nodes(void *blob)
}; };
static const char * const lcdif_ep_path[] = { static const char * const lcdif_ep_path[] = {
"/lcdif@30320000/port@0/mipi-dsi-endpoint", "/lcdif@30320000/port@0/mipi-dsi-endpoint",
"/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint" "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
"/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
}; };
static const char * const mipi_dsi_ep_path[] = { static const char * const mipi_dsi_ep_path[] = {
"/mipi_dsi@30A00000/port@1/endpoint", "/mipi_dsi@30A00000/port@1/endpoint",
"/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint" "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
"/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
}; };
int lookup_node; int lookup_node;
@ -726,10 +758,46 @@ int disable_vpu_nodes(void *blob)
return -EPERM; return -EPERM;
} }
#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
static int low_drive_gpu_freq(void *blob)
{
static const char *nodes_path_8mn[] = {
"/gpu@38000000",
"/soc@0/gpu@38000000"
};
int nodeoff, cnt, i;
u32 assignedclks[7];
nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
if (nodeoff < 0)
return nodeoff;
cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
if (cnt < 0)
return cnt;
if (cnt != 7)
printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
assignedclks[cnt - 1] = 200000000;
assignedclks[cnt - 2] = 200000000;
for (i = 0; i < cnt; i++) {
debug("<%u>, ", assignedclks[i]);
assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
}
debug("\n");
return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
}
#endif
int disable_gpu_nodes(void *blob) int disable_gpu_nodes(void *blob)
{ {
static const char * const nodes_path_8mn[] = { static const char * const nodes_path_8mn[] = {
"/gpu@38000000" "/gpu@38000000",
"/soc@/gpu@38000000"
}; };
return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn)); return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
@ -763,6 +831,79 @@ int disable_dsp_nodes(void *blob)
return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
} }
static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const thermal_path[] = {
"/thermal-zones/cpu-thermal/cooling-maps/map0"
};
int nodeoff, cnt, i, ret, j;
u32 cooling_dev[12];
for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
nodeoff = fdt_path_offset(blob, thermal_path[i]);
if (nodeoff < 0)
continue; /* Not found, skip it */
cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
if (cnt < 0)
continue;
if (cnt != 12)
printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
for (j = 0; j < cnt; j++)
cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
sizeof(u32) * (12 - disabled_cores * 3));
if (ret < 0) {
printf("Warning: %s, cooling-device setprop failed %d\n",
thermal_path[i], ret);
continue;
}
printf("Update node %s, cooling-device prop\n", thermal_path[i]);
}
}
static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const pmu_path[] = {
"/pmu"
};
int nodeoff, cnt, i, ret, j;
u32 irq_affinity[4];
for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
nodeoff = fdt_path_offset(blob, pmu_path[i]);
if (nodeoff < 0)
continue; /* Not found, skip it */
cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
irq_affinity, 4);
if (cnt < 0)
continue;
if (cnt != 4)
printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
for (j = 0; j < cnt; j++)
irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
sizeof(u32) * (4 - disabled_cores));
if (ret < 0) {
printf("Warning: %s, interrupt-affinity setprop failed %d\n",
pmu_path[i], ret);
continue;
}
printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
}
}
static int disable_cpu_nodes(void *blob, u32 disabled_cores) static int disable_cpu_nodes(void *blob, u32 disabled_cores)
{ {
static const char * const nodes_path[] = { static const char * const nodes_path[] = {
@ -795,6 +936,9 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores)
} }
} }
disable_thermal_cpu_nodes(blob, disabled_cores);
disable_pmu_cpu_nodes(blob, disabled_cores);
return 0; return 0;
} }
@ -895,10 +1039,20 @@ usb_modify_speed:
#elif defined(CONFIG_IMX8MN) #elif defined(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
disable_gpu_nodes(blob); disable_gpu_nodes(blob);
#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
else {
int ldm_gpu = low_drive_gpu_freq(blob);
if (is_imx8mnd() || is_imx8mndl()) if (ldm_gpu < 0)
printf("Update GPU node assigned-clock-rates failed\n");
else
printf("Update GPU node assigned-clock-rates ok\n");
}
#endif
if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
disable_cpu_nodes(blob, 2); disable_cpu_nodes(blob, 2);
else if (is_imx8mns() || is_imx8mnsl()) else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
disable_cpu_nodes(blob, 3); disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP) #elif defined(CONFIG_IMX8MP)

67
arch/arm/mach-imx/imx_bootaux.c
View File

@ -14,6 +14,71 @@
#include <linux/compiler.h> #include <linux/compiler.h>
#include <cpu_func.h> #include <cpu_func.h>
#ifndef CONFIG_IMX8M
const __weak struct rproc_att hostmap[] = { };
static const struct rproc_att *get_host_mapping(unsigned long auxcore)
{
const struct rproc_att *mmap = hostmap;
while (mmap && mmap->size) {
if (mmap->da <= auxcore &&
mmap->da + mmap->size > auxcore)
return mmap;
mmap++;
}
return NULL;
}
/*
* A very simple elf loader for the auxilary core, assumes the image
* is valid, returns the entry point address.
* Translates load addresses in the elf file to the U-Boot address space.
*/
static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
{
Elf32_Ehdr *ehdr; /* ELF header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
int i;
ehdr = (Elf32_Ehdr *)addr;
phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
/* Load each program header */
for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) {
const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr);
void *dst, *src;
if (phdr->p_type != PT_LOAD)
continue;
if (!mmap) {
printf("Invalid aux core address: %08x",
phdr->p_paddr);
return 0;
}
dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
src = (void *)addr + phdr->p_offset;
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
memcpy(dst, src, phdr->p_filesz);
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
flush_cache((unsigned long)dst &
~(CONFIG_SYS_CACHELINE_SIZE - 1),
ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE));
}
return ehdr->e_entry;
}
#endif
int arch_auxiliary_core_up(u32 core_id, ulong addr) int arch_auxiliary_core_up(u32 core_id, ulong addr)
{ {
ulong stack, pc; ulong stack, pc;
@ -31,7 +96,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
*/ */
if (valid_elf_image(addr)) { if (valid_elf_image(addr)) {
stack = 0x0; stack = 0x0;
pc = load_elf_image_phdr(addr); pc = load_elf_image_m_core_phdr(addr);
if (!pc) if (!pc)
return CMD_RET_FAILURE; return CMD_RET_FAILURE;

1
arch/arm/mach-imx/mx7ulp/Kconfig
View File

@ -9,6 +9,7 @@ config LDO_ENABLED_MODE
Select this option to enable the PMC1 LDO. Select this option to enable the PMC1 LDO.
config MX7ULP config MX7ULP
select HAS_CAAM
bool bool
choice choice

33
arch/arm/mach-imx/priblob.c Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/*
* Boot command to get and set the PRIBLOB bitfield form the SCFGR register
* of the CAAM IP. It is recommended to set this bitfield to 3 once your
* encrypted boot image is ready, to prevent the generation of blobs usable
* to decrypt an encrypted boot image.
*/
#include <asm/io.h>
#include <common.h>
#include <command.h>
#include "../drivers/crypto/fsl_caam_internal.h"
int do_priblob_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR);
printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3);
return 0;
}
U_BOOT_CMD(
set_priblob_bitfield, 1, 0, do_priblob_write,
"Set the PRIBLOB bitfield to 3",
"<value>\n"
" - Write 3 in PRIBLOB bitfield of SCFGR regiter of CAAM IP.\n"
" Prevent the generation of blobs usable to decrypt an\n"
" encrypted boot image."
);

163
board/embest/mx6boards/mx6boards.c
View File

@ -31,8 +31,6 @@
#include <asm/mach-imx/video.h> #include <asm/mach-imx/video.h>
#include <i2c.h> #include <i2c.h>
#include <input.h> #include <input.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h> #include <miiphy.h>
#include <netdev.h> #include <netdev.h>
#include <asm/arch/mxc_hdmi.h> #include <asm/arch/mxc_hdmi.h>
@ -93,24 +91,6 @@ static void setup_iomux_uart(void)
} }
iomux_v3_cfg_t const enet_pads[] = { iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* GPIO16 -> AR8035 25MHz */
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Reset */ /* AR8035 PHY Reset */
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Interrupt */ /* AR8035 PHY Interrupt */
@ -150,141 +130,6 @@ int board_phy_config(struct phy_device *phydev)
return 0; return 0;
} }
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* eMMC RST */
MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
if (board_type == BOARD_IS_RIOTBOARD)
ret = !gpio_get_value(USDHC3_CD_GPIO);
else if (board_type == BOARD_IS_MARSBOARD)
ret = 1; /* eMMC/uSDHC3 is always present */
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
int ret;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* ** RiOTboard :
* mmc0 SDCard slot (bottom)
* mmc1 uSDCard slot (top)
* mmc2 eMMC
* ** MarSBoard :
* mmc0 uSDCard slot (bottom)
* mmc1 eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].max_bus_width = 4;
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
if (board_type == BOARD_IS_RIOTBOARD) {
imx_iomux_v3_setup_multiple_pads(
riotboard_usdhc3_pads,
ARRAY_SIZE(riotboard_usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
} else {
gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(7, 8), 1);
}
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].max_bus_width = 4;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[2].max_bus_width = 4;
gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(6, 8), 1);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_MXC_SPI #ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = { iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@ -513,13 +358,6 @@ int overwrite_console(void)
return 1; return 1;
} }
int board_eth_init(struct bd_info *bis)
{
setup_iomux_enet();
return cpu_eth_init(bis);
}
int board_early_init_f(void) int board_early_init_f(void)
{ {
u32 cputype = cpu_type(get_cpu_rev()); u32 cputype = cpu_type(get_cpu_rev());
@ -597,6 +435,7 @@ int board_late_init(void)
else if (board_type == BOARD_IS_RIOTBOARD) else if (board_type == BOARD_IS_RIOTBOARD)
add_board_boot_modes(marsboard_boot_modes); add_board_boot_modes(marsboard_boot_modes);
#endif #endif
setup_iomux_enet();
return 0; return 0;
} }

35
board/freescale/imx8mm_evk/boot.cmd
View File

@ -1,35 +0,0 @@
setenv bootargs console=${console} root=${mmcroot};
for boot_target in ${boot_targets};
do
if test "${boot_target}" = "mmc1" ; then
if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from SD card(mmc1);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
if test "${boot_target}" = "mmc2" ; then
if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from eMMC(mmc2);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
if test "${boot_target}" = "dhcp" ; then
if dhcp ${kernel_addr_r} ${serverip}:${image}; then
if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
echo Load image and .dtb from net(dhcp);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
done

9
board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg Normal file
View File

@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#define __ASSEMBLY__
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x7E1000

692
board/freescale/imx8mm_evk/lpddr4_timing.c
View File

@ -1,129 +1,162 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* Copyright 2019 NXP * Copyright 2018-2019 NXP
*
* Generated code from MX8M_DDR_tool
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <common.h>
#include <asm/arch/ddr.h> #include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
struct dram_cfg_param lpddr4_ddrc_cfg[] = { struct dram_cfg_param ddr_ddrc_cfg[] = {
/* Start to config, default 3200mbps */ /* Initialize DDRC registers */
{ DDRC_DBG1(0), 0x00000001 }, { 0x3d400304, 0x1 },
{ DDRC_PWRCTL(0), 0x00000001 }, { 0x3d400030, 0x1 },
{ DDRC_MSTR(0), 0xa1080020 }, { 0x3d400000, 0xa1080020 },
{ DDRC_RFSHTMG(0), 0x005b00d2 }, { 0x3d400020, 0x223 },
{ DDRC_INIT0(0), 0xC003061B }, { 0x3d400024, 0x16e3600 },
{ DDRC_INIT1(0), 0x009D0000 }, { 0x3d400064, 0x5b00d2 },
{ DDRC_INIT3(0), 0x00D4002D }, { 0x3d4000d0, 0xc00305ba },
{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, { 0x3d4000d4, 0x940000 },
{ DDRC_INIT6(0), 0x0066004a }, { 0x3d4000dc, 0xd4002d },
{ DDRC_INIT7(0), 0x0006004a }, { 0x3d4000e0, 0x310000 },
{ 0x3d4000e8, 0x66004d },
{ DDRC_DRAMTMG0(0), 0x1A201B22 }, { 0x3d4000ec, 0x16004d },
{ DDRC_DRAMTMG1(0), 0x00060633 }, { 0x3d400100, 0x191e1920 },
{ DDRC_DRAMTMG3(0), 0x00C0C000 }, { 0x3d400104, 0x60630 },
{ DDRC_DRAMTMG4(0), 0x0F04080F }, { 0x3d40010c, 0xb0b000 },
{ DDRC_DRAMTMG5(0), 0x02040C0C }, { 0x3d400110, 0xe04080e },
{ DDRC_DRAMTMG6(0), 0x01010007 }, { 0x3d400114, 0x2040c0c },
{ DDRC_DRAMTMG7(0), 0x00000401 }, { 0x3d400118, 0x1010007 },
{ DDRC_DRAMTMG12(0), 0x00020600 }, { 0x3d40011c, 0x401 },
{ DDRC_DRAMTMG13(0), 0x0C100002 }, { 0x3d400130, 0x20600 },
{ DDRC_DRAMTMG14(0), 0x000000E6 }, { 0x3d400134, 0xc100002 },
{ DDRC_DRAMTMG17(0), 0x00A00050 }, { 0x3d400138, 0xd8 },
{ 0x3d400144, 0x96004b },
{ DDRC_ZQCTL0(0), 0x03200018 }, { 0x3d400180, 0x2ee0017 },
{ DDRC_ZQCTL1(0), 0x028061A8 }, { 0x3d400184, 0x2605b8e },
{ DDRC_ZQCTL2(0), 0x00000000 }, { 0x3d400188, 0x0 },
{ 0x3d400190, 0x497820a },
{ DDRC_DFITMG0(0), 0x0497820A }, { 0x3d400194, 0x80303 },
{ DDRC_DFITMG2(0), 0x0000170A }, { 0x3d4001b4, 0x170a },
{ DDRC_DRAMTMG2(0), 0x070E171a }, { 0x3d4001a0, 0xe0400018 },
{ DDRC_DBICTL(0), 0x00000001 }, { 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ DDRC_DFITMG1(0), 0x00080303 }, { 0x3d4001b0, 0x11 },
{ DDRC_DFIUPD0(0), 0xE0400018 }, { 0x3d4001c0, 0x1 },
{ DDRC_DFIUPD1(0), 0x00DF00E4 }, { 0x3d4001c4, 0x0 },
{ DDRC_DFIUPD2(0), 0x80000000 }, { 0x3d4000f4, 0xc99 },
{ DDRC_DFIMISC(0), 0x00000011 }, { 0x3d400108, 0x70e1617 },
{ 0x3d400200, 0x1f },
{ DDRC_DFIPHYMSTR(0), 0x00000000 }, { 0x3d40020c, 0x0 },
{ DDRC_RANKCTL(0), 0x00000c99 }, { 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
/* address mapping */ { 0x3d400214, 0x7070707 },
{ DDRC_ADDRMAP0(0), 0x0000001f }, { 0x3d400218, 0x7070707 },
{ DDRC_ADDRMAP1(0), 0x00080808 },
{ DDRC_ADDRMAP2(0), 0x00000000 },
{ DDRC_ADDRMAP3(0), 0x00000000 },
{ DDRC_ADDRMAP4(0), 0x00001f1f },
{ DDRC_ADDRMAP5(0), 0x07070707 },
{ DDRC_ADDRMAP6(0), 0x07070707 },
{ DDRC_ADDRMAP7(0), 0x00000f0f },
/* performance setting */ /* performance setting */
{ DDRC_SCHED(0), 0x29001701 }, { 0x3d400250, 0x29001701 },
{ DDRC_SCHED1(0), 0x0000002c }, { 0x3d400254, 0x2c },
{ DDRC_PERFHPR1(0), 0x04000030 }, { 0x3d40025c, 0x4000030 },
{ DDRC_PERFLPR1(0), 0x900093e7 }, { 0x3d400264, 0x900093e7 },
{ DDRC_PERFWR1(0), 0x20005574 }, { 0x3d40026c, 0x2005574 },
{ DDRC_PCCFG(0), 0x00000111 }, { 0x3d400400, 0x111 },
{ DDRC_PCFGW_0(0), 0x000072ff }, { 0x3d400408, 0x72ff },
{ DDRC_PCFGQOS0_0(0), 0x02100e07 }, { 0x3d400494, 0x2100e07 },
{ DDRC_PCFGQOS1_0(0), 0x00620096 }, { 0x3d400498, 0x620096 },
{ DDRC_PCFGWQOS0_0(0), 0x01100e07 }, { 0x3d40049c, 0x1100e07 },
{ DDRC_PCFGWQOS1_0(0), 0x00c8012c }, { 0x3d4004a0, 0xc8012c },
/* frequency P1&P2 */ /* P1: 400mts */
/* Frequency 1: 400mbps */ { 0x3d402020, 0x21 },
{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, { 0x3d402024, 0x30d400 },
{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, { 0x3d402050, 0x20d040 },
{ DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, { 0x3d402064, 0xc001c },
{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, { 0x3d4020dc, 0x840000 },
{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, { 0x3d4020e0, 0x310000 },
{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, { 0x3d4020e8, 0x66004d },
{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, { 0x3d4020ec, 0x16004d },
{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, { 0x3d402100, 0xa040305 },
{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, { 0x3d402104, 0x30407 },
{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, { 0x3d402108, 0x203060b },
{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, { 0x3d40210c, 0x505000 },
{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, { 0x3d402110, 0x2040202 },
{ DDRC_FREQ1_DFITMG0(0), 0x03818200 }, { 0x3d402114, 0x2030202 },
{ DDRC_FREQ1_DFITMG2(0), 0x00000000 }, { 0x3d402118, 0x1010004 },
{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, { 0x3d40211c, 0x301 },
{ DDRC_FREQ1_INIT3(0), 0x00840000 }, { 0x3d402130, 0x20300 },
{ DDRC_FREQ1_INIT4(0), 0x00310000 }, { 0x3d402134, 0xa100002 },
{ DDRC_FREQ1_INIT6(0), 0x0066004a }, { 0x3d402138, 0x1d },
{ DDRC_FREQ1_INIT7(0), 0x0006004a }, { 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
/* Frequency 2: 100mbps */ /* p2: 100mts */
{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, { 0x3d403020, 0x21 },
{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, { 0x3d403024, 0xc3500 },
{ DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, { 0x3d403050, 0x20d040 },
{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, { 0x3d403064, 0x30007 },
{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, { 0x3d4030dc, 0x840000 },
{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, { 0x3d4030e0, 0x310000 },
{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, { 0x3d4030e8, 0x66004d },
{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, { 0x3d4030ec, 0x16004d },
{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, { 0x3d403100, 0xa010102 },
{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, { 0x3d403104, 0x30404 },
{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, { 0x3d403108, 0x203060b },
{ DDRC_FREQ2_DFITMG0(0), 0x03818200 }, { 0x3d40310c, 0x505000 },
{ DDRC_FREQ2_DFITMG2(0), 0x00000000 }, { 0x3d403110, 0x2040202 },
{ DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, { 0x3d403114, 0x2030202 },
{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, { 0x3d403118, 0x1010004 },
{ DDRC_FREQ2_INIT3(0), 0x00840000 }, { 0x3d40311c, 0x301 },
{ DDRC_FREQ2_INIT4(0), 0x00310008 }, { 0x3d403130, 0x20300 },
{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, { 0x3d403134, 0xa100002 },
{ DDRC_FREQ2_INIT6(0), 0x0066004a }, { 0x3d403138, 0x8 },
{ DDRC_FREQ2_INIT7(0), 0x0006004a }, { 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
/* boot start point */ /* default boot point */
{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 { 0x3d400028, 0x0 },
}; };
/* PHY Initialize Configuration */ /* PHY Initialize Configuration */
struct dram_cfg_param lpddr4_ddrphy_cfg[] = { struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
{ 0x100a2, 0x2 },
{ 0x100a3, 0x3 },
{ 0x100a4, 0x4 },
{ 0x100a5, 0x5 },
{ 0x100a6, 0x6 },
{ 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
{ 0x110a2, 0x3 },
{ 0x110a3, 0x4 },
{ 0x110a4, 0x5 },
{ 0x110a5, 0x2 },
{ 0x110a6, 0x7 },
{ 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
{ 0x120a2, 0x3 },
{ 0x120a3, 0x2 },
{ 0x120a4, 0x5 },
{ 0x120a5, 0x4 },
{ 0x120a6, 0x7 },
{ 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
{ 0x130a2, 0x2 },
{ 0x130a3, 0x3 },
{ 0x130a4, 0x4 },
{ 0x130a5, 0x5 },
{ 0x130a6, 0x6 },
{ 0x130a7, 0x7 },
{ 0x1005f, 0x1ff }, { 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff }, { 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff }, { 0x1105f, 0x1ff },
@ -132,7 +165,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x1215f, 0x1ff }, { 0x1215f, 0x1ff },
{ 0x1305f, 0x1ff }, { 0x1305f, 0x1ff },
{ 0x1315f, 0x1ff }, { 0x1315f, 0x1ff },
{ 0x11005f, 0x1ff }, { 0x11005f, 0x1ff },
{ 0x11015f, 0x1ff }, { 0x11015f, 0x1ff },
{ 0x11105f, 0x1ff }, { 0x11105f, 0x1ff },
@ -141,7 +173,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x11215f, 0x1ff }, { 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff }, { 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff }, { 0x11315f, 0x1ff },
{ 0x21005f, 0x1ff }, { 0x21005f, 0x1ff },
{ 0x21015f, 0x1ff }, { 0x21015f, 0x1ff },
{ 0x21105f, 0x1ff }, { 0x21105f, 0x1ff },
@ -150,7 +181,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x21215f, 0x1ff }, { 0x21215f, 0x1ff },
{ 0x21305f, 0x1ff }, { 0x21305f, 0x1ff },
{ 0x21315f, 0x1ff }, { 0x21315f, 0x1ff },
{ 0x55, 0x1ff }, { 0x55, 0x1ff },
{ 0x1055, 0x1ff }, { 0x1055, 0x1ff },
{ 0x2055, 0x1ff }, { 0x2055, 0x1ff },
@ -161,32 +191,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x7055, 0x1ff }, { 0x7055, 0x1ff },
{ 0x8055, 0x1ff }, { 0x8055, 0x1ff },
{ 0x9055, 0x1ff }, { 0x9055, 0x1ff },
{ 0x200c5, 0x19 }, { 0x200c5, 0x19 },
{ 0x1200c5, 0x7 }, { 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 }, { 0x2200c5, 0x7 },
{ 0x2002e, 0x2 }, { 0x2002e, 0x2 },
{ 0x12002e, 0x2 }, { 0x12002e, 0x2 },
{ 0x22002e, 0x2 }, { 0x22002e, 0x2 },
{ 0x90204, 0x0 }, { 0x90204, 0x0 },
{ 0x190204, 0x0 }, { 0x190204, 0x0 },
{ 0x290204, 0x0 }, { 0x290204, 0x0 },
{ 0x20024, 0x1ab },
{ 0x20024, 0xab },
{ 0x2003a, 0x0 }, { 0x2003a, 0x0 },
{ 0x120024, 0x1ab },
{ 0x120024, 0xab },
{ 0x2003a, 0x0 }, { 0x2003a, 0x0 },
{ 0x220024, 0x1ab },
{ 0x220024, 0xab },
{ 0x2003a, 0x0 }, { 0x2003a, 0x0 },
{ 0x20056, 0x3 }, { 0x20056, 0x3 },
{ 0x120056, 0xa }, { 0x120056, 0xa },
{ 0x220056, 0xa }, { 0x220056, 0xa },
{ 0x1004d, 0xe00 }, { 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 }, { 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 }, { 0x1104d, 0xe00 },
@ -195,7 +217,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x1214d, 0xe00 }, { 0x1214d, 0xe00 },
{ 0x1304d, 0xe00 }, { 0x1304d, 0xe00 },
{ 0x1314d, 0xe00 }, { 0x1314d, 0xe00 },
{ 0x11004d, 0xe00 }, { 0x11004d, 0xe00 },
{ 0x11014d, 0xe00 }, { 0x11014d, 0xe00 },
{ 0x11104d, 0xe00 }, { 0x11104d, 0xe00 },
@ -204,7 +225,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x11214d, 0xe00 }, { 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 }, { 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 }, { 0x11314d, 0xe00 },
{ 0x21004d, 0xe00 }, { 0x21004d, 0xe00 },
{ 0x21014d, 0xe00 }, { 0x21014d, 0xe00 },
{ 0x21104d, 0xe00 }, { 0x21104d, 0xe00 },
@ -213,34 +233,30 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x21214d, 0xe00 }, { 0x21214d, 0xe00 },
{ 0x21304d, 0xe00 }, { 0x21304d, 0xe00 },
{ 0x21314d, 0xe00 }, { 0x21314d, 0xe00 },
{ 0x10049, 0xeba },
{ 0x10049, 0xfbe }, { 0x10149, 0xeba },
{ 0x10149, 0xfbe }, { 0x11049, 0xeba },
{ 0x11049, 0xfbe }, { 0x11149, 0xeba },
{ 0x11149, 0xfbe }, { 0x12049, 0xeba },
{ 0x12049, 0xfbe }, { 0x12149, 0xeba },
{ 0x12149, 0xfbe }, { 0x13049, 0xeba },
{ 0x13049, 0xfbe }, { 0x13149, 0xeba },
{ 0x13149, 0xfbe }, { 0x110049, 0xeba },
{ 0x110149, 0xeba },
{ 0x110049, 0xfbe }, { 0x111049, 0xeba },
{ 0x110149, 0xfbe }, { 0x111149, 0xeba },
{ 0x111049, 0xfbe }, { 0x112049, 0xeba },
{ 0x111149, 0xfbe }, { 0x112149, 0xeba },
{ 0x112049, 0xfbe }, { 0x113049, 0xeba },
{ 0x112149, 0xfbe }, { 0x113149, 0xeba },
{ 0x113049, 0xfbe }, { 0x210049, 0xeba },
{ 0x113149, 0xfbe }, { 0x210149, 0xeba },
{ 0x211049, 0xeba },
{ 0x210049, 0xfbe }, { 0x211149, 0xeba },
{ 0x210149, 0xfbe }, { 0x212049, 0xeba },
{ 0x211049, 0xfbe }, { 0x212149, 0xeba },
{ 0x211149, 0xfbe }, { 0x213049, 0xeba },
{ 0x212049, 0xfbe }, { 0x213149, 0xeba },
{ 0x212149, 0xfbe },
{ 0x213049, 0xfbe },
{ 0x213149, 0xfbe },
{ 0x43, 0x63 }, { 0x43, 0x63 },
{ 0x1043, 0x63 }, { 0x1043, 0x63 },
{ 0x2043, 0x63 }, { 0x2043, 0x63 },
@ -251,7 +267,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x7043, 0x63 }, { 0x7043, 0x63 },
{ 0x8043, 0x63 }, { 0x8043, 0x63 },
{ 0x9043, 0x63 }, { 0x9043, 0x63 },
{ 0x20018, 0x3 }, { 0x20018, 0x3 },
{ 0x20075, 0x4 }, { 0x20075, 0x4 },
{ 0x20050, 0x0 }, { 0x20050, 0x0 },
@ -259,8 +274,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x120008, 0x64 }, { 0x120008, 0x64 },
{ 0x220008, 0x19 }, { 0x220008, 0x19 },
{ 0x20088, 0x9 }, { 0x20088, 0x9 },
{ 0x200b2, 0xdc },
{ 0x200b2, 0x1d4 },
{ 0x10043, 0x5a1 }, { 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 }, { 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 }, { 0x11043, 0x5a1 },
@ -269,7 +283,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x12143, 0x5a1 }, { 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 }, { 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 }, { 0x13143, 0x5a1 },
{ 0x1200b2, 0xdc }, { 0x1200b2, 0xdc },
{ 0x110043, 0x5a1 }, { 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 }, { 0x110143, 0x5a1 },
@ -279,7 +292,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x112143, 0x5a1 }, { 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 }, { 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 }, { 0x113143, 0x5a1 },
{ 0x2200b2, 0xdc }, { 0x2200b2, 0xdc },
{ 0x210043, 0x5a1 }, { 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 }, { 0x210143, 0x5a1 },
@ -289,15 +301,12 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x212143, 0x5a1 }, { 0x212143, 0x5a1 },
{ 0x213043, 0x5a1 }, { 0x213043, 0x5a1 },
{ 0x213143, 0x5a1 }, { 0x213143, 0x5a1 },
{ 0x200fa, 0x1 }, { 0x200fa, 0x1 },
{ 0x1200fa, 0x1 }, { 0x1200fa, 0x1 },
{ 0x2200fa, 0x1 }, { 0x2200fa, 0x1 },
{ 0x20019, 0x1 }, { 0x20019, 0x1 },
{ 0x120019, 0x1 }, { 0x120019, 0x1 },
{ 0x220019, 0x1 }, { 0x220019, 0x1 },
{ 0x200f0, 0x660 }, { 0x200f0, 0x660 },
{ 0x200f1, 0x0 }, { 0x200f1, 0x0 },
{ 0x200f2, 0x4444 }, { 0x200f2, 0x4444 },
@ -306,21 +315,20 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x200f5, 0x0 }, { 0x200f5, 0x0 },
{ 0x200f6, 0x0 }, { 0x200f6, 0x0 },
{ 0x200f7, 0xf000 }, { 0x200f7, 0xf000 },
{ 0x20025, 0x0 }, { 0x20025, 0x0 },
{ 0x2002d, LPDDR4_PHY_DMIPinPresent }, { 0x2002d, 0x0 },
{ 0x12002d, LPDDR4_PHY_DMIPinPresent }, { 0x12002d, 0x0 },
{ 0x22002d, LPDDR4_PHY_DMIPinPresent }, { 0x22002d, 0x0 },
{ 0x200c7, 0x21 }, { 0x200c7, 0x21 },
{ 0x200ca, 0x24 },
{ 0x1200c7, 0x21 }, { 0x1200c7, 0x21 },
{ 0x1200ca, 0x24 },
{ 0x2200c7, 0x21 }, { 0x2200c7, 0x21 },
{ 0x200ca, 0x24 },
{ 0x1200ca, 0x24 },
{ 0x2200ca, 0x24 }, { 0x2200ca, 0x24 },
}; };
/* ddr phy trained csr */ /* ddr phy trained csr */
struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 }, { 0x200b2, 0x0 },
{ 0x1200b2, 0x0 }, { 0x1200b2, 0x0 },
{ 0x2200b2, 0x0 }, { 0x2200b2, 0x0 },
@ -1041,309 +1049,164 @@ struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
{ 0x13730, 0x0 }, { 0x13730, 0x0 },
{ 0x13830, 0x0 }, { 0x13830, 0x0 },
}; };
/* P0 message block paremeter for training firmware */ /* P0 message block paremeter for training firmware */
struct dram_cfg_param lpddr4_fsp0_cfg[] = { struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xbb8 }, { 0x54003, 0xbb8 },
{ 0x54004, 0x2 }, { 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt { 0x54005, 0x2228 },
{ 0x54006, LPDDR4_PHY_VREF_VALUE }, { 0x54006, 0x11 },
{ 0x54007, 0x0 },
{ 0x54008, 0x131f }, { 0x54008, 0x131f },
{ 0x54009, 0xc8 }, { 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 }, { 0x5400b, 0x2 },
{ 0x5400c, 0x0 }, { 0x54012, 0x110 },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x2dd4 }, { 0x54019, 0x2dd4 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 }, { 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 }, { 0x5401c, 0x4d00 },
{ 0x5401d, 0x0 }, { 0x5401e, 0x16 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x2dd4 }, { 0x5401f, 0x2dd4 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x54020, 0x31 },
{ 0x54021, 0x4d66 }, { 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 }, { 0x54022, 0x4d00 },
{ 0x54023, 0x0 }, { 0x54024, 0x16 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, LPDDR4_CS }, { 0x5402c, 0x1 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 }, { 0x54032, 0xd400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, { 0x54033, 0x312d },
{ 0x54034, 0x6600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x84d }, { 0x54035, 0x4d },
{ 0x54036, 0x4d }, { 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, { 0x54037, 0x1600 },
{ 0x54038, 0xd400 }, { 0x54038, 0xd400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, { 0x54039, 0x312d },
{ 0x5403a, 0x6600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x84d }, { 0x5403b, 0x4d },
{ 0x5403c, 0x4d }, { 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, { 0x5403d, 0x1600 },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P1 message block paremeter for training firmware */ /* P1 message block paremeter for training firmware */
struct dram_cfg_param lpddr4_fsp1_cfg[] = { struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x101 }, { 0x54002, 0x101 },
{ 0x54003, 0x190 }, { 0x54003, 0x190 },
{ 0x54004, 0x2 }, { 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ { 0x54005, 0x2228 },
{ 0x54006, LPDDR4_PHY_VREF_VALUE }, { 0x54006, 0x11 },
{ 0x54007, 0x0 },
{ 0x54008, 0x121f }, { 0x54008, 0x121f },
{ 0x54009, 0xc8 }, { 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 }, { 0x5400b, 0x2 },
{ 0x5400c, 0x0 }, { 0x54012, 0x110 },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x84 }, { 0x54019, 0x84 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 }, { 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 }, { 0x5401c, 0x4d00 },
{ 0x5401d, 0x0 }, { 0x5401e, 0x16 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x84 }, { 0x5401f, 0x84 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x54020, 0x31 },
{ 0x54021, 0x4d66 }, { 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 }, { 0x54022, 0x4d00 },
{ 0x54023, 0x0 }, { 0x54024, 0x16 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, LPDDR4_CS }, { 0x5402c, 0x1 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 }, { 0x54032, 0x8400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, { 0x54033, 0x3100 },
{ 0x54034, 0x6600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x84d }, { 0x54035, 0x4d },
{ 0x54036, 0x4d }, { 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, { 0x54037, 0x1600 },
{ 0x54038, 0x8400 }, { 0x54038, 0x8400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, { 0x54039, 0x3100 },
{ 0x5403a, 0x6600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x84d }, { 0x5403b, 0x4d },
{ 0x5403c, 0x4d }, { 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, { 0x5403d, 0x1600 },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P1 message block paremeter for training firmware */ /* P2 message block paremeter for training firmware */
struct dram_cfg_param lpddr4_fsp2_cfg[] = { struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x102 }, { 0x54002, 0x102 },
{ 0x54003, 0x64 }, { 0x54003, 0x64 },
{ 0x54004, 0x2 }, { 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt { 0x54005, 0x2228 },
{ 0x54006, LPDDR4_PHY_VREF_VALUE }, { 0x54006, 0x11 },
{ 0x54007, 0x0 },
{ 0x54008, 0x121f }, { 0x54008, 0x121f },
{ 0x54009, 0xc8 }, { 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 }, { 0x5400b, 0x2 },
{ 0x5400c, 0x0 }, { 0x54012, 0x110 },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x84 }, { 0x54019, 0x84 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 }, { 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 }, { 0x5401c, 0x4d00 },
{ 0x5401d, 0x0 }, { 0x5401e, 0x16 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x84 }, { 0x5401f, 0x84 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x54020, 0x31 },
{ 0x54021, 0x4d66 }, { 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 }, { 0x54022, 0x4d00 },
{ 0x54023, 0x0 }, { 0x54024, 0x16 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, LPDDR4_CS }, { 0x5402c, 0x1 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 }, { 0x54032, 0x8400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, { 0x54033, 0x3100 },
{ 0x54034, 0x6600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x84d }, { 0x54035, 0x4d },
{ 0x54036, 0x4d }, { 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, { 0x54037, 0x1600 },
{ 0x54038, 0x8400 }, { 0x54038, 0x8400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, { 0x54039, 0x3100 },
{ 0x5403a, 0x6600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x84d }, { 0x5403b, 0x4d },
{ 0x5403c, 0x4d }, { 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, { 0x5403d, 0x1600 },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P0 2D message block paremeter for training firmware */ /* P0 2D message block paremeter for training firmware */
struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xbb8 }, { 0x54003, 0xbb8 },
{ 0x54004, 0x2 }, { 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt { 0x54005, 0x2228 },
{ 0x54006, LPDDR4_PHY_VREF_VALUE }, { 0x54006, 0x11 },
{ 0x54007, 0x0 },
{ 0x54008, 0x61 }, { 0x54008, 0x61 },
{ 0x54009, 0xc8 }, { 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 }, { 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x100 }, { 0x5400f, 0x100 },
{ 0x54010, 0x1f7f }, { 0x54010, 0x1f7f },
{ 0x54011, 0x0 }, { 0x54012, 0x110 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x2dd4 }, { 0x54019, 0x2dd4 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 }, { 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 }, { 0x5401c, 0x4d00 },
{ 0x5401d, 0x0 }, { 0x5401e, 0x16 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x2dd4 }, { 0x5401f, 0x2dd4 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, { 0x54020, 0x31 },
{ 0x54021, 0x4d66 }, { 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 }, { 0x54022, 0x4d00 },
{ 0x54023, 0x0 }, { 0x54024, 0x16 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, LPDDR4_CS }, { 0x5402c, 0x1 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 }, { 0x54032, 0xd400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, { 0x54033, 0x312d },
{ 0x54034, 0x6600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x84d }, { 0x54035, 0x4d },
{ 0x54036, 0x4d }, { 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, { 0x54037, 0x1600 },
{ 0x54038, 0xd400 }, { 0x54038, 0xd400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, { 0x54039, 0x312d },
{ 0x5403a, 0x6600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x84d }, { 0x5403b, 0x4d },
{ 0x5403c, 0x4d }, { 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, { 0x5403d, 0x1600 },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* DRAM PHY init engine image */ /* DRAM PHY init engine image */
struct dram_cfg_param lpddr4_phy_pie[] = { struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
{ 0x90000, 0x10 }, { 0x90000, 0x10 },
{ 0x90001, 0x400 }, { 0x90001, 0x400 },
@ -1854,6 +1717,10 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
{ 0x90013, 0x6152 }, { 0x90013, 0x6152 },
{ 0x20010, 0x5a }, { 0x20010, 0x5a },
{ 0x20011, 0x3 }, { 0x20011, 0x3 },
{ 0x120010, 0x5a },
{ 0x120011, 0x3 },
{ 0x220010, 0x5a },
{ 0x220011, 0x3 },
{ 0x40080, 0xe0 }, { 0x40080, 0xe0 },
{ 0x40081, 0x12 }, { 0x40081, 0x12 },
{ 0x40082, 0xe0 }, { 0x40082, 0xe0 },
@ -1931,50 +1798,51 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
{ 0x138b4, 0x1 }, { 0x138b4, 0x1 },
{ 0x2003a, 0x2 }, { 0x2003a, 0x2 },
{ 0xc0080, 0x2 }, { 0xc0080, 0x2 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 }
}; };
struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{ {
/* P0 3000mts 1D */ /* P0 3000mts 1D */
.drate = 3000, .drate = 3000,
.fw_type = FW_1D_IMAGE, .fw_type = FW_1D_IMAGE,
.fsp_cfg = lpddr4_fsp0_cfg, .fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
/* P0 3000mts 2D */
.drate = 3000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = lpddr4_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
}, },
{ {
/* P1 400mts 1D */ /* P1 400mts 1D */
.drate = 400, .drate = 400,
.fw_type = FW_1D_IMAGE, .fw_type = FW_1D_IMAGE,
.fsp_cfg = lpddr4_fsp1_cfg, .fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
}, },
{ {
/* P1 100mts 1D */ /* P2 100mts 1D */
.drate = 100, .drate = 100,
.fw_type = FW_1D_IMAGE, .fw_type = FW_1D_IMAGE,
.fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg = ddr_fsp2_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
/* P0 3000mts 2D */
.drate = 3000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
}, },
}; };
/* lpddr4 timing config params on EVK board */ /* ddr timing config params */
struct dram_timing_info dram_timing = { struct dram_timing_info dram_timing = {
.ddrc_cfg = lpddr4_ddrc_cfg, .ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = lpddr4_ddrphy_cfg, .ddrphy_cfg = ddr_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
.fsp_msg = lpddr4_dram_fsp_msg, .fsp_msg = ddr_dram_fsp_msg,
.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = lpddr4_phy_pie, .ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
}; };

33
board/freescale/imx8mm_evk/spl.c
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@ -26,7 +26,7 @@
#include <dm/device-internal.h> #include <dm/device-internal.h>
#include <power/pmic.h> #include <power/pmic.h>
#include <power/bd71837.h> #include <power/pca9450.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -94,7 +94,7 @@ static int power_init_board(void)
struct udevice *dev; struct udevice *dev;
int ret; int ret;
ret = pmic_get("pmic@4b", &dev); ret = pmic_get("pca9450@25", &dev);
if (ret == -ENODEV) { if (ret == -ENODEV) {
puts("No pmic\n"); puts("No pmic\n");
return 0; return 0;
@ -102,25 +102,26 @@ static int power_init_board(void)
if (ret != 0) if (ret != 0)
return ret; return ret;
/* decrease RESET key long push time from the default 10s to 10ms */ /* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* unlock the PMIC regs */ /* Buck 1 DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
/* increase VDD_SOC to typical value 0.85v before first DRAM access */ /* Set DVS1 to 0.8v for suspend */
pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */ /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
#ifndef CONFIG_IMX8M_LPDDR4 /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
#endif
/* lock the PMIC regs */ /* set VDD_SNVS_0V8 from default 0.85V */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0; return 0;
} }

6
board/freescale/imx8mn_evk/Kconfig
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@ -1,4 +1,4 @@
if TARGET_IMX8MN_DDR4_EVK if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK
config SYS_BOARD config SYS_BOARD
default "imx8mn_evk" default "imx8mn_evk"
@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "imx8mn_evk" default "imx8mn_evk"
config IMX8MN_LOW_DRIVE_MODE
bool "Enable the low drive mode of iMX8MN on EVK board"
default n
source "board/freescale/common/Kconfig" source "board/freescale/common/Kconfig"
endif endif

3
board/freescale/imx8mn_evk/MAINTAINERS
View File

@ -1,6 +1,7 @@
i.MX8MM EVK BOARD i.MX8MN EVK BOARD
M: Peng Fan <peng.fan@nxp.com> M: Peng Fan <peng.fan@nxp.com>
S: Maintained S: Maintained
F: board/freescale/imx8mn_evk/ F: board/freescale/imx8mn_evk/
F: include/configs/imx8mn_evk.h F: include/configs/imx8mn_evk.h
F: configs/imx8mn_ddr4_evk_defconfig F: configs/imx8mn_ddr4_evk_defconfig
F: configs/imx8mn_evk_defconfig

6
board/freescale/imx8mn_evk/Makefile
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@ -8,5 +8,11 @@ obj-y += imx8mn_evk.o
ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_BUILD
obj-y += spl.o obj-y += spl.o
ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o
else
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
endif endif
endif

1057
board/freescale/imx8mn_evk/ddr4_timing.c
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1057
board/freescale/imx8mn_evk/ddr4_timing_ld.c Normal file
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10
board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg Normal file
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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#define __ASSEMBLY__
ROM_VERSION v2
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x912000

1587
board/freescale/imx8mn_evk/lpddr4_timing.c Normal file
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1440
board/freescale/imx8mn_evk/lpddr4_timing_ld.c Normal file
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