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ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit

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Now that bit 29 is the USB PHY reset bit, update the Kilauea port
to remove the USB PHY reset after powerup. The CPLD will keep the
USB PHY in reset (active low) until the bit is set to 1 in
board_early_init_f().

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-01-14 10:05:05 +01:00
parent f43ad53908
commit a0dd99d51e
1 changed files with 7 additions and 7 deletions
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14
board/amcc/kilauea/kilauea.c
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@ -192,13 +192,6 @@ int board_early_init_f (void)
*/ */
mtsdr(SDR0_SRST, 0); mtsdr(SDR0_SRST, 0);
/*
* Configure FPGA register with PCIe reset
*/
out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
mdelay(50);
out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
/* Configure 405EX for NAND usage */ /* Configure 405EX for NAND usage */
val = SDR0_CUST0_MUX_NDFC_SEL | val = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_ENABLE |
@ -214,6 +207,13 @@ int board_early_init_f (void)
val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
mtsdr(SDR0_PFC1, val); mtsdr(SDR0_PFC1, val);
/*
* Configure FPGA register with PCIe reset
*/
out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
mdelay(50);
out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
return 0; return 0;
} }