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Blackfin: bf533-stamp: bump up default clocks
Since the hardware can handle it, bump the default clocks from 80mhz SCLK and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -30,7 +30,7 @@
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 36
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#define CONFIG_VCO_MULT 45
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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