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armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Mingkai Hu
York Sun
parent
23e1acaf4b
commit
9f3183d2d6
@ -15,6 +15,6 @@ obj-y += cache.o
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obj-y += tlb.o
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obj-y += transition.o
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obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
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obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
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obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
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obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
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21
arch/arm/cpu/armv8/fsl-layerscape/Makefile
Normal file
21
arch/arm/cpu/armv8/fsl-layerscape/Makefile
Normal file
@ -0,0 +1,21 @@
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#
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# Copyright 2014-2015, Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SPL) += spl.o
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ifneq ($(CONFIG_FSL_LSCH3),)
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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endif
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ifneq ($(CONFIG_LS2085A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
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endif
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@ -1,5 +1,5 @@
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#
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# Copyright 2014 Freescale Semiconductor
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# Copyright 2014-2015 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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@ -1,5 +1,5 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -10,34 +10,28 @@
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-fsl-lsch3/soc.h>
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#include <asm/arch-fsl-lsch3/immap_lsch3.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/speed.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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#include <fm_eth.h>
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#include <fsl_debug_server.h>
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#include <fsl-mc/fsl_mc.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include "cpu.h"
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#include "mp.h"
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#include "speed.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct cpu_type cpu_type_list[] = {
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#ifdef CONFIG_LS2085A
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CPU_TYPE_ENTRY(LS2085, LS2085, 8),
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CPU_TYPE_ENTRY(LS2080, LS2080, 8),
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CPU_TYPE_ENTRY(LS2045, LS2045, 4),
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#endif
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};
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void cpu_name(char *name)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int i, svr, ver;
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svr = in_le32(&gur->svr);
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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@ -54,146 +48,6 @@ void cpu_name(char *name)
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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#define SECTION_SHIFT_L0 39UL
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#define SECTION_SHIFT_L1 30UL
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#define SECTION_SHIFT_L2 21UL
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#define BLOCK_SIZE_L0 0x8000000000
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#define BLOCK_SIZE_L1 0x40000000
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#define BLOCK_SIZE_L2 0x200000
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#define NUM_OF_ENTRY 512
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#define TCR_EL2_PS_40BIT (2 << 16)
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#define LSCH3_VA_BITS (40)
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#define LSCH3_TCR (TCR_TG0_4K | \
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_NON | \
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TCR_ORGN_NC | \
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TCR_IRGN_NC | \
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TCR_T0SZ(LSCH3_VA_BITS))
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#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_OUTER | \
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TCR_ORGN_WBWA | \
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TCR_IRGN_WBWA | \
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TCR_T0SZ(LSCH3_VA_BITS))
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#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
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#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
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#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
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#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
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#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
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#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
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#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
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#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
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#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
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#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
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#define CONFIG_SYS_FSL_NI_BASE 0x810000000
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#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
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#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
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#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
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struct sys_mmu_table {
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u64 virt_addr;
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u64 phys_addr;
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u64 size;
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u64 memory_type;
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u64 share;
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};
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static const struct sys_mmu_table lsch3_early_mmu_table[] = {
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
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/* For IFC Region #1, only the first 4MB is cache-enabled */
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{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
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CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
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CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
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CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
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MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
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CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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};
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static const struct sys_mmu_table lsch3_final_mmu_table[] = {
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
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CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
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CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
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CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
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CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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/* For QBMAN portal, only the first 64MB is cache-enabled */
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{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
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CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
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CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
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CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
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MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
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CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
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CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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#ifdef CONFIG_LS2085A
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
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CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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#endif
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
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CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
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CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
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CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
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};
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struct table_info {
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u64 *ptr;
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u64 table_base;
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u64 entry_size;
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};
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/*
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* Set the block entries according to the information of the table.
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*/
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@ -311,6 +165,7 @@ static inline void early_mmu_setup(void)
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u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
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u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
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u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
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struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
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/* Invalidate all table entries */
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@ -320,19 +175,21 @@ static inline void early_mmu_setup(void)
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set_pgtable_table(level0_table, 0, level1_table0);
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set_pgtable_table(level0_table, 1, level1_table1);
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set_pgtable_table(level1_table0, 0, level2_table0);
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#ifdef CONFIG_FSL_LSCH3
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set_pgtable_table(level1_table0,
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CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
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level2_table1);
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#endif
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/* Find the table and fill in the block entries */
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for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
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if (find_table(&lsch3_early_mmu_table[i],
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for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
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if (find_table(&early_mmu_table[i],
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&table, level0_table) == 0) {
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/*
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* If find_table() returns error, it cannot be dealt
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* with here. Breakpoint can be added for debugging.
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*/
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set_block_entry(&lsch3_early_mmu_table[i], &table);
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set_block_entry(&early_mmu_table[i], &table);
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/*
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* If set_block_entry() returns error, it cannot be
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* dealt with here too.
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@ -341,7 +198,9 @@ static inline void early_mmu_setup(void)
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}
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el = current_el();
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set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
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set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
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MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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@ -353,6 +212,8 @@ static inline void early_mmu_setup(void)
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* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
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* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
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* Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
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*
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* For LSCH3:
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* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
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*/
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static inline void final_mmu_setup(void)
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@ -362,7 +223,9 @@ static inline void final_mmu_setup(void)
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u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
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u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
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u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
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#ifdef CONFIG_FSL_LSCH3
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u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
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#endif
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struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
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/* Invalidate all table entries */
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@ -372,23 +235,25 @@ static inline void final_mmu_setup(void)
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set_pgtable_table(level0_table, 0, level1_table0);
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set_pgtable_table(level0_table, 1, level1_table1);
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set_pgtable_table(level1_table0, 0, level2_table0);
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#ifdef CONFIG_FSL_LSCH3
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set_pgtable_table(level1_table0,
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CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
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level2_table1);
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#endif
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/* Find the table and fill in the block entries */
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for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
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if (find_table(&lsch3_final_mmu_table[i],
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for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
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if (find_table(&final_mmu_table[i],
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&table, level0_table) == 0) {
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if (set_block_entry(&lsch3_final_mmu_table[i],
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if (set_block_entry(&final_mmu_table[i],
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&table) != 0) {
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printf("MMU error: could not set block entry for %p\n",
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&lsch3_final_mmu_table[i]);
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&final_mmu_table[i]);
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}
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} else {
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printf("MMU error: could not find the table for %p\n",
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&lsch3_final_mmu_table[i]);
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&final_mmu_table[i]);
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}
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}
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@ -398,7 +263,8 @@ static inline void final_mmu_setup(void)
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/* point TTBR to the new table */
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el = current_el();
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set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
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set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
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MEMORY_ATTRIBUTES);
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/*
|
||||
* MMU is already enabled, just need to invalidate TLB to load the
|
||||
@ -434,8 +300,9 @@ static inline u32 initiator_type(u32 cluster, int init_id)
|
||||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
|
||||
u32 type = in_le32(&gur->tp_ityp[idx]);
|
||||
u32 type = 0;
|
||||
|
||||
type = gur_in32(&gur->tp_ityp[idx]);
|
||||
if (type & TP_ITYP_AV)
|
||||
return type;
|
||||
|
||||
@ -450,7 +317,8 @@ u32 cpu_mask(void)
|
||||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
type = initiator_type(cluster, j);
|
||||
if (type) {
|
||||
@ -460,7 +328,7 @@ u32 cpu_mask(void)
|
||||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return mask;
|
||||
}
|
||||
@ -482,7 +350,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
|
||||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
if (initiator_type(cluster, j)) {
|
||||
if (count == core)
|
||||
@ -491,7 +360,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
|
||||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return -1; /* cannot identify the cluster */
|
||||
}
|
||||
@ -505,7 +374,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
|
||||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
type = initiator_type(cluster, j);
|
||||
if (type) {
|
||||
@ -515,7 +385,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
|
||||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return -1; /* cannot identify the cluster */
|
||||
}
|
||||
@ -527,15 +397,13 @@ int print_cpuinfo(void)
|
||||
struct sys_info sysinfo;
|
||||
char buf[32];
|
||||
unsigned int i, core;
|
||||
u32 type;
|
||||
u32 type, rcw;
|
||||
|
||||
puts("SoC: ");
|
||||
|
||||
cpu_name(buf);
|
||||
printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
|
||||
|
||||
printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
|
||||
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
puts("Clock Configuration:");
|
||||
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
|
||||
@ -551,18 +419,20 @@ int print_cpuinfo(void)
|
||||
printf("\n Bus: %-4s MHz ",
|
||||
strmhz(buf, sysinfo.freq_systembus));
|
||||
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
|
||||
#endif
|
||||
puts("\n");
|
||||
|
||||
/* Display the RCW, so that no one gets confused as to what RCW
|
||||
/*
|
||||
* Display the RCW, so that no one gets confused as to what RCW
|
||||
* we're actually using for this boot.
|
||||
*/
|
||||
puts("Reset Configuration Word (RCW):");
|
||||
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
||||
u32 rcw = in_le32(&gur->rcwsr[i]);
|
||||
|
||||
rcw = gur_in32(&gur->rcwsr[i]);
|
||||
if ((i % 4) == 0)
|
||||
printf("\n %02x:", i * 4);
|
||||
printf("\n %08x:", i * 4);
|
||||
printf(" %08x", rcw);
|
||||
}
|
||||
puts("\n");
|
||||
@ -590,11 +460,13 @@ int cpu_eth_init(bd_t *bis)
|
||||
|
||||
int arch_early_init_r(void)
|
||||
{
|
||||
int rv;
|
||||
rv = fsl_lsch3_wake_seconday_cores();
|
||||
#ifdef CONFIG_MP
|
||||
int rv = 1;
|
||||
|
||||
rv = fsl_layerscape_wake_seconday_cores();
|
||||
if (rv)
|
||||
printf("Did not wake secondary cores\n");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_SERDES
|
||||
fsl_serdes_init();
|
||||
@ -605,7 +477,9 @@ int arch_early_init_r(void)
|
||||
int timer_init(void)
|
||||
{
|
||||
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
|
||||
#endif
|
||||
#ifdef COUNTER_FREQUENCY_REAL
|
||||
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
|
||||
|
||||
@ -613,10 +487,12 @@ int timer_init(void)
|
||||
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
/* Enable timebase for all clusters.
|
||||
* It is safe to do so even some clusters are not enabled.
|
||||
*/
|
||||
out_le32(cltbenr, 0xf);
|
||||
#endif
|
||||
|
||||
/* Enable clock for timer
|
||||
* This is a global setting.
|
||||
@ -632,7 +508,7 @@ void reset_cpu(ulong addr)
|
||||
u32 val;
|
||||
|
||||
/* Raise RESET_REQ_B */
|
||||
val = in_le32(rstcr);
|
||||
val = scfg_in32(rstcr);
|
||||
val |= 0x02;
|
||||
out_le32(rstcr, val);
|
||||
scfg_out32(rstcr, val);
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -7,11 +7,16 @@
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch-fsl-lsch3/fdt.h>
|
||||
#include <phy.h>
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch/fdt.h>
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
#include "mp.h"
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
void ft_fixup_cpu(void *blob)
|
||||
@ -150,6 +155,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
|
||||
* for all DPAA2 devices.
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
static void fdt_fixup_smmu(void *blob)
|
||||
{
|
||||
int nodeoffset;
|
||||
@ -165,6 +171,7 @@ static void fdt_fixup_smmu(void *blob)
|
||||
fdt_fixup_smmu_pcie(blob);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
@ -181,9 +188,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
fdt_fixup_esdhc(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
fdt_fixup_smmu(blob);
|
||||
#endif
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -8,7 +8,7 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = in_le32(&gur->rcwsr[28]);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[28]);
|
||||
int i;
|
||||
|
||||
switch (sd) {
|
||||
@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
||||
|
||||
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
|
||||
|
||||
cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
|
||||
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
|
||||
cfg >>= sd_prctl_shift;
|
||||
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
@ -11,8 +11,8 @@
|
||||
#include <fsl_ifc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "cpu.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
sys_info->freq_ddrbus2 = sysclk;
|
||||
#endif
|
||||
|
||||
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
/* Platform clock is half of platform PLL */
|
||||
sys_info->freq_systembus /= 2;
|
||||
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
|
||||
|
||||
@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FSL_IFC)
|
||||
ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
|
||||
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
|
||||
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
|
||||
|
||||
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* (C) Copyright 2014 Freescale Semiconductor
|
||||
* (C) Copyright 2014-2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
@ -10,11 +10,14 @@
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/gic.h>
|
||||
#include <asm/macro.h>
|
||||
#include "mp.h"
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
mov x29, lr /* Save LR */
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
/* Add fully-coherent masters to DVM domain */
|
||||
ldr x0, =CCI_MN_BASE
|
||||
ldr x1, =CCI_MN_RNF_NODEID_LIST
|
||||
@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
|
||||
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
|
||||
ldr x1, =0x00FF000C
|
||||
bl ccn504_set_qos
|
||||
#endif
|
||||
|
||||
/* Set the SMMU page size in the sACR register */
|
||||
ldr x1, =SMMU_BASE
|
||||
@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
|
||||
|
||||
branch_if_master x0, x1, 2f
|
||||
|
||||
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
|
||||
ldr x0, =secondary_boot_func
|
||||
blr x0
|
||||
2:
|
||||
#endif
|
||||
|
||||
2:
|
||||
#ifdef CONFIG_FSL_TZPC_BP147
|
||||
/* Set Non Secure access for all devices protected via TZPC */
|
||||
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
|
||||
@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
|
||||
ret
|
||||
ENDPROC(__asm_flush_l3_cache)
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
/* Keep literals not used by the secondary boot code outside it */
|
||||
.ltorg
|
||||
|
||||
@ -353,3 +360,4 @@ __real_cntfrq:
|
||||
/* Secondary Boot Code ends here */
|
||||
__secondary_boot_code_size:
|
||||
.quad .-secondary_boot_code
|
||||
#endif
|
||||
@ -1,12 +1,11 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
|
||||
struct serdes_config {
|
||||
u8 protocol;
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -7,9 +7,8 @@
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include "mp.h"
|
||||
#include <asm/arch/mp.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -23,7 +22,7 @@ phys_addr_t determine_mp_bootpg(void)
|
||||
return (phys_addr_t)&secondary_boot_code;
|
||||
}
|
||||
|
||||
int fsl_lsch3_wake_seconday_cores(void)
|
||||
int fsl_layerscape_wake_seconday_cores(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
|
||||
@ -48,9 +47,10 @@ int fsl_lsch3_wake_seconday_cores(void)
|
||||
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
|
||||
|
||||
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
|
||||
out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
|
||||
out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
|
||||
out_le32(&gur->scratchrw[6], 1);
|
||||
|
||||
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
|
||||
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
|
||||
gur_out32(&gur->scratchrw[6], 1);
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
rst->brrl = cores;
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
@ -1,19 +1,18 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
* Copyright 2014-2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <nand.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
static void erratum_a008751(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
@ -77,31 +76,11 @@ void fsl_lsch3_early_init_f(void)
|
||||
init_early_memctl_regs(); /* tighten IFC timing */
|
||||
erratum_a009203();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
arch_cpu_init();
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
env_init();
|
||||
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
|
||||
|
||||
serial_init();
|
||||
console_init_f();
|
||||
dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_NAND;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
76
arch/arm/cpu/armv8/fsl-layerscape/spl.c
Normal file
76
arch/arm/cpu/armv8/fsl-layerscape/spl.c
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <fsl_csu.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
return BOOT_DEVICE_NAND;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(void)
|
||||
{
|
||||
switch (spl_boot_device()) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
#ifdef CONFIG_SPL_FAT_SUPPORT
|
||||
return MMCSD_MODE_FAT;
|
||||
#else
|
||||
return MMCSD_MODE_RAW;
|
||||
#endif
|
||||
case BOOT_DEVICE_NAND:
|
||||
return 0;
|
||||
default:
|
||||
puts("spl: error: unsupported device\n");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Set global data pointer */
|
||||
gd = &gdata;
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
#ifdef CONFIG_LS2085A
|
||||
arch_cpu_init();
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
init_early_memctl_regs();
|
||||
#endif
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
#ifdef CONFIG_LS2085A
|
||||
env_init();
|
||||
#endif
|
||||
get_clocks();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
i2c_init_all();
|
||||
#endif
|
||||
dram_init();
|
||||
|
||||
/* Clear the BSS */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
@ -1,13 +0,0 @@
|
||||
#
|
||||
# Copyright 2014, Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += lowlevel.o
|
||||
obj-y += soc.o
|
||||
obj-y += speed.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
@ -1,7 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info);
|
||||
@ -1,12 +1,12 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
@ -21,4 +21,4 @@ enum mxc_clock {
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
|
||||
96
arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
96
arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
|
||||
#if defined(CONFIG_LS2085A)
|
||||
#define CONFIG_MAX_CPUS 16
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define SRDS_MAX_LANES 8
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_FSL_DDR_LE
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
|
||||
165
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
165
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
@ -0,0 +1,165 @@
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_CPU_H
|
||||
#define _FSL_LAYERSCAPE_CPU_H
|
||||
|
||||
static struct cpu_type cpu_type_list[] = {
|
||||
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
|
||||
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
|
||||
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define SECTION_SHIFT_L0 39UL
|
||||
#define SECTION_SHIFT_L1 30UL
|
||||
#define SECTION_SHIFT_L2 21UL
|
||||
#define BLOCK_SIZE_L0 0x8000000000
|
||||
#define BLOCK_SIZE_L1 0x40000000
|
||||
#define BLOCK_SIZE_L2 0x200000
|
||||
#define NUM_OF_ENTRY 512
|
||||
#define TCR_EL2_PS_40BIT (2 << 16)
|
||||
|
||||
#define LAYERSCAPE_VA_BITS (40)
|
||||
#define LAYERSCAPE_TCR (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_NON | \
|
||||
TCR_ORGN_NC | \
|
||||
TCR_IRGN_NC | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_OUTER | \
|
||||
TCR_ORGN_WBWA | \
|
||||
TCR_IRGN_WBWA | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
|
||||
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
|
||||
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
|
||||
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
|
||||
#endif
|
||||
|
||||
struct sys_mmu_table {
|
||||
u64 virt_addr;
|
||||
u64 phys_addr;
|
||||
u64 size;
|
||||
u64 memory_type;
|
||||
u64 share;
|
||||
};
|
||||
|
||||
struct table_info {
|
||||
u64 *ptr;
|
||||
u64 table_base;
|
||||
u64 entry_size;
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table early_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
/* For IFC Region #1, only the first 4MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table final_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
|
||||
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
|
||||
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
|
||||
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
/* For QBMAN portal, only the first 64MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#ifdef CONFIG_LS2085A
|
||||
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#endif
|
||||
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
|
||||
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
|
||||
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
|
||||
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core);
|
||||
u32 cpu_mask(void);
|
||||
#endif /* _FSL_LAYERSCAPE_CPU_H */
|
||||
@ -4,7 +4,11 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
|
||||
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
|
||||
void append_mmu_masters(void *blob, const char *smmu_path,
|
||||
const char *master_name, u32 *stream_ids, int count);
|
||||
void fdt_fixup_smmu_pcie(void *blob);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
|
||||
@ -4,13 +4,12 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
#ifndef __FSL_SERDES_H__
|
||||
#define __FSL_SERDES_H__
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#define SRDS_MAX_LANES 8
|
||||
|
||||
#if defined(CONFIG_LS2085A)
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
@ -56,12 +55,12 @@ enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
||||
#endif /* __FSL_SERDES_H__ */
|
||||
@ -6,9 +6,109 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
#define __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
/* SP (Cortex-A5) related */
|
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
|
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
/* This is chassis generation 3 */
|
||||
|
||||
struct sys_info {
|
||||
@ -109,21 +209,6 @@ struct ccsr_gur {
|
||||
u8 res_858[0x1000-0x858];
|
||||
};
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
|
||||
struct ccsr_clk_cluster_group {
|
||||
struct {
|
||||
@ -180,4 +265,4 @@ struct ccsr_reset {
|
||||
u32 ip_rev1; /* 0xbf8 */
|
||||
u32 ip_rev2; /* 0xbfc */
|
||||
};
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
|
||||
55
arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
55
arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_FSL_LPUART
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FSL_LPUART */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
|
||||
10
arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
10
arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#include <asm/arch-armv8/mmu.h>
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
|
||||
@ -1,11 +1,11 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CH3_MP_H
|
||||
#define _FSL_CH3_MP_H
|
||||
#ifndef _FSL_LAYERSCAPE_MP_H
|
||||
#define _FSL_LAYERSCAPE_MP_H
|
||||
|
||||
/*
|
||||
* Each spin table element is defined as
|
||||
@ -29,10 +29,10 @@ extern u64 __spin_table[];
|
||||
extern u64 __real_cntfrq;
|
||||
extern u64 *secondary_boot_code;
|
||||
extern size_t __secondary_boot_code_size;
|
||||
int fsl_lsch3_wake_seconday_cores(void);
|
||||
int fsl_layerscape_wake_seconday_cores(void);
|
||||
void *get_spin_tbl_addr(void);
|
||||
phys_addr_t determine_mp_bootpg(void);
|
||||
void secondary_boot_func(void);
|
||||
int is_core_online(u64 cpu_id);
|
||||
#endif
|
||||
#endif /* _FSL_CH3_MP_H */
|
||||
#endif /* _FSL_LAYERSCAPE_MP_H */
|
||||
@ -4,6 +4,25 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define gur_in32(a) in_le32(a)
|
||||
#define gur_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
|
||||
#define gur_in32(a) in_be32(a)
|
||||
#define gur_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define scfg_in32(a) in_le32(a)
|
||||
#define scfg_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
|
||||
#define scfg_in32(a) in_be32(a)
|
||||
#define scfg_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
struct cpu_type {
|
||||
char name[15];
|
||||
u32 soc_ver;
|
||||
@ -25,4 +44,4 @@ struct cpu_type {
|
||||
|
||||
void fsl_lsch3_early_init_f(void);
|
||||
void cpu_name(char *name);
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
|
||||
10
arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
10
arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
@ -0,0 +1,10 @@
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_SPEED_H
|
||||
#define _FSL_LAYERSCAPE_SPEED_H
|
||||
void get_sys_info(struct sys_info *sys_info);
|
||||
#endif /* _FSL_LAYERSCAPE_SPEED_H */
|
||||
@ -1,185 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
|
||||
#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_MP
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
/* Link Definitions */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
/* SP (Cortex-A5) related */
|
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
|
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_FSL_DDR_LE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
/* IFC */
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
#define CONFIG_MAX_CPUS 16
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
|
||||
@ -1,9 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
|
||||
#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
|
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
|
||||
@ -1,13 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
|
||||
#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
|
||||
@ -15,14 +15,11 @@
|
||||
#define CONFIG_STATIC_RELA
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch-fsl-lsch3/config.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LS102XA) || \
|
||||
defined(CONFIG_CPU_PXA27X) || \
|
||||
defined(CONFIG_CPU_MONAHANS) || \
|
||||
defined(CONFIG_CPU_PXA25X)
|
||||
defined(CONFIG_CPU_PXA25X) || \
|
||||
defined(CONFIG_FSL_LAYERSCAPE)
|
||||
#include <asm/arch/config.h>
|
||||
#endif
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@ config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-lsch3"
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ls2085a_emu"
|
||||
@ -23,7 +23,7 @@ config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-lsch3"
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ls2085a_simu"
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#include <fsl_debug_server.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <environment.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-lsch3"
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ls2085aqds"
|
||||
|
||||
@ -8,7 +8,6 @@
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <hwconfig.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <malloc.h>
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#include <environment.h>
|
||||
#include <i2c.h>
|
||||
#include <rtc.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <hwconfig.h>
|
||||
|
||||
#include "../common/qixis.h"
|
||||
|
||||
@ -8,7 +8,7 @@ config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-lsch3"
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ls2085ardb"
|
||||
|
||||
@ -16,7 +16,6 @@
|
||||
#include <asm/io.h>
|
||||
#include <exports.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <environment.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "../common/qixis.h"
|
||||
#include "ls2085ardb_qixis.h"
|
||||
|
||||
@ -523,8 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
|
||||
#endif
|
||||
|
||||
static struct mxc_i2c_bus mxc_i2c_buses[] = {
|
||||
#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
|
||||
defined(CONFIG_VF610)
|
||||
#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
|
||||
defined(CONFIG_FSL_LAYERSCAPE)
|
||||
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
|
||||
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
|
||||
{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
|
||||
|
||||
@ -8,7 +8,6 @@
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <fsl_debug_server.h>
|
||||
|
||||
@ -7,9 +7,7 @@
|
||||
#include <phy.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
u32 dpmac_to_devdisr[] = {
|
||||
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
|
||||
|
||||
@ -11,7 +11,9 @@
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/arch-fsl-lsch3/fdt.h>
|
||||
#ifdef CONFIG_FSL_LAYERSCAPE
|
||||
#include <asm/arch/fdt.h>
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
|
||||
|
||||
@ -76,6 +76,9 @@ typedef volatile unsigned char vu_char;
|
||||
#ifdef CONFIG_SOC_DA8XX
|
||||
#include <asm/arch/hardware.h>
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch/immap_lsch3.h>
|
||||
#endif
|
||||
|
||||
#include <part.h>
|
||||
#include <flash.h>
|
||||
|
||||
@ -9,8 +9,10 @@
|
||||
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_FSL_LSCH3
|
||||
#define CONFIG_LS2085A
|
||||
#define CONFIG_MP
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
|
||||
@ -18,12 +20,15 @@
|
||||
#define CONFIG_ARM_ERRATA_828024
|
||||
#define CONFIG_ARM_ERRATA_826974
|
||||
|
||||
#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
|
||||
#include <asm/arch-fsl-lsch3/config.h>
|
||||
#include <asm/arch/ls2085a_stream_id.h>
|
||||
#include <asm/arch/config.h>
|
||||
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
|
||||
#define CONFIG_SYS_HAS_SERDES
|
||||
#endif
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
|
||||
|
||||
/* We need architecture specific misc initializations */
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
@ -62,6 +67,7 @@
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user