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arm: socfpga: gen5: reduce SPL pre-reloc malloc

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By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Simon Goldschmidt 2019-04-09 21:02:06 +02:00 committed by Marek Vasut
parent aef44283ac
commit 9dc61aac2d
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-socfpga/Kconfig
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@ -6,6 +6,9 @@ config NR_DRAM_BANKS
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
config SPL_SYS_MALLOC_F_LEN
default 0x800 if TARGET_SOCFPGA_GEN5
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2