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spi: Add Amlogic Meson SPI Flash Controller driver
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. This driver, ported from the Linux meson-spi-spifc driver, add support for this controller on the Amlogic Meson GX SoCs in U-Boot. Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Jagan Teki
parent
ebe3497c9c
commit
9d26506a9c
@ -116,6 +116,14 @@ config ICH_SPI
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access the SPI NOR flash on platforms embedding this Intel
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ICH IP core.
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config MESON_SPIFC
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bool "Amlogic Meson SPI Flash Controller driver"
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depends on ARCH_MESON
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help
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Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
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This driver can be used to access the SPI NOR flash chips on
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Amlogic Meson SoCs.
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config MT7621_SPI
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bool "MediaTek MT7621 SPI driver"
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depends on ARCH_MT7620
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@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
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obj-$(CONFIG_ICH_SPI) += ich.o
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obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
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obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
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obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
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obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
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320
drivers/spi/meson_spifc.c
Normal file
320
drivers/spi/meson_spifc.c
Normal file
@ -0,0 +1,320 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Amlogic Meson SPI Flash Controller driver
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*/
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#include <common.h>
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#include <spi.h>
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#include <clk.h>
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#include <dm.h>
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#include <regmap.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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/* register map */
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#define REG_CMD 0x00
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#define REG_ADDR 0x04
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#define REG_CTRL 0x08
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#define REG_CTRL1 0x0c
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#define REG_STATUS 0x10
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#define REG_CTRL2 0x14
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#define REG_CLOCK 0x18
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#define REG_USER 0x1c
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#define REG_USER1 0x20
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#define REG_USER2 0x24
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#define REG_USER3 0x28
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#define REG_USER4 0x2c
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#define REG_SLAVE 0x30
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#define REG_SLAVE1 0x34
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#define REG_SLAVE2 0x38
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#define REG_SLAVE3 0x3c
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#define REG_C0 0x40
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#define REG_B8 0x60
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#define REG_MAX 0x7c
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/* register fields */
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#define CMD_USER BIT(18)
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#define CTRL_ENABLE_AHB BIT(17)
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#define CLOCK_SOURCE BIT(31)
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#define CLOCK_DIV_SHIFT 12
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#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
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#define CLOCK_CNT_HIGH_SHIFT 6
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#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
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#define CLOCK_CNT_LOW_SHIFT 0
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#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
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#define USER_DIN_EN_MS BIT(0)
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#define USER_CMP_MODE BIT(2)
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#define USER_CLK_NOT_INV BIT(7)
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#define USER_UC_DOUT_SEL BIT(27)
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#define USER_UC_DIN_SEL BIT(28)
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#define USER_UC_MASK ((BIT(5) - 1) << 27)
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#define USER1_BN_UC_DOUT_SHIFT 17
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#define USER1_BN_UC_DOUT_MASK (0xff << 16)
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#define USER1_BN_UC_DIN_SHIFT 8
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#define USER1_BN_UC_DIN_MASK (0xff << 8)
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#define USER4_CS_POL_HIGH BIT(23)
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#define USER4_IDLE_CLK_HIGH BIT(29)
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#define USER4_CS_ACT BIT(30)
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#define SLAVE_TRST_DONE BIT(4)
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#define SLAVE_OP_MODE BIT(30)
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#define SLAVE_SW_RST BIT(31)
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#define SPIFC_BUFFER_SIZE 64
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struct meson_spifc_priv {
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struct regmap *regmap;
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struct clk clk;
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};
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/**
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* meson_spifc_drain_buffer() - copy data from device buffer to memory
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* @spifc: the Meson SPI device
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* @buf: the destination buffer
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* @len: number of bytes to copy
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*/
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static void meson_spifc_drain_buffer(struct meson_spifc_priv *spifc,
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u8 *buf, int len)
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{
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u32 data;
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int i = 0;
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while (i < len) {
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regmap_read(spifc->regmap, REG_C0 + i, &data);
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if (len - i >= 4) {
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*((u32 *)buf) = data;
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buf += 4;
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} else {
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memcpy(buf, &data, len - i);
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break;
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}
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i += 4;
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}
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}
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/**
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* meson_spifc_fill_buffer() - copy data from memory to device buffer
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* @spifc: the Meson SPI device
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* @buf: the source buffer
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* @len: number of bytes to copy
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*/
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static void meson_spifc_fill_buffer(struct meson_spifc_priv *spifc,
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const u8 *buf, int len)
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{
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u32 data = 0;
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int i = 0;
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while (i < len) {
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if (len - i >= 4)
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data = *(u32 *)buf;
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else
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memcpy(&data, buf, len - i);
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regmap_write(spifc->regmap, REG_C0 + i, data);
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buf += 4;
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i += 4;
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}
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}
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/**
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* meson_spifc_txrx() - transfer a chunk of data
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* @spifc: the Meson SPI device
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* @dout: data buffer for TX
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* @din: data buffer for RX
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* @offset: offset of the data to transfer
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* @len: length of the data to transfer
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* @last_xfer: whether this is the last transfer of the message
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* @last_chunk: whether this is the last chunk of the transfer
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* Return: 0 on success, a negative value on error
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*/
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static int meson_spifc_txrx(struct meson_spifc_priv *spifc,
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const u8 *dout, u8 *din, int offset,
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int len, bool last_xfer, bool last_chunk)
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{
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bool keep_cs = true;
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u32 data;
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int ret;
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if (dout)
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meson_spifc_fill_buffer(spifc, dout + offset, len);
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/* enable DOUT stage */
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regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
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USER_UC_DOUT_SEL);
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regmap_write(spifc->regmap, REG_USER1,
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(8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
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/* enable data input during DOUT */
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regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
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USER_DIN_EN_MS);
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if (last_chunk && last_xfer)
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keep_cs = false;
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regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
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keep_cs ? USER4_CS_ACT : 0);
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/* clear transition done bit */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
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/* start transfer */
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regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
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/* wait for the current operation to terminate */
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ret = regmap_read_poll_timeout(spifc->regmap, REG_SLAVE, data,
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(data & SLAVE_TRST_DONE),
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0, 5 * CONFIG_SYS_HZ);
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if (!ret && din)
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meson_spifc_drain_buffer(spifc, din + offset, len);
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return ret;
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}
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/**
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* meson_spifc_xfer() - perform a single transfer
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* @dev: the SPI controller device
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* @bitlen: length of the transfer
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* @dout: data buffer for TX
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* @din: data buffer for RX
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* @flags: transfer flags
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* Return: 0 on success, a negative value on error
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*/
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static int meson_spifc_xfer(struct udevice *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct meson_spifc_priv *spifc = dev_get_priv(slave->parent);
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int blen = bitlen / 8;
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int len, done = 0, ret = 0;
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if (bitlen % 8)
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return -EINVAL;
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debug("xfer len %d (%d) dout %p din %p\n", bitlen, blen, dout, din);
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regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
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while (done < blen && !ret) {
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len = min_t(int, blen - done, SPIFC_BUFFER_SIZE);
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ret = meson_spifc_txrx(spifc, dout, din, done, len,
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flags & SPI_XFER_END,
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done + len >= blen);
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done += len;
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}
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regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
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CTRL_ENABLE_AHB);
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return ret;
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}
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/**
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* meson_spifc_set_speed() - program the clock divider
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* @dev: the SPI controller device
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* @speed: desired speed in Hz
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*/
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static int meson_spifc_set_speed(struct udevice *dev, uint speed)
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{
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struct meson_spifc_priv *spifc = dev_get_priv(dev);
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unsigned long parent, value;
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int n;
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parent = clk_get_rate(&spifc->clk);
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n = max_t(int, parent / speed - 1, 1);
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debug("parent %lu, speed %u, n %d\n", parent, speed, n);
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value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
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value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
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value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
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CLOCK_CNT_HIGH_MASK;
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regmap_write(spifc->regmap, REG_CLOCK, value);
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return 0;
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}
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/**
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* meson_spifc_set_mode() - setups the SPI bus mode
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* @dev: the SPI controller device
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* @mode: desired mode bitfield
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* Return: 0 on success, -ENODEV on error
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*/
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static int meson_spifc_set_mode(struct udevice *dev, uint mode)
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{
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struct meson_spifc_priv *spifc = dev_get_priv(dev);
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if (mode & (SPI_CPHA | SPI_RX_QUAD | SPI_RX_DUAL |
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SPI_TX_QUAD | SPI_TX_DUAL))
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return -ENODEV;
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regmap_update_bits(spifc->regmap, REG_USER, USER_CLK_NOT_INV,
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mode & SPI_CPOL ? USER_CLK_NOT_INV : 0);
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regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_POL_HIGH,
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mode & SPI_CS_HIGH ? USER4_CS_POL_HIGH : 0);
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return 0;
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}
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/**
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* meson_spifc_hw_init() - reset and initialize the SPI controller
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* @spifc: the Meson SPI device
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*/
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static void meson_spifc_hw_init(struct meson_spifc_priv *spifc)
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{
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/* reset device */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
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SLAVE_SW_RST);
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/* disable compatible mode */
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regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
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/* set master mode */
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regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
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}
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static const struct dm_spi_ops meson_spifc_ops = {
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.xfer = meson_spifc_xfer,
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.set_speed = meson_spifc_set_speed,
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.set_mode = meson_spifc_set_mode,
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};
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static int meson_spifc_probe(struct udevice *dev)
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{
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struct meson_spifc_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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meson_spifc_hw_init(priv);
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return 0;
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}
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static const struct udevice_id meson_spifc_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-spifc", },
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{ }
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};
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U_BOOT_DRIVER(meson_spifc) = {
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.name = "meson_spifc",
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.id = UCLASS_SPI,
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.of_match = meson_spifc_ids,
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.ops = &meson_spifc_ops,
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.probe = meson_spifc_probe,
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.priv_auto_alloc_size = sizeof(struct meson_spifc_priv),
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};
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