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imx8ulp: Workaround LPOSC_TRIM fuse load issue

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8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.

A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2021-10-29 09:46:25 +08:00 committed by Stefano Babic
parent 112b4cac9d
commit 9c7fbebe5d
3 changed files with 27 additions and 0 deletions
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1
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
View File

@ -17,4 +17,5 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
#endif

20
arch/arm/mach-imx/imx8ulp/soc.c
View File

@ -487,6 +487,26 @@ void lpav_configure(void)
writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58);
}
void load_lposc_fuse(void)
{
int ret;
u32 val = 0, val2 = 0, reg;
ret = fuse_read(25, 0, &val);
if (ret)
return; /* failed */
ret = fuse_read(25, 1, &val2);
if (ret)
return; /* failed */
/* LPOSCCTRL */
reg = readl(0x2802f304);
reg &= ~0xff;
reg |= (val & 0xff);
writel(reg, 0x2802f304);
}
void set_lpav_qos(void)
{
/* Set read QoS of dcnano on LPAV NIC */

6
board/freescale/imx8ulp_evk/spl.c
View File

@ -77,6 +77,12 @@ void spl_board_init(void)
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
/* Load the lposc fuse for single boot to work around ROM issue,
* The fuse depends on S400 to read.
*/
if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
load_lposc_fuse();
upower_init();
power_init_board();