mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-25 05:04:23 +08:00
Code Issues Packages Projects Releases Wiki Activity

mxs: prefix register structs with 'mxs' prefix

Browse Source 
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Otavio Salvador 2012-08-05 09:05:31 +00:00 committed by Albert ARIBAUD
parent ddcf13b152
commit 9c471142bc
32 changed files with 188 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/arm/cpu/arm926ejs/mxs/clock.c
View File

@ -43,8 +43,8 @@
static uint32_t mx28_get_pclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
static uint32_t mx28_get_hclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
uint32_t clkctrl;
@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
static uint32_t mx28_get_emiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
static uint32_t mx28_get_gpmiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
int io_reg;
@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint8_t ret;
int io_reg;
@ -199,8 +199,8 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK3)
@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;
@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mx28_ssp_regs *ssp_regs;
struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),

28
arch/arm/cpu/arm926ejs/mxs/mx28.c
View File

@ -51,10 +51,10 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(ulong ignored)
{
struct mx28_rtc_regs *rtc_regs =
(struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mx28_lcdif_regs *lcdif_regs =
(struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
struct mxs_lcdif_regs *lcdif_regs =
(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
/*
* Shut down the LCD controller as it interferes with BootROM boot mode
@ -155,8 +155,8 @@ int arch_misc_init(void)
int arch_cpu_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
extern uint32_t _start;
mx28_fixup_vt((uint32_t)&_start);
@ -190,8 +190,8 @@ int arch_cpu_init(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
static const char *get_cpu_type(void)
{
struct mx28_digctl_regs *digctl_regs =
(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX28:
@ -203,8 +203,8 @@ static const char *get_cpu_type(void)
static const char *get_cpu_rev(void)
{
struct mx28_digctl_regs *digctl_regs =
(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
@ -249,8 +249,8 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
#ifdef CONFIG_CMD_NET
int cpu_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Turn on ENET clocks */
clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
@ -291,8 +291,8 @@ void mx28_adjust_mac(int dev_id, unsigned char *mac)
#define MXS_OCOTP_MAX_TIMEOUT 1000000
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
struct mx28_ocotp_regs *ocotp_regs =
(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
struct mxs_ocotp_regs *ocotp_regs =
(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
uint32_t data;
memset(mac, 0, 6);

4
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
View File

@ -32,7 +32,7 @@
void mx28_lradc_init(void)
{
struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
@ -51,7 +51,7 @@ void mx28_lradc_init(void)
void mx28_lradc_enable_batt_measurement(void)
{
struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
/* Check if the channel is present at all. */
if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))

24
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View File

@ -100,8 +100,8 @@ void init_mx28_200mhz_ddr2(void)
void mx28_mem_init_clock(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
@ -131,8 +131,8 @@ void mx28_mem_init_clock(void)
void mx28_mem_setup_cpu_and_hbus(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
@ -163,8 +163,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
void mx28_mem_setup_vdda(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
@ -174,8 +174,8 @@ void mx28_mem_setup_vdda(void)
void mx28_mem_setup_vddd(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
@ -204,10 +204,10 @@ uint32_t mx28_mem_get_size(void)
void mx28_mem_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mx28_pinctrl_regs *pinctrl_regs =
(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,

116
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -32,8 +32,8 @@
void mx28_power_clock2xtal(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
@ -42,8 +42,8 @@ void mx28_power_clock2xtal(void)
void mx28_power_clock2pll(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
@ -54,8 +54,8 @@ void mx28_power_clock2pll(void)
void mx28_power_clear_auto_restart(void)
{
struct mx28_rtc_regs *rtc_regs =
(struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
@ -87,8 +87,8 @@ void mx28_power_clear_auto_restart(void)
void mx28_power_set_linreg(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
@ -106,8 +106,8 @@ void mx28_power_set_linreg(void)
int mx28_get_batt_volt(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
@ -122,8 +122,8 @@ int mx28_is_batt_ready(void)
int mx28_is_batt_good(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mx28_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
@ -162,8 +162,8 @@ int mx28_is_batt_good(void)
void mx28_power_setup_5v_detect(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
@ -174,8 +174,8 @@ void mx28_power_setup_5v_detect(void)
void mx28_src_power_init(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
@ -205,8 +205,8 @@ void mx28_src_power_init(void)
void mx28_power_init_4p2_params(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
@ -229,8 +229,8 @@ void mx28_power_init_4p2_params(void)
void mx28_enable_4p2_dcdc_input(int xfer)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
@ -325,8 +325,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
void mx28_power_init_4p2_regulator(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
@ -409,8 +409,8 @@ void mx28_power_init_4p2_regulator(void)
void mx28_power_init_dcdc_4p2_source(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
@ -431,8 +431,8 @@ void mx28_power_init_dcdc_4p2_source(void)
void mx28_power_enable_4p2(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
@ -490,8 +490,8 @@ void mx28_power_enable_4p2(void)
void mx28_boot_valid_5v(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
@ -513,8 +513,8 @@ void mx28_boot_valid_5v(void)
void mx28_powerdown(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
@ -522,8 +522,8 @@ void mx28_powerdown(void)
void mx28_batt_boot(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
@ -566,8 +566,8 @@ void mx28_batt_boot(void)
void mx28_handle_5v_conflict(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
@ -598,8 +598,8 @@ void mx28_handle_5v_conflict(void)
void mx28_5v_boot(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
@ -621,8 +621,8 @@ void mx28_5v_boot(void)
void mx28_init_batt_bo(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
@ -635,8 +635,8 @@ void mx28_init_batt_bo(void)
void mx28_switch_vddd_to_dcdc_source(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
@ -650,10 +650,10 @@ void mx28_switch_vddd_to_dcdc_source(void)
void mx28_power_configure_power_source(void)
{
int batt_ready, batt_good;
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mx28_lradc_regs *lradc_regs =
(struct mx28_lradc_regs *)MXS_LRADC_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
mx28_src_power_init();
@ -690,8 +690,8 @@ void mx28_power_configure_power_source(void)
void mx28_enable_output_rail_protection(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@ -708,8 +708,8 @@ void mx28_enable_output_rail_protection(void)
int mx28_get_vddio_power_source_off(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
@ -736,8 +736,8 @@ int mx28_get_vddio_power_source_off(void)
int mx28_get_vddd_power_source_off(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
@ -767,8 +767,8 @@ int mx28_get_vddd_power_source_off(void)
void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
@ -864,8 +864,8 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
@ -968,8 +968,8 @@ void mx28_setup_batt_detect(void)
void mx28_power_init(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mx28_power_clock2xtal();
mx28_power_clear_auto_restart();
@ -998,8 +998,8 @@ void mx28_power_init(void)
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
void mx28_power_wait_pswitch(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;

8
arch/arm/cpu/arm926ejs/mxs/timer.c
View File

@ -62,8 +62,8 @@ static inline unsigned long us_to_tick(unsigned long us)
int timer_init(void)
{
struct mx28_timrot_regs *timrot_regs =
(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
struct mxs_timrot_regs *timrot_regs =
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Reset Timers and Rotary Encoder module */
mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
@ -84,8 +84,8 @@ int timer_init(void)
unsigned long long get_ticks(void)
{
struct mx28_timrot_regs *timrot_regs =
(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
struct mxs_timrot_regs *timrot_regs =
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Current tick value */
uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);

2
arch/arm/include/asm/arch-mxs/regs-apbh.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_apbh_regs {
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)

2
arch/arm/include/asm/arch-mxs/regs-bch.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_bch_regs {
struct mxs_bch_regs {
mxs_reg_32(hw_bch_ctrl)
mxs_reg_32(hw_bch_status0)
mxs_reg_32(hw_bch_mode)

2
arch/arm/include/asm/arch-mxs/regs-clkctrl.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_clkctrl_regs {
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */

2
arch/arm/include/asm/arch-mxs/regs-digctl.h
View File

@ -25,7 +25,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_digctl_regs {
struct mxs_digctl_regs {
mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
mxs_reg_32(hw_digctl_status) /* 0x010 */
mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */

2
arch/arm/include/asm/arch-mxs/regs-gpmi.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_gpmi_regs {
struct mxs_gpmi_regs {
mxs_reg_32(hw_gpmi_ctrl0)
mxs_reg_32(hw_gpmi_compare)
mxs_reg_32(hw_gpmi_eccctrl)

2
arch/arm/include/asm/arch-mxs/regs-i2c.h
View File

@ -26,7 +26,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_i2c_regs {
struct mxs_i2c_regs {
mxs_reg_32(hw_i2c_ctrl0)
mxs_reg_32(hw_i2c_timing0)
mxs_reg_32(hw_i2c_timing1)

2
arch/arm/include/asm/arch-mxs/regs-lcdif.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_lcdif_regs {
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */

2
arch/arm/include/asm/arch-mxs/regs-lradc.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_lradc_regs {
struct mxs_lradc_regs {
mxs_reg_32(hw_lradc_ctrl0);
mxs_reg_32(hw_lradc_ctrl1);
mxs_reg_32(hw_lradc_ctrl2);

2
arch/arm/include/asm/arch-mxs/regs-ocotp.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_ocotp_regs {
struct mxs_ocotp_regs {
mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
mxs_reg_32(hw_ocotp_data) /* 0x10 */
mxs_reg_32(hw_ocotp_cust0) /* 0x20 */

2
arch/arm/include/asm/arch-mxs/regs-pinctrl.h
View File

@ -29,7 +29,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_pinctrl_regs {
struct mxs_pinctrl_regs {
mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
uint32_t reserved1[60];

2
arch/arm/include/asm/arch-mxs/regs-power.h
View File

@ -25,7 +25,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_power_regs {
struct mxs_power_regs {
mxs_reg_32(hw_power_ctrl)
mxs_reg_32(hw_power_5vctrl)
mxs_reg_32(hw_power_minpwr)

2
arch/arm/include/asm/arch-mxs/regs-rtc.h
View File

@ -26,7 +26,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_rtc_regs {
struct mxs_rtc_regs {
mxs_reg_32(hw_rtc_ctrl)
mxs_reg_32(hw_rtc_stat)
mxs_reg_32(hw_rtc_milliseconds)

2
arch/arm/include/asm/arch-mxs/regs-ssp.h
View File

@ -28,7 +28,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_ssp_regs {
struct mxs_ssp_regs {
mxs_reg_32(hw_ssp_ctrl0)
mxs_reg_32(hw_ssp_cmd0)
mxs_reg_32(hw_ssp_cmd1)

2
arch/arm/include/asm/arch-mxs/regs-timrot.h
View File

@ -28,7 +28,7 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_timrot_regs {
struct mxs_timrot_regs {
mxs_reg_32(hw_timrot_rotctrl)
mxs_reg_32(hw_timrot_rotcount)
mxs_reg_32(hw_timrot_timctrl0)

2
arch/arm/include/asm/arch-mxs/regs-usb.h
View File

@ -23,7 +23,7 @@
#ifndef __REGS_USB_H__
#define __REGS_USB_H__
struct mx28_usb_regs {
struct mxs_usb_regs {
uint32_t hw_usbctrl_id; /* 0x000 */
uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
uint32_t hw_usbctrl_hwhost; /* 0x008 */

2
arch/arm/include/asm/arch-mxs/regs-usbphy.h
View File

@ -23,7 +23,7 @@
#ifndef __REGS_USBPHY_H__
#define __REGS_USBPHY_H__
struct mx28_usbphy_regs {
struct mxs_usbphy_regs {
mxs_reg_32(hw_usbphy_pwd)
mxs_reg_32(hw_usbphy_tx)
mxs_reg_32(hw_usbphy_rx)

4
board/bluegiga/apx4devkit/apx4devkit.c
View File

@ -122,8 +122,8 @@ int board_eth_init(bd_t *bis)
#define MXS_OCOTP_MAX_TIMEOUT 1000000
void get_board_serial(struct tag_serialnr *serialnr)
{
struct mx28_ocotp_regs *ocotp_regs =
(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
struct mxs_ocotp_regs *ocotp_regs =
(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
serialnr->high = 0;
serialnr->low = 0;

4
board/denx/m28evk/m28evk.c
View File

@ -122,8 +122,8 @@ int fecmxc_mii_postcall(int phy)
int board_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;

4
board/freescale/mx28evk/mx28evk.c
View File

@ -115,8 +115,8 @@ int fecmxc_mii_postcall(int phy)
int board_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;

32
drivers/dma/apbh_dma.c
View File

@ -76,8 +76,8 @@ static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
*/
static int mxs_dma_read_semaphore(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
uint32_t tmp;
int ret;
@ -119,8 +119,8 @@ inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
*/
static int mxs_dma_enable(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
unsigned int sem;
struct mxs_dma_chan *pchan;
struct mxs_dma_desc *pdesc;
@ -191,8 +191,8 @@ static int mxs_dma_enable(int channel)
static int mxs_dma_disable(int channel)
{
struct mxs_dma_chan *pchan;
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
@ -220,8 +220,8 @@ static int mxs_dma_disable(int channel)
*/
static int mxs_dma_reset(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
@ -241,8 +241,8 @@ static int mxs_dma_reset(int channel)
*/
static int mxs_dma_enable_irq(int channel, int enable)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
@ -267,8 +267,8 @@ static int mxs_dma_enable_irq(int channel, int enable)
*/
static int mxs_dma_ack_irq(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
@ -504,8 +504,8 @@ static int mxs_dma_finish(int channel, struct list_head *head)
*/
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(chan);
@ -554,8 +554,8 @@ int mxs_dma_go(int chan)
*/
void mxs_dma_init(void)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);

12
drivers/i2c/mxs_i2c.c
View File

@ -38,7 +38,7 @@
void mxs_i2c_reset(void)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
int ret;
ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
@ -57,7 +57,7 @@ void mxs_i2c_reset(void)
void mxs_i2c_setup_read(uint8_t chip, int len)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
@ -76,7 +76,7 @@ void mxs_i2c_setup_read(uint8_t chip, int len)
void mxs_i2c_write(uchar chip, uint addr, int alen,
uchar *buf, int blen, int stop)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t data;
int i, remain, off;
@ -119,7 +119,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
int mxs_i2c_wait_for_ack(void)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp;
int timeout = MXS_I2C_MAX_TIMEOUT;
@ -157,7 +157,7 @@ err:
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp = 0;
int ret;
int i;
@ -212,7 +212,7 @@ int i2c_probe(uchar chip)
void i2c_init(int speed, int slaveadd)
{
struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
mxs_i2c_reset();

20
drivers/mmc/mxsmmc.c
View File

@ -52,7 +52,7 @@
struct mxsmmc_priv {
int id;
struct mx28_ssp_regs *regs;
struct mxs_ssp_regs *regs;
uint32_t clkseq_bypass;
uint32_t *clkctrl_ssp;
uint32_t buswidth;
@ -70,7 +70,7 @@ static int
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
struct mxs_ssp_regs *ssp_regs = priv->regs;
uint32_t reg;
int timeout;
uint32_t data_count;
@ -282,7 +282,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
static void mxsmmc_set_ios(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Set the clock speed */
if (mmc->clock)
@ -311,7 +311,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
static int mxsmmc_init(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Reset SSP */
mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
@ -335,8 +335,8 @@ static int mxsmmc_init(struct mmc *mmc)
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
@ -366,22 +366,22 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
priv->id = id;
switch (id) {
case 0:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
break;
case 1:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
break;
case 2:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
break;
case 3:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
break;

12
drivers/mtd/nand/mxs_nand.c
View File

@ -233,7 +233,7 @@ static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
*/
static int mxs_nand_wait_for_bch_complete(void)
{
struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
int timeout = MXS_NAND_BCH_TIMEOUT;
int ret;
@ -338,8 +338,8 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
struct mxs_nand_info *nand_info = chip->priv;
struct mx28_gpmi_regs *gpmi_regs =
(struct mx28_gpmi_regs *)MXS_GPMI_BASE;
struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
tmp = readl(&gpmi_regs->hw_gpmi_stat);
@ -968,7 +968,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
{
struct nand_chip *nand = mtd->priv;
struct mxs_nand_info *nand_info = nand->priv;
struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp;
/* Configure BCH and set NFC geometry */
@ -1056,8 +1056,8 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
*/
int mxs_nand_init(struct mxs_nand_info *info)
{
struct mx28_gpmi_regs *gpmi_regs =
(struct mx28_gpmi_regs *)MXS_GPMI_BASE;
struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
int i = 0, j;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *

6
drivers/rtc/mxsrtc.c
View File

@ -31,7 +31,7 @@
/* Set time in seconds since 1970-01-01 */
int mxs_rtc_set_time(uint32_t secs)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
int ret;
writel(secs, &rtc_regs->hw_rtc_seconds);
@ -52,7 +52,7 @@ int mxs_rtc_set_time(uint32_t secs)
int rtc_get(struct rtc_time *time)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
uint32_t secs;
secs = readl(&rtc_regs->hw_rtc_seconds);
@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *time)
void rtc_reset(void)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
int ret;
/* Set time to 1970-01-01 */

19
drivers/spi/mxs_spi.c
View File

@ -55,7 +55,7 @@ struct mxs_spi_slave {
struct spi_slave slave;
uint32_t max_khz;
uint32_t mode;
struct mx28_ssp_regs *regs;
struct mxs_ssp_regs *regs;
struct mxs_dma_desc *desc;
};
@ -82,7 +82,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
{
struct mxs_spi_slave *mxs_slave;
uint32_t addr;
struct mx28_ssp_regs *ssp_regs;
struct mxs_ssp_regs *ssp_regs;
int reg;
struct mxs_dma_desc *desc;
@ -108,7 +108,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
mxs_slave->slave.cs = cs;
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
mxs_slave->regs = (struct mx28_ssp_regs *)addr;
mxs_slave->regs = (struct mxs_ssp_regs *)addr;
mxs_slave->desc = desc;
ssp_regs = mxs_slave->regs;
@ -136,7 +136,7 @@ void spi_free_slave(struct spi_slave *slave)
int spi_claim_bus(struct spi_slave *slave)
{
struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
uint32_t reg = 0;
mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
@ -159,13 +159,13 @@ void spi_release_bus(struct spi_slave *slave)
{
}
static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}
static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
@ -174,7 +174,7 @@ static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
char *data, int length, int write, unsigned long flags)
{
struct mx28_ssp_regs *ssp_regs = slave->regs;
struct mxs_ssp_regs *ssp_regs = slave->regs;
if (flags & SPI_XFER_BEGIN)
mxs_spi_start_xfer(ssp_regs);
@ -223,14 +223,13 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
}
return 0;
}
static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
char *data, int length, int write, unsigned long flags)
{
struct mxs_dma_desc *desc = slave->desc;
struct mx28_ssp_regs *ssp_regs = slave->regs;
struct mxs_ssp_regs *ssp_regs = slave->regs;
uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
uint32_t cache_data_count;
int dmach;
@ -289,7 +288,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
int len = bitlen / 8;
char dummy;
int write = 0;

16
drivers/usb/host/ehci-mxs.c
View File

@ -39,8 +39,8 @@
#endif
static struct ehci_mxs {
struct mx28_usb_regs *usb_regs;
struct mx28_usbphy_regs *phy_regs;
struct mxs_usb_regs *usb_regs;
struct mxs_usbphy_regs *phy_regs;
} ehci_mxs;
int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
@ -60,8 +60,8 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
return -1;
}
mxs_usb->usb_regs = (struct mx28_usb_regs *)usb_base;
mxs_usb->phy_regs = (struct mx28_usbphy_regs *)phy_base;
mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
return 0;
}
@ -77,8 +77,8 @@ int ehci_hcd_init(void)
uint32_t usb_base, cap_base;
struct mxs_register_32 *digctl_ctrl =
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)
@ -121,8 +121,8 @@ int ehci_hcd_stop(void)
uint32_t tmp;
struct mxs_register_32 *digctl_ctrl =
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)