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arm/km: introduce kmsugp1 target

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KMSUGP1 is from a u-boot perspective (almost) identical to KMNUSA.
The only difference is that the PCIe reset is connected to Kirkwood pin
MPP7_PEX_RST_OUTn, we use a dedicated config flag KM_PCIE_RESET_MPP7.
Such pin should theoretically be handled by the PCIe subsystem
automatically, but this turned out not to be the case.
So simply configure this PIN as a GPIO and issue a pulse manually.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Cc: Valentin Longchamp <valenting.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This commit is contained in:
Gerlando Falauto 2014-02-13 16:43:00 +01:00 committed by Albert ARIBAUD
parent b1c2a7ae32
commit 9c134e189a
4 changed files with 41 additions and 2 deletions
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26
board/keymile/km_arm/fpga_config.c
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@ -189,6 +189,31 @@ int wait_for_fpga_config(void)
return 0;
}
#if defined(KM_PCIE_RESET_MPP7)
#define KM_PEX_RST_GPIO_PIN 7
int fpga_reset(void)
{
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
}
printf("PCIe reset through GPIO7: ");
/* apply PCIe reset via GPIO */
kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
udelay(1000*10);
kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
printf(" done\n");
return 0;
}
#else
#define PRST1 0x4
#define PCIE_RST 0x10
#define TRAFFIC_RST 0x04
@ -219,6 +244,7 @@ int fpga_reset(void)
return 0;
}
#endif
/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
* is available from the Bobcat SPI bus */

4
board/keymile/km_arm/km_arm.c
View File

@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = {
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
#if defined(KM_PCIE_RESET_MPP7)
MPP7_GPO,
#else
MPP7_PEX_RST_OUTn,
#endif
#if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */

1
boards.cfg
View File

@ -173,6 +173,7 @@ Active arm arm926ejs kirkwood keymile km_arm
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>

12
include/configs/km_kirkwood.h
View File

@ -45,11 +45,19 @@
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_NUSA */
#elif defined(CONFIG_KM_NUSA)
/* KM_NUSA / KM_SUGP1 */
#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
# if defined(CONFIG_KM_NUSA)
#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
# elif defined(CONFIG_KM_SUGP1)
#define CONFIG_IDENT_STRING "\nKeymile SUGP1"
#define CONFIG_HOSTNAME kmsugp1
#define KM_PCIE_RESET_MPP7
#endif
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg