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EXYNOS5: Add support for FIMD and DP
Add panel_info structure required by LCD driver and DP panel platdata for SMDK5250. Add GPIO configuration for LCD. Enable FIMD and DP support on SMDK5250. DP Panel size: 2560x1600. We use 16BPP resolution to get LCD console. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chomium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
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}
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#endif
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void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
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#endif /* _DP_INFO_H */
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@ -24,13 +24,16 @@
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <lcd.h>
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#include <netdev.h>
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#include <spi.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/sromc.h>
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#include <asm/arch/dp_info.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -277,3 +280,97 @@ int board_early_init_f(void)
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return err;
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}
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#endif
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void cfg_lcd_gpio(void)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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/* For Backlight */
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s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
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s5p_gpio_set_value(&gpio1->b2, 0, 1);
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/* LCD power on */
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s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
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s5p_gpio_set_value(&gpio1->x1, 5, 1);
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/* Set Hotplug detect for DP */
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s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
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}
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vidinfo_t panel_info = {
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.vl_freq = 60,
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.vl_col = 2560,
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.vl_row = 1600,
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.vl_width = 2560,
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.vl_height = 1600,
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.vl_clkp = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_LOW,
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.vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
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/* wDP panel timing infomation */
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.vl_hspw = 32,
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.vl_hbpd = 80,
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.vl_hfpd = 48,
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.vl_vspw = 6,
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.vl_vbpd = 37,
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.vl_vfpd = 3,
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.vl_cmd_allow_len = 0xf,
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.win_id = 3,
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.cfg_gpio = cfg_lcd_gpio,
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.backlight_on = NULL,
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.lcd_power_on = NULL,
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.reset_lcd = NULL,
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.dual_lcd_enabled = 0,
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.init_delay = 0,
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.power_on_delay = 0,
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.reset_delay = 0,
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.interface_mode = FIMD_RGB_INTERFACE,
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.dp_enabled = 1,
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};
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static struct edp_device_info edp_info = {
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.disp_info = {
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.h_res = 2560,
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.h_sync_width = 32,
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.h_back_porch = 80,
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.h_front_porch = 48,
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.v_res = 1600,
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.v_sync_width = 6,
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.v_back_porch = 37,
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.v_front_porch = 3,
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.v_sync_rate = 60,
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},
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.lt_info = {
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.lt_status = DP_LT_NONE,
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},
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.video_info = {
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.master_mode = 0,
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.bist_mode = DP_DISABLE,
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.bist_pattern = NO_PATTERN,
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.h_sync_polarity = 0,
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.v_sync_polarity = 0,
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.interlaced = 0,
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.color_space = COLOR_RGB,
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.dynamic_range = VESA,
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.ycbcr_coeff = COLOR_YCBCR601,
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.color_depth = COLOR_8,
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},
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};
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static struct exynos_dp_platform_data dp_platform_data = {
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.phy_enable = set_dp_phy_ctrl,
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.edp_dev_info = &edp_info,
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};
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void init_panel_info(vidinfo_t *vid)
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{
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vid->rgb_mode = MODE_RGB_P,
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exynos_set_dp_platform_data(&dp_platform_data);
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}
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@ -297,4 +297,12 @@
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#define CONFIG_SHA1
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#define CONFIG_SHA256
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/* Display */
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#define CONFIG_LCD
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#define CONFIG_EXYNOS_FB
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#define CONFIG_EXYNOS_DP
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#define LCD_XRES 2560
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#define LCD_YRES 1600
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#define LCD_BPP LCD_COLOR16
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#endif /* __CONFIG_H */
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