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ppc4xx: Add 405EP based PMC405DE board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
da799f66ad
commit
99d8b23bc7
@ -172,6 +172,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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PCI405 PPC405GP
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PLU405 PPC405EP
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PMC405 PPC405GP
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PMC405DE PPC405EP
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PMC440 PPC440EPx
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VOH405 PPC405EP
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VOM405 PPC405EP
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1
MAKEALL
1
MAKEALL
@ -238,6 +238,7 @@ LIST_4xx=" \
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PIP405 \
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PLU405 \
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PMC405 \
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PMC405DE \
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PMC440 \
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PPChameleonEVB \
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quad100hd \
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3
Makefile
3
Makefile
@ -1459,6 +1459,9 @@ PLU405_config: unconfig
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PMC405_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
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PMC405DE_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405de esd
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PMC440_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
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53
board/esd/pmc405de/Makefile
Normal file
53
board/esd/pmc405de/Makefile
Normal file
@ -0,0 +1,53 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y = $(BOARD).o
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COBJS-y += ../common/cmd_loadpci.o
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COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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61
board/esd/pmc405de/chip_config.c
Normal file
61
board/esd/pmc405de/chip_config.c
Normal file
@ -0,0 +1,61 @@
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/*
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* (C) Copyright 2008-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/ppc4xx_config.h>
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struct ppc4xx_config ppc4xx_config_val[] = {
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{
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"133",
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"CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
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{
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0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
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}
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},
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{
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"266",
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"CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
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{
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0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
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}
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},
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{
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"333",
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"CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
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{
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0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
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}
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},
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};
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
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23
board/esd/pmc405de/config.mk
Normal file
23
board/esd/pmc405de/config.mk
Normal file
@ -0,0 +1,23 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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521
board/esd/pmc405de/pmc405de.c
Normal file
521
board/esd/pmc405de/pmc405de.c
Normal file
@ -0,0 +1,521 @@
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/*
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* (C) Copyright 2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/4xx_pci.h>
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#include <command.h>
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#include <malloc.h>
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/*
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* PMC405-DE cpld registers
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* - all registers are 8 bit
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* - all registers are on 32 bit addesses
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*/
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struct pmc405de_cpld {
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/* cpld design version */
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u8 version;
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u8 reserved0[3];
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/* misc. status lines */
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u8 status;
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u8 reserved1[3];
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/*
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* gated control flags
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* gate bit(s) must be written with '1' to
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* access control flag
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*/
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u8 control;
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u8 reserved2[3];
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};
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#define CPLD_VERSION_MASK 0x0f
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#define CPLD_CONTROL_POSTLED_N 0x01
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#define CPLD_CONTROL_POSTLED_GATE 0x02
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#define CPLD_CONTROL_RESETOUT_N 0x40
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#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
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DECLARE_GLOBAL_DATA_PTR;
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extern void __ft_board_setup(void *blob, bd_t *bd);
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extern void pll_write(u32 a, u32 b);
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static int wait_for_pci_ready_done;
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static int is_monarch(void);
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static int pci_is_66mhz(void);
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static int board_revision(void);
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static int cpld_revision(void);
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static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
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int board_early_init_f(void)
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{
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u32 pllmr0, pllmr1;
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/*
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* check M66EN and patch PLB:PCI divider for 66MHz PCI
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*
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* fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
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* fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
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* fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
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* fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
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*
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* calling upd_plb_pci_div() may end in calling pll_write() which will
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* do a chip reset and never return.
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*/
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pllmr0 = mfdcr(CPC0_PLLMR0);
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pllmr1 = mfdcr(CPC0_PLLMR1);
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if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
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/* fCPU=333MHz, fPLB=111MHz */
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if (pci_is_66mhz())
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
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else
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
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} else {
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/* fCPU=133|266MHz, fPLB=133MHz */
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if (pci_is_66mhz())
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
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else
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upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
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}
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/*
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* IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register:
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* - set ready timeout to 512 ebc-clks -> ca. 15 us
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* - EBC lines are always driven
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*/
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mtebc(epcr, 0xa8400000);
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return 0;
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}
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static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
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{
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if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
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pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
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}
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int misc_init_r(void)
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{
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int i;
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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struct pmc405de_cpld *cpld =
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(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
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if (!is_monarch()) {
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/* PCI configuration done: release EREADY */
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setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
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setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
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}
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/* turn off POST LED */
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out_8(&cpld->control,
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CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
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/* turn on LEDs: RUN, A, B */
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clrbits_be32(&gpio0->or,
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CONFIG_SYS_GPIO_LEDRUN_N |
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CONFIG_SYS_GPIO_LEDA_N |
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CONFIG_SYS_GPIO_LEDB_N);
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for (i=0; i < 200; i++)
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udelay(1000);
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/* turn off LEDs: A, B */
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setbits_be32(&gpio0->or,
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CONFIG_SYS_GPIO_LEDA_N |
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CONFIG_SYS_GPIO_LEDB_N);
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return (0);
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}
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static int is_monarch(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
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}
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static int pci_is_66mhz(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
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}
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static int board_revision(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
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CONFIG_SYS_GPIO_HWREV_SHIFT);
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}
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static int cpld_revision(void)
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{
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struct pmc405de_cpld *cpld =
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(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
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return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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puts("Board: esd GmbH - PMC-CPU/405-DE");
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gd->board_type = board_revision();
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printf(", Rev 1.%ld, ", gd->board_type);
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if (!is_monarch())
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puts("non-");
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printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
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pci_is_66mhz() ? "66" : "33", cpld_revision());
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return 0;
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}
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static void wait_for_pci_ready(void)
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{
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struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
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int i;
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char *s = getenv("pcidelay");
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/* only wait once */
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if (wait_for_pci_ready_done)
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return;
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/*
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* We have our own handling of the pcidelay variable.
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* Using CONFIG_PCI_BOOTDELAY enables pausing for host
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* and adapter devices. For adapter devices we do not
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* want this.
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*/
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if (s) {
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int ms = simple_strtoul(s, NULL, 10);
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printf("PCI: Waiting for %d ms\n", ms);
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for (i=0; i<ms; i++)
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udelay(1000);
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}
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if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
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printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
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while (1) {
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if (ctrlc()) {
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puts("abort\n");
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break;
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}
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if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
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printf("done\n");
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break;
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}
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}
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}
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wait_for_pci_ready_done = 1;
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}
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/*
|
||||
* Overwrite weak is_pci_host()
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*/
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
char *s;
|
||||
|
||||
if (!is_monarch()) {
|
||||
/*
|
||||
* Overwrite PCI identification when running in
|
||||
* non-monarch mode
|
||||
* This should be moved into pci_target_init()
|
||||
* when it is sometimes available for 405 CPUs
|
||||
*/
|
||||
pci_write_config_word(PCIDEVID_405GP,
|
||||
PCI_SUBSYSTEM_ID,
|
||||
CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
|
||||
pci_write_config_word(PCIDEVID_405GP,
|
||||
PCI_CLASS_SUB_CODE,
|
||||
CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
|
||||
}
|
||||
|
||||
s = getenv("pciscan");
|
||||
if (s == NULL) {
|
||||
if (is_monarch()) {
|
||||
wait_for_pci_ready();
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
if (!strcmp(s, "yes"))
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Overwrite weak pci_pre_init()
|
||||
*
|
||||
* The default implementation enables the 405EP
|
||||
* internal PCI arbiter. We do not want that
|
||||
* on a PMC module.
|
||||
*/
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int rc;
|
||||
|
||||
__ft_board_setup(blob, bd);
|
||||
|
||||
/*
|
||||
* Disable PCI in non-monarch mode.
|
||||
*/
|
||||
if (!is_monarch()) {
|
||||
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
|
||||
"disabled", sizeof("disabled"), 1);
|
||||
if (rc) {
|
||||
printf("Unable to update property status in PCI node, "
|
||||
"err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||
{
|
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
|
||||
|
||||
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO0. */
|
||||
clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO0. */
|
||||
setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32(&gpio0->or) &
|
||||
CONFIG_SYS_GPIO_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
|
||||
if (state < 0) {
|
||||
puts("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf("Write access for device 0x%0x is %sabled.\n",
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable(
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable(
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0)
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"Enable / disable / query EEPROM write access",
|
||||
""
|
||||
);
|
||||
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
|
||||
|
||||
#if defined(CONFIG_PRAM)
|
||||
#include <environment.h>
|
||||
extern env_t *env_ptr;
|
||||
|
||||
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u32 pram, nextbase, base;
|
||||
char *v;
|
||||
u32 param;
|
||||
ulong *lptr;
|
||||
|
||||
v = getenv("pram");
|
||||
if (v)
|
||||
pram = simple_strtoul(v, NULL, 10);
|
||||
else {
|
||||
printf("Error: pram undefined. Please define pram in KiB\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
base = gd->bd->bi_memsize;
|
||||
#if defined(CONFIG_LOGBUFFER)
|
||||
base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
|
||||
#endif
|
||||
/*
|
||||
* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
|
||||
*/
|
||||
param = base - (pram << 10);
|
||||
printf("PARAM: @%08x\n", param);
|
||||
debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
|
||||
|
||||
/* clear entire PA ram */
|
||||
memset((void*)param, 0, (pram << 10));
|
||||
|
||||
/* reserve 4k for pointer field */
|
||||
nextbase = base - 4096;
|
||||
lptr = (ulong*)(base);
|
||||
|
||||
/*
|
||||
* *(--lptr) = item_size;
|
||||
* *(--lptr) = base - item_base = distance from field top;
|
||||
*/
|
||||
|
||||
/* env is first (4k aligned) */
|
||||
nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
|
||||
memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
|
||||
*(--lptr) = CONFIG_ENV_SIZE; /* size */
|
||||
*(--lptr) = base - nextbase; /* offset | type=0 */
|
||||
|
||||
/* free section */
|
||||
*(--lptr) = nextbase - param; /* size */
|
||||
*(--lptr) = (base - param) | 126; /* offset | type=126 */
|
||||
|
||||
/* terminate pointer field */
|
||||
*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
|
||||
*(--lptr) = 0; /* offset=0 -> terminator */
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
painit, 1, 1, do_painit,
|
||||
"prepare PciAccess system",
|
||||
""
|
||||
);
|
||||
#endif /* CONFIG_PRAM */
|
||||
|
||||
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
|
||||
setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
selfreset, 1, 1, do_selfreset,
|
||||
"assert self-reset# signal",
|
||||
""
|
||||
);
|
||||
|
||||
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
struct pmc405de_cpld *cpld =
|
||||
(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
|
||||
|
||||
if (argc > 1) {
|
||||
if (argv[1][0] == '0') {
|
||||
/* assert */
|
||||
printf("PMC-RESETOUT# asserted\n");
|
||||
out_8(&cpld->control,
|
||||
CPLD_CONTROL_RESETOUT_N_GATE);
|
||||
} else {
|
||||
/* deassert */
|
||||
printf("PMC-RESETOUT# deasserted\n");
|
||||
out_8(&cpld->control,
|
||||
CPLD_CONTROL_RESETOUT_N |
|
||||
CPLD_CONTROL_RESETOUT_N_GATE);
|
||||
}
|
||||
} else {
|
||||
printf("PMC-RESETOUT# is %s\n",
|
||||
(in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
|
||||
"inactive" : "active");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
resetout, 2, 1, do_resetout,
|
||||
"assert PMC-RESETOUT# signal",
|
||||
""
|
||||
);
|
||||
133
board/esd/pmc405de/u-boot.lds
Normal file
133
board/esd/pmc405de/u-boot.lds
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
378
include/configs/PMC405DE.h
Normal file
378
include/configs/PMC405DE.h
Normal file
@ -0,0 +1,378 @@
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
|
||||
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */
|
||||
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */
|
||||
#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
|
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_CHIP_CONFIG
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
#define CONFIG_PRAM 0
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
|
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#define CONFIG_UART1_CONSOLE
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED 1
|
||||
#define CONFIG_AUTOBOOT_PROMPT \
|
||||
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
|
||||
#undef CONFIG_AUTOBOOT_DELAY_STR
|
||||
#define CONFIG_AUTOBOOT_STOP_STR " "
|
||||
|
||||
/*
|
||||
* PCI stuff
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
/*
|
||||
* PCI identification
|
||||
*/
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
|
||||
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
|
||||
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
|
||||
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
|
||||
|
||||
#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
|
||||
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
/*
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfe000000
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
|
||||
|
||||
/*
|
||||
* Environment in EEPROM setup
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1
|
||||
#define CONFIG_ENV_OFFSET 0x100
|
||||
#define CONFIG_ENV_SIZE 0x700
|
||||
|
||||
/*
|
||||
* I2C EEPROM (24W16) for environment
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CONFIG_SYS_EEPROM_WREN 1
|
||||
|
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
|
||||
#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
|
||||
|
||||
/*
|
||||
* RTC
|
||||
*/
|
||||
#define CONFIG_RTC_RX8025
|
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
* (max. 55MHZ EBC clock)
|
||||
*/
|
||||
/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x03017200
|
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
|
||||
|
||||
/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xef000000
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x00800000
|
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
/* inside SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
|
||||
/* End of used area in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* GPIO Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
||||
} \
|
||||
}
|
||||
|
||||
#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
|
||||
#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
|
||||
#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
|
||||
#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
|
||||
#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
|
||||
#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
|
||||
#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
|
||||
#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
|
||||
#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
|
||||
#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
|
||||
|
||||
/*
|
||||
* Default speed selection (cpu_plb_opb_ebc) in mhz.
|
||||
* This value will be set if iic boot eprom is disabled.
|
||||
*/
|
||||
#undef CONFIG_SYS_FCPU333MHZ
|
||||
#define CONFIG_SYS_FCPU266MHZ
|
||||
#undef CONFIG_SYS_FCPU133MHZ
|
||||
|
||||
#if defined(CONFIG_SYS_FCPU333MHZ)
|
||||
/*
|
||||
* CPU: 333MHz
|
||||
* PLB/SDRAM/MAL: 111MHz
|
||||
* OPB: 55MHz
|
||||
* EBC: 55MHz
|
||||
* PCI: 55MHz (111MHz on M66EN=1)
|
||||
*/
|
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_FCPU266MHZ)
|
||||
/*
|
||||
* CPU: 266MHz
|
||||
* PLB/SDRAM/MAL: 133MHz
|
||||
* OPB: 66MHz
|
||||
* EBC: 44MHz
|
||||
* PCI: 44MHz (66MHz on M66EN=1)
|
||||
*/
|
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_FCPU133MHZ)
|
||||
/*
|
||||
* CPU: 133MHz
|
||||
* PLB/SDRAM/MAL: 133MHz
|
||||
* OPB: 66MHz
|
||||
* EBC: 44MHz
|
||||
* PCI: 44MHz (66MHz on M66EN=1)
|
||||
*/
|
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user