mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-29 15:43:44 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge with /home/wd/git/u-boot/master

Browse Source
This commit is contained in:
Wolfgang Denk 2006-08-07 23:21:52 +02:00
commit 98280e3d43
168 changed files with 16270 additions and 6012 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

195
CHANGELOG
View File

@ -2,6 +2,193 @@
Changes since U-Boot 1.1.4:
======================================================================
* Prevent USB commands from working when USB is stopped.
* Add rudimentary handling of alternate settings of USB interfaces.
This is in order to fix issues with some USB sticks timing out
during initialization. Some code readability improvements.
* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
Please see doc/README.bamboo for details.
Patch by Stefan Roese, 27 Jul 2006
* Fix CONFIG_CMDLINE_EDITING implementation
Patch by Stefan Roese, 27 Jul 2006
* Fix preboot message on TQM5200 after switching to hush parser.
* MCC200: set default configuration to low_boot DDR,
and support for configurable options high_boot and/or SDRAM.
* Add support for 256 MB SDRAM on CPU87
Patch by Josef Wagner, 25 Nov 2005
* Add configuration for cam5200 board (based on TQM5200S).
* More code cleanup
* Disabled kvme080 board in MAKEALL because of build problems.
* Code cleanup
* Update NetStar board
Patch by Ladislav Michl, 03 Nov 2005
* Make code better readable.
Patch by Ladislav Michl, 14 Sep 2005
* Enable initrd ATAG for xm250 board.
Patch by Josef Wagner, 05 Sep 2005
* Add readline cmdline-editing extension
Patch by JinHua Luo, 01 Sep 2005
* Add support for friendly-arm SBC-2410X board
Patch by JinHua Luo, 01 Sep 2005
* Fix multi-part image support on i386 platform.
Patch by David Updegraff, 19 Aug 2005
* Add support for KVME080 board
Patch by Sangmoon Kim, 18 Aug 2005
* Fix MIPS LE build problem
Patch by Matej Kupljen, 10 Aug 2005
* Check argument count in "mii" command.
Problem pointed out by Andrew Dyer, 13 Jun 2005
* Cleanup TQM5200 board configurations:
- make highboot configurations use environment at high end, too,
to avoid flash fragmentation
- always use redundand environment
- don't enable video code for modules without graphics controller
- provide useful (though different) mtdparts settings
- get rid of CONFIG_CS_AUTOCONF which was always set anyway
* Extend mkconfig tool to print more useful target name
* Add support for high-boot on TQM5200 and TQM5200S boards.
Hint: the CPLD on the TQM5200 must be programmed with a software
version supporting the high boot option! The new TQM5200S is
already supporting this option. On the TQM5200 this option will be
supported in configurations with MPC5200 rev B processors.
To actually "high boot", set jumper X30 on the STK52xx.
Patch by Martin Krause, 12 Jul 2006
* Add support for new TQM5200 revisions
- Support for TQM5200S (short version without graphic controller)
- Support for modules with 'N' type S29GL128N Spansion flashes
(requires changes to flash layout)
- Support for MPC5200B cpu (mostly support for second SDRAM bank)
Patch by Martin Krause, 07 Jul 2006
* Fix support for PS/2 keyboard on TQM85xx boards
The PS/2 keyobard driver for the TQM85xx modules only supports the
internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
include a DUART, the TQM8560 modules can't be used with the PS/2
keyboard controller on the STK85xx board.
The PS/2 keyboard driver should work with the modules TQM8540,
TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
Make sure the PS/2 controller on the STK85xx is programmed. Jumper
settings: X66 1-2, 9-10; X61 2-3
Patch by Martin Krause, 21 Jun 2006
* Adjust RTC century handling on STK52xx board to match Linux driver.
Patch by Martin Krause, 12 Jun 2006
* Adjust filenames for USB update images on TRAB board.
During an automatic update via USB stick, U-Boot searches for
images with the name "firmware.img" and "kernel.img". This names
are now changed to "firmw_01.img" and "kernl_01.img". This is done,
to prevent updates of new boards (with the new macronics "c" step
flashes) with old, incompatible firmware or kernel versions.
Patch by Martin Krause, 21 Jun 2006
* Bugfix in VFD routine on TRAB board.
Make sure upper lext pixel can be set to blue, too
(so far only red was possible).
Patch by Martin Krause, 15 Feb 2006
* Enable buffered flash writes for TB5200 board.
* Fix some bugs in TRAB board flash driver.
- increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- remove "Unlock Bypass" mode, because macronix flashes do not support
this mode officially
- fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
for Intel compatible flashes, not for AMD compatible.
Patch by Martin Krause, 15 Feb 2006
* Add additional error messages to flash driver on TRAB board
(for erase errors and timeout errors)
Patch by Martin Krause, 14 Feb 2006
* Add support for TB5200 board
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006
* Enable buffered flash writes for TQM5200 board.
* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
* Add support for TQM885D board.
Patch by Martin Krause, 20 Mar 2006
* Fix FEC initialisation: All MII configuration is done via FEC1
registers, but MII_SPEED was configured according to FEC used. So
if only FEC2 was used, this caused the real MII_SPEED register in
FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
Fix: always configure MII_SPEED on FEC1 only.
Patch by Markus Klotzbuecher, 12 Jul 2006
* Add support for SPC1920 board.
Patch by Markus Klotzbuecher, 12 Jul 2006
* MCC200 board: support console on any one of the Quad UART ports.
* Fix error in flash protection calculation on MCC200 board.
* Major PCMCIA Cleanup to make code better readable and maintainable.
Notes:
- Board-dependend code for RPXLITE and RPXCLASSIC-based boards
placed to the drivers/rpx_pmcia.c file to avoid duplication.
Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- drivers/i82365.c has been split into two parts located at
board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
the only boards using CONFIG_82365).
- Changes were tested for clean build and *very* *few* boards.
* Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
* Bring yucca config more in line with other AMCC boards.
* Add AMCC bamboo board to MAKEALL build script.
* Fix AMCC bamboo eval board compilation errors.
* Add system memory to the PCI region list for AMCC PPC44x CPUs.
Enabled it for Yucca board.
* Cleanup config file and bootup output for Yucca board.
* Fix CONFIG_440_GX define usage.
* Remove autogenerated bmp_logo.h file.
* Add support for AMCC 440SPe CPU based eval board (Yucca).
* Call serial_initialize() before first debug() is used.
* Code cleanup
* Various USB related patches
@ -21,14 +208,14 @@ Changes since U-Boot 1.1.4:
* VoiceBlue update: use new MTD flash partitioning methods, use more
reasonable TEXT_BASE, update default environment and enable keyed
autoboot.
Patch by Ladislav Michl, 16. Aug 2005
Patch by Ladislav Michl, 16. Aug 2005
* Add forgotten changes for the PLEB 2 Board.
Patch by David Snowdon, 13. Aug 2005
* Add support for wrPPMC7xx/74xx boards
Patch by Richard Danter, 12 Aug 2005
* Add support for gth2 board
Patch by Thomas Lange, Aug 11 2005
@ -50,7 +237,7 @@ Changes since U-Boot 1.1.4:
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006
* Fix DDR6 errata on TQM834x boards
Patch by Thomas Waehner, 07 Mar 2006
@ -67,7 +254,7 @@ Changes since U-Boot 1.1.4:
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
In tsc2000_read_channel() the delay after setting the multiplexer
In tsc2000_read_channel() the delay after setting the multiplexer
to a temperature channel is increased from 1,5 ms to 10 ms. This
is to allow the multiplexer inputs to stabilize after huge steps
of the input signal level.

1
CREDITS
View File

@ -233,6 +233,7 @@ D: Port to Windriver ppmc8260 board
N: Sangmoon Kim
E: dogoil@etinsys.com
D: Support for debris board
D: Support for KVME080 board
N: Frederick W. Klatt
E: fred.klatt@windriver.com

1
MAINTAINERS
View File

@ -197,6 +197,7 @@ Brad Kemp <Brad.Kemp@seranoa.com>
Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
KVME080 MPC8245
Thomas Lange <thomas@corelatus.se>

47
MAKEALL
View File

@ -27,14 +27,14 @@ LIST_5xx=" \
LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 icecube_5100 \
icecube_5200 lite5200b mcc200 o2dnt \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200 \
pf5200 PM520 TB5200 Total5100 \
Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
TQM5200S \
"
#########################################################################
## MPC8xx Systems
#########################################################################
LIST_8xx=" \
Adder87x GENIETV MBX860T R360MPI \
AdderII GTH MHPC RBC823 \
@ -44,16 +44,18 @@ LIST_8xx=" \
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
EP88x IVML24_256 NETTA_ISDN SPD823TS \
ESTEEM192E IVMS8 NETVIA svm_sc8xx \
ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
FADS823 IVMS8_256 NX823 TOP860 \
FADS850SAR KUP4K pcu_e TQM823L \
FADS860T KUP4X QS823 TQM823L_LCD \
FLAGADM LANTEC QS850 TQM850L \
FPS850L lwmon QS860T TQM855L \
GEN860T MBX quantum TQM860L \
GEN860T_SC uc100 \
EP88x IVML24_256 NETTA_ISDN spc1920 \
ESTEEM192E IVMS8 NETVIA SPD823TS \
ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \
FADS823 IVMS8_256 NX823 SXNI855T \
FADS850SAR KUP4K pcu_e TOP860 \
FADS860T KUP4X QS823 TQM823L \
FLAGADM LANTEC QS850 TQM823L_LCD \
FPS850L lwmon QS860T TQM850L \
GEN860T MBX quantum TQM855L \
GEN860T_SC TQM860L \
TQM885D \
uc100 \
v37 \
"
@ -72,10 +74,10 @@ LIST_4xx=" \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 pcs440ep \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite \
yellowstone yosemite yucca bamboo \
"
#########################################################################
@ -93,9 +95,9 @@ LIST_8220=" \
LIST_824x=" \
A3000 barco BMW CPC45 \
CU824 debris eXalion HIDDEN_DRAGON \
MOUSSE MUSENKI MVBLUE OXC \
PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
SL8245 utx8245 \
MOUSSE MUSENKI MVBLUE \
OXC PN62 Sandpoint8240 Sandpoint8245 \
sbc8240 SL8245 utx8245 \
"
#########################################################################
@ -179,9 +181,10 @@ LIST_ARM9=" \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 netstar omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
versatile versatileab versatilepb voiceblue
omap1610h2 omap1610inn omap730p2 sbc2410x \
scb9328 smdk2400 smdk2410 trab \
VCMA9 versatile versatileab versatilepb \
voiceblue \
"
#########################################################################

77
Makefile
View File

@ -7,7 +7,7 @@
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
@ -323,13 +323,25 @@ lite5200b_LOWBOOT_config: unconfig
@./mkconfig -a IceCube ppc mpc5xxx icecube
mcc200_config \
mcc200_lowboot_config: unconfig
mcc200_SDRAM \
mcc200_highboot \
mcc200_highboot_SDRAM: unconfig
@ >include/config.h
@[ -z "$(findstring lowboot_,$@)" ] || \
{ echo "TEXT_BASE = 0xFC000000" >board/mcc200/config.tmp ; \
echo "... with lowboot configuration" ; \
@[ -n "$(findstring highboot,$@)" ] || \
{ echo "... with lowboot configuration" ; \
}
@./mkconfig mcc200 ppc mpc5xxx mcc200
@[ -z "$(findstring highboot,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \
echo "... with highboot configuration" ; \
}
@[ -n "$(findstring _SDRAM,$@)" ] || \
{ echo "... with DDR" ; \
}
@[ -z "$(findstring _SDRAM,$@)" ] || \
{ echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \
echo "... with SDRAM" ; \
}
@./mkconfig -a mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@./mkconfig o2dnt ppc mpc5xxx o2dnt
@ -356,15 +368,21 @@ smmaco4_config: unconfig
@./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
spieval_config: unconfig
@echo "#define CONFIG_CS_AUTOCONF">>include/config.h
@echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200
TB5200_B_config \
TB5200_config: unconfig
@[ -z "$(findstring _B,$@)" ] || \
{ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
echo "... with MPC5200B processor" ; \
}
@./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
@./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
Total5100_config \
Total5200_config \
@ -395,20 +413,39 @@ Total5200_Rev2_lowboot_config: unconfig
@./mkconfig -a Total5200 ppc mpc5xxx total5200
TQM5200_config \
TQM5200_B_config \
TQM5200_B_HIGHBOOT_config \
TQM5200S_config \
TQM5200S_HIGHBOOT_config \
TQM5200_STK100_config \
cam5200_config \
MiniFAP_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>include/config.h ; \
echo "#define CONFIG_TQM5200S" >>include/config.h ; \
echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
echo "... TQM5200S on Cam5200" ; \
}
@[ -z "$(findstring STK100,$@)" ] || \
{ echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
echo "... on a STK52XX.100 base board" ; \
}
@echo "#define CONFIG_CS_AUTOCONF">>include/config.h ;
@echo "... with automatic CS configuration" ;
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
@[ -z "$(findstring TQM5200_B,$@)" ] || \
{ echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
}
@[ -z "$(findstring TQM5200S,$@)" ] || \
{ echo "#define CONFIG_TQM5200S" >>include/config.h ; \
echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
}
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \
}
@./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
## MPC8xx Systems
@ -708,6 +745,9 @@ RRvision_LCD_config: unconfig
SM850_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
spc1920_config:
@./mkconfig $(@:_config=) ppc mpc8xx spc1920
SPD823TS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
@ -745,6 +785,7 @@ TQM855M_config \
TQM860M_config \
TQM862M_config \
TQM866M_config \
TQM885D_config \
virtlab2_config: unconfig
@ >include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
@ -984,6 +1025,9 @@ yosemite_config: unconfig
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
yucca_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
#########################################################################
## MPC8220 Systems
#########################################################################
@ -1034,6 +1078,9 @@ eXalion_config: unconfig
HIDDEN_DRAGON_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
kvme080_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
MOUSSE_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x mousse
@ -1457,7 +1504,7 @@ ZUMA_config: unconfig
ppmc7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
#========================================================================
# ARM
#========================================================================
@ -1591,6 +1638,9 @@ omap730p2_cs3boot_config : unconfig
fi;
@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
sbc2410x_config: unconfig
@./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
@ -1971,6 +2021,7 @@ clean:
rm -f board/netstar/*.srec board/netstar/*.bin
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
rm -f include/bmp_logo.h
clobber: clean
find . -type f \( -name .depend \

8
README
View File

@ -306,7 +306,7 @@ The following options need to be configured:
CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
@ -1552,6 +1552,12 @@ The following options need to be configured:
of the backslashes before semicolons and special
symbols.
- Commandline Editing and History:
CONFIG_CMDLINE_EDITING
Enable editiong and History functions for interactive
commandline input operations
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS

8
board/MAI/bios_emulator/scitech/src/pm/win32/event.c
View File

@ -147,14 +147,14 @@ void _EVT_pumpMessages(void)
if (EVT.oldMove != -1) {
EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */
EVT.evtq[EVT.oldMove].where_y = evt.where_y;
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */
/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */
/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */
evt.what = 0;
}
else {
EVT.oldMove = EVT.freeHead; /* Save id of this move event */
/* evt.relative_x = mickeyX; // TODO! */
/* evt.relative_y = mickeyY; // TODO! */
/* evt.relative_x = mickeyX; / / TODO! */
/* evt.relative_y = mickeyY; / / TODO! */
}
}
else

3
board/Marvell/include/core.h
View File

@ -91,7 +91,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
#define _1G 0x40000000
#define _2G 0x80000000
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
#endif
/* Little to Big endian conversion macros */

2
board/amcc/bamboo/bamboo.c
View File

@ -435,7 +435,7 @@ long int initdram (int board_type)
*/
init_spd_array();
dram_size = spd_sdram (0);
dram_size = spd_sdram();
return dram_size;
}

13
board/amcc/bamboo/bamboo.h
View File

@ -283,10 +283,8 @@
/*----------------------------------------------------------------------------+
| PPC440EP GPIOs addresses.
+----------------------------------------------------------------------------*/
#define GPIO0_BASE 0xEF600B00
#define GPIO0_REAL 0xEF600B00
#define GPIO1_BASE 0xEF600C00
#define GPIO1_REAL 0xEF600C00
/* Offsets */
@ -331,17 +329,6 @@
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef struct { unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
/*----------------------------------------------------------------------------+
| XX XX
|

4
board/amcc/bamboo/config.mk
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2002
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFF80000
TEXT_BASE = 0xFFFA0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1

4
board/amcc/yellowstone/yellowstone.c
View File

@ -313,13 +313,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);

4
board/amcc/yosemite/yosemite.c
View File

@ -309,13 +309,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);

47
board/amcc/yucca/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o cmd_yucca.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

288
board/amcc/yucca/cmd_yucca.c Normal file
View File

@ -0,0 +1,288 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* hacked for evb440spe
*/
#include <common.h>
#include <command.h>
#include "yucca.h"
#include <i2c.h>
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
/* ------------------------------------------------------------------------- */
int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
return setBootStrapClock (cmdtp, 1, flag, argc, argv);
}
/* ------------------------------------------------------------------------- */
/* Modify memory.
*
* Syntax:
* evb440spe wrclk prom0,prom1
*/
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
int argc, char *argv[])
{
uchar chip;
ulong data;
int nbytes;
extern char console_buffer[];
char sysClock[4];
char cpuClock[4];
char plbClock[4];
char pcixClock[4];
if (argc < 3) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;
else
chip = IIC0_ALT_BOOTPROM_ADDR;
do {
printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0))
nbytes=0;
strcpy(sysClock, console_buffer);
} while (nbytes == 0);
do {
if (strcmp(sysClock, "66") == 0) {
printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
} else {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
}
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
} else {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "500") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
}
strcpy(cpuClock, console_buffer);
} while (nbytes == 0);
if (strcmp(cpuClock, "500") == 0){
strcpy(plbClock, "166");
} else if (strcmp(cpuClock, "533") == 0){
strcpy(plbClock, "133");
} else {
do {
if (strcmp(cpuClock, "400") == 0)
printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0)
printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
#endif
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
#endif
strcpy(plbClock, console_buffer);
} while (nbytes == 0);
}
do {
printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0) &
(strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
strcpy(pcixClock, console_buffer);
} while (nbytes == 0);
printf("\nsys clk = %sMhz\n", sysClock);
printf("cpu clk = %sMhz\n", cpuClock);
printf("plb clk = %sMhz\n", plbClock);
printf("Pci-X clk = %sMhz\n", pcixClock);
do {
printf("\npress [y] to write I2C bootstrap \n");
printf("or [n] to abort. \n");
printf("Don't forget to set board switches \n");
printf("according to your choice before re-starting \n");
printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "n") == 0)
return 0;
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
if ((strcmp(cpuClock, "500") == 0))
data = 0x8778f2c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x84706206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x847062c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x85708206;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8570a256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x8570a206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x00000701;
if (strcmp(pcixClock, "66") == 0)
data = 0x00000601;
if (strcmp(pcixClock, "100") == 0)
data = 0x00000501;
if (strcmp(pcixClock, "133") == 0)
data = 0x00000401;
if (strcmp(plbClock, "166") == 0)
data = data | 0x05950000;
else
data = data | 0x05A50000;
#ifdef DEBUG
printf(" pin strap1 to write in i2c = %x\n", data);
#endif /* DEBUG */
udelay(1000);
if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap1 in %s\n", argv[2]);
return 0;
}
U_BOOT_CMD(
evb440spe, 3, 1, do_evb440spe,
"evb440spe - program the serial device strap\n",
"wrclk [prom0|prom1] - program the serial device strap\n"
);

42
board/amcc/yucca/config.mk Normal file
View File

@ -0,0 +1,42 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440SPe Reference Platform (yucca) board
#
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xfffb0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

1054
board/amcc/yucca/flash.c Normal file
View File

File diff suppressed because it is too large Load Diff

104
board/amcc/yucca/init.S Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
#define TLB2(a) ((a) & 0x00000fbf)
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ;\
0: mflr r0 ;\
mtlr r1 ;\
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

157
board/amcc/yucca/u-boot.lds Normal file
View File

@ -0,0 +1,157 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

146
board/amcc/yucca/u-boot.lds.debug Normal file
View File

@ -0,0 +1,146 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1096
board/amcc/yucca/yucca.c Normal file
View File

File diff suppressed because it is too large Load Diff

363
board/amcc/yucca/yucca.h Normal file
View File

@ -0,0 +1,363 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __YUCCA_H_
#define __YUCCA_H_
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define TMR_FREQ_EXT 25000000
#define BOARD_UART_CLOCK 11059200
#define BOARD_OPTION_SELECTED 1
#define BOARD_OPTION_NOT_SELECTED 0
#define ENGINEERING_CLOCK_CHECKING "clk_chk"
#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
#define ENGINEERING_CLOCK_CHECKING_DATA 1
#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
/* ethernet definition */
#define MAX_ENETMODE_PARM 3
#define ENETMODE_NEG 0
#define ENETMODE_SPEED 1
#define ENETMODE_DUPLEX 2
#define ENETMODE_AUTONEG 0
#define ENETMODE_NO_AUTONEG 1
#define ENETMODE_10 2
#define ENETMODE_100 3
#define ENETMODE_1000 4
#define ENETMODE_HALF 5
#define ENETMODE_FULL 6
#define NUM_TLB_ENTRIES 64
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK 0xF0000000
#define TLB_16MB_ALIGN_MASK 0xFF000000
#define TLB_1MB_ALIGN_MASK 0xFFF00000
#define TLB_256KB_ALIGN_MASK 0xFFFC0000
#define TLB_64KB_ALIGN_MASK 0xFFFF0000
#define TLB_16KB_ALIGN_MASK 0xFFFFC000
#define TLB_4KB_ALIGN_MASK 0xFFFFF000
#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
#define TLB_256MB_SIZE 0x10000000
#define TLB_16MB_SIZE 0x01000000
#define TLB_1MB_SIZE 0x00100000
#define TLB_256KB_SIZE 0x00040000
#define TLB_64KB_SIZE 0x00010000
#define TLB_16KB_SIZE 0x00004000
#define TLB_4KB_SIZE 0x00001000
#define TLB_1KB_SIZE 0x00000400
#define TLB_WORD0_EPN_MASK 0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK 0x00000200
#define TLB_WORD0_V_ENABLE 0x00000200
#define TLB_WORD0_V_DISABLE 0x00000000
#define TLB_WORD0_TS_MASK 0x00000100
#define TLB_WORD0_TS_1 0x00000100
#define TLB_WORD0_TS_0 0x00000000
#define TLB_WORD0_SIZE_MASK 0x000000F0
#define TLB_WORD0_SIZE_1KB 0x00000000
#define TLB_WORD0_SIZE_4KB 0x00000010
#define TLB_WORD0_SIZE_16KB 0x00000020
#define TLB_WORD0_SIZE_64KB 0x00000030
#define TLB_WORD0_SIZE_256KB 0x00000040
#define TLB_WORD0_SIZE_1MB 0x00000050
#define TLB_WORD0_SIZE_16MB 0x00000070
#define TLB_WORD0_SIZE_256MB 0x00000090
#define TLB_WORD0_TPAR_MASK 0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD1_RPN_MASK 0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK 0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0 0x00000000
#define TLB_WORD1_PAR1_1 0x00000100
#define TLB_WORD1_PAR1_2 0x00000200
#define TLB_WORD1_PAR1_3 0x00000300
#define TLB_WORD1_ERPN_MASK 0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD2_PAR2_MASK 0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0 0x00000000
#define TLB_WORD2_PAR2_1 0x40000000
#define TLB_WORD2_PAR2_2 0x80000000
#define TLB_WORD2_PAR2_3 0xC0000000
#define TLB_WORD2_U0_MASK 0x00008000
#define TLB_WORD2_U0_ENABLE 0x00008000
#define TLB_WORD2_U0_DISABLE 0x00000000
#define TLB_WORD2_U1_MASK 0x00004000
#define TLB_WORD2_U1_ENABLE 0x00004000
#define TLB_WORD2_U1_DISABLE 0x00000000
#define TLB_WORD2_U2_MASK 0x00002000
#define TLB_WORD2_U2_ENABLE 0x00002000
#define TLB_WORD2_U2_DISABLE 0x00000000
#define TLB_WORD2_U3_MASK 0x00001000
#define TLB_WORD2_U3_ENABLE 0x00001000
#define TLB_WORD2_U3_DISABLE 0x00000000
#define TLB_WORD2_W_MASK 0x00000800
#define TLB_WORD2_W_ENABLE 0x00000800
#define TLB_WORD2_W_DISABLE 0x00000000
#define TLB_WORD2_I_MASK 0x00000400
#define TLB_WORD2_I_ENABLE 0x00000400
#define TLB_WORD2_I_DISABLE 0x00000000
#define TLB_WORD2_M_MASK 0x00000200
#define TLB_WORD2_M_ENABLE 0x00000200
#define TLB_WORD2_M_DISABLE 0x00000000
#define TLB_WORD2_G_MASK 0x00000100
#define TLB_WORD2_G_ENABLE 0x00000100
#define TLB_WORD2_G_DISABLE 0x00000000
#define TLB_WORD2_E_MASK 0x00000080
#define TLB_WORD2_E_ENABLE 0x00000080
#define TLB_WORD2_E_DISABLE 0x00000000
#define TLB_WORD2_UX_MASK 0x00000020
#define TLB_WORD2_UX_ENABLE 0x00000020
#define TLB_WORD2_UX_DISABLE 0x00000000
#define TLB_WORD2_UW_MASK 0x00000010
#define TLB_WORD2_UW_ENABLE 0x00000010
#define TLB_WORD2_UW_DISABLE 0x00000000
#define TLB_WORD2_UR_MASK 0x00000008
#define TLB_WORD2_UR_ENABLE 0x00000008
#define TLB_WORD2_UR_DISABLE 0x00000000
#define TLB_WORD2_SX_MASK 0x00000004
#define TLB_WORD2_SX_ENABLE 0x00000004
#define TLB_WORD2_SX_DISABLE 0x00000000
#define TLB_WORD2_SW_MASK 0x00000002
#define TLB_WORD2_SW_ENABLE 0x00000002
#define TLB_WORD2_SW_DISABLE 0x00000000
#define TLB_WORD2_SR_MASK 0x00000001
#define TLB_WORD2_SR_ENABLE 0x00000001
#define TLB_WORD2_SR_DISABLE 0x00000000
/*----------------------------------------------------------------------------+
| Board specific defines.
+----------------------------------------------------------------------------*/
#define NONCACHE_MEMORY_SIZE (64*1024)
#define NONCACHE_AREA0_ENDOFFSET (64*1024)
#define NONCACHE_AREA1_ENDOFFSET (32*1024)
#define FLASH_SECTORSIZE 0x00010000
/* SDRAM MICRON */
#define SDRAM_MICRON 0x2C
#define SDRAM_TRUE 1
#define SDRAM_FALSE 0
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXBANKSPERDIMM 2
#define MAXRANKSPERDIMM 2
#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
#define ERROR_STR_LENGTH 256
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
/*----------------------------------------------------------------------------+
| SDR Configuration registers
+----------------------------------------------------------------------------*/
/* Serial Device Strap Reg 0 */
#define sdr_pstrp0 0x0040
#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
/* Serial Device Enabled - Addr = 0xA8 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
/* Serial Device Enabled - Addr = 0xA4 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
/* Pin Straps Reg */
#define SDR0_PSTRP0 0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
/* fpgareg - defines are in include/config/YUCCA.h */
#define SDR0_CUST0_ENET3_MASK 0x00000080
#define SDR0_CUST0_ENET3_COPPER 0x00000000
#define SDR0_CUST0_ENET3_FIBER 0x00000080
#define SDR0_CUST0_RGMII3_MASK 0x00000070
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
#define SDR0_CUST0_RGMII3_DISAB 0x00000000
#define SDR0_CUST0_RGMII3_RTBI 0x00000040
#define SDR0_CUST0_RGMII3_RGMII 0x00000050
#define SDR0_CUST0_RGMII3_TBI 0x00000060
#define SDR0_CUST0_RGMII3_GMII 0x00000070
#define SDR0_CUST0_ENET2_MASK 0x00000008
#define SDR0_CUST0_ENET2_COPPER 0x00000000
#define SDR0_CUST0_ENET2_FIBER 0x00000008
#define SDR0_CUST0_RGMII2_MASK 0x00000007
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
#define SDR0_CUST0_RGMII2_DISAB 0x00000000
#define SDR0_CUST0_RGMII2_RTBI 0x00000004
#define SDR0_CUST0_RGMII2_RGMII 0x00000005
#define SDR0_CUST0_RGMII2_TBI 0x00000006
#define SDR0_CUST0_RGMII2_GMII 0x00000007
#define ONE_MILLION 1000000
#define ONE_BILLION 1000000000
/*----------------------------------------------------------------------------+
| X
| XX
| XX XXX XXXXX XX XXX XXXXX
| XX XX X XXX XX XX
| XX XX XXXXXX XX XX
| XX XX X XX XX XX XX
| XXX XX XXXXX X XXXX XXX
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/
typedef enum config_selection {
CONFIG_NOT_SELECTED,
CONFIG_SELECTED
} config_selection_t;
typedef enum config_list {
UART2_IN_SERVICE_MODE,
CPU_TRACE_MODE,
UART1_CTS_RTS,
CONFIG_NB
} config_list_t;
#define MAX_CONFIG_SELECT_NB 3
#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
#define BOARD_INFO_CPU_TRACE_MODE 2
#define BOARD_INFO_UART1_CTS_RTS_MODE 4
void force_bup_config_selection(config_selection_t *confgi_select_P);
void update_config_selection_table(config_selection_t *config_select_P);
void display_config_selection(config_selection_t *config_select_P);
/*----------------------------------------------------------------------------+
| XX
|
| XXXX XX XXX XXX XXXX
| XX XX XX XX XX XX
| XX XXX XX XX XX XX XX
| XX XX XXXXX XX XX XX
| XXXX XX XXXX XXXX
| XXXX
|
|
|
| +------------------------------------------------------------------+
| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
| +----------------------+------------------+-----+------------+-----+
| | | | | | |
| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
| | GPIO0_8 | PERREADY | I | TRCES4 | NA |
| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
| | GPIO0_16 | IRQ5 | I | UART2RX | I |
| | GPIO0_17 | PERBE0_N | O | UART2TX | O |
| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
| | GPIO0_30 | UART1RX | I | NA | NA |
| | GPIO0_31 | UART1TX | O | NA | NA |
| | | | | | |
| +----------------------+------------------+-----+------------+-----+
|
+----------------------------------------------------------------------------*/
unsigned long auto_calc_speed(void);
/*----------------------------------------------------------------------------+
| Prototypes
+----------------------------------------------------------------------------*/
void print_evb440spe_info(void);
int onboard_pci_arbiter_selected(int core_pci);
#ifdef __cplusplus
}
#endif
#endif /* __YUCCA_H_ */

2
board/atc/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o ti113x.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

637
board/atc/ti113x.c Normal file
View File

@ -0,0 +1,637 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
*
* Lots of code copied from:
*
* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
#ifdef CONFIG_I82365
#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>
#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#include <pcmcia/ti113x.h>
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
{0, 0}
};
#define CYCLE_TIME 120
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif
typedef struct socket_info_t {
pci_dev_t dev;
u_short bcr;
u_char pci_lat, cb_lat, sub_bus, cache;
u_int cb_phys;
socket_cap_t cap;
u_short type;
u_int flags;
ti113x_state_t state;
} socket_info_t;
static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;
/*====================================================================*/
/* Some PCI shortcuts */
static int pci_readb (socket_info_t * s, int r, u_char * v)
{
return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
return pci_write_config_word (s->dev, r, v);
}
static int pci_readl (socket_info_t * s, int r, u_int * v)
{
return pci_read_config_dword (s->dev, r, v);
}
static int pci_writel (socket_info_t * s, int r, u_int v)
{
return pci_write_config_dword (s->dev, r, v);
}
/*====================================================================*/
#define cb_readb(s, r) readb((s)->cb_phys + (r))
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
return cb_readb (s, 0x0800 + reg);
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
cb_writeb (s, 0x0800 + reg, data);
}
static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) | mask);
}
static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) & ~mask);
}
#if 0 /* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
u_char d = i365_get (s, reg);
i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}
static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif /* not used */
static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
i365_set (s, reg, data & 0xff);
i365_set (s, reg + 1, data >> 8);
}
/*======================================================================
Code to save and restore global state information for TI 1130 and
TI 1131 controllers, and to set and report global configuration
options.
======================================================================*/
static void ti113x_get_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
}
static void ti113x_set_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
pci_writel (s, TI12XX_IRQMUX, p->irqmux);
i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
}
static u_int ti113x_set_opts (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
u_int mask = 0xffff;
p->cardctl &= ~TI113X_CCR_ZVENABLE;
p->cardctl |= TI113X_CCR_SPKROUTEN;
return mask;
}
/*======================================================================
Routines to handle common CardBus options
======================================================================*/
/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
static void cb_get_state (socket_info_t * s)
{
pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}
static void cb_set_state (socket_info_t * s)
{
pci_writel (s, CB_LEGACY_MODE_BASE, 0);
pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
pci_writew (s, PCI_COMMAND, CMD_DFLT);
pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}
static void cb_set_opts (socket_info_t * s)
{
if (s->cache == 0)
s->cache = 8;
if (s->pci_lat == 0)
s->pci_lat = 0xa8;
if (s->cb_lat == 0)
s->cb_lat = 0xb0;
}
/*======================================================================
Power control for Cardbus controllers: used both for 16-bit and
Cardbus cards.
======================================================================*/
static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
u_int reg = 0;
/* restart card voltage detection if it seems appropriate */
if ((state->Vcc == 0) && (state->Vpp == 0) &&
!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
switch (state->Vcc) {
case 0:
reg = 0;
break;
case 33:
reg = CB_SC_VCC_3V;
break;
case 50:
reg = CB_SC_VCC_5V;
break;
default:
return -1;
}
switch (state->Vpp) {
case 0:
break;
case 33:
reg |= CB_SC_VPP_3V;
break;
case 50:
reg |= CB_SC_VPP_5V;
break;
case 120:
reg |= CB_SC_VPP_12V;
break;
default:
return -1;
}
if (reg != cb_readl (s, CB_SOCKET_CONTROL))
cb_writel (s, CB_SOCKET_CONTROL, reg);
return 0;
}
/*======================================================================
Generic routines to get and set controller options
======================================================================*/
static void get_bridge_state (socket_info_t * s)
{
ti113x_get_state (s);
cb_get_state (s);
}
static void set_bridge_state (socket_info_t * s)
{
cb_set_state (s);
i365_set (s, I365_GBLCTL, 0x00);
i365_set (s, I365_GENCTL, 0x00);
ti113x_set_state (s);
}
static void set_bridge_opts (socket_info_t * s)
{
ti113x_set_opts (s);
cb_set_opts (s);
}
/*====================================================================*/
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
#define pd67_ext_get(s, r) \
(i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
static int i365_get_status (socket_info_t * s, u_int * value)
{
u_int status;
status = i365_get (s, I365_IDENT);
status = i365_get (s, I365_STATUS);
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
} else {
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
}
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
*value |= (status & I365_CS_READY) ? SS_READY : 0;
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
status = cb_readl (s, CB_SOCKET_STATE);
*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
/* For now, ignore cards with unsupported voltage keys */
if (*value & SS_XVCARD)
*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
return 0;
} /* i365_get_status */
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
{
u_char reg;
set_bridge_state (s);
/* IO card, RESET flag */
reg = 0;
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
i365_set (s, I365_INTCTL, reg);
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
cb_set_power (s, state);
reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
if (reg != i365_get (s, I365_POWER))
i365_set (s, I365_POWER, reg);
return 0;
} /* i365_set_socket */
/*====================================================================*/
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
{
u_short base, i;
u_char map;
debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
mem->map, mem->flags, mem->speed,
mem->sys_start, mem->sys_stop, mem->card_start);
map = mem->map;
if ((map > 4) ||
(mem->card_start > 0x3ffffff) ||
(mem->sys_start > mem->sys_stop) ||
(mem->speed > 1000)) {
return -1;
}
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
/* Take care of high byte, for PCI controllers */
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
base = I365_MEM (map);
i = (mem->sys_start >> 12) & 0x0fff;
if (mem->flags & MAP_16BIT)
i |= I365_MEM_16BIT;
if (mem->flags & MAP_0WS)
i |= I365_MEM_0WS;
i365_set_pair (s, base + I365_W_START, i);
i = (mem->sys_stop >> 12) & 0x0fff;
switch (mem->speed / CYCLE_TIME) {
case 0:
break;
case 1:
i |= I365_MEM_WS0;
break;
case 2:
i |= I365_MEM_WS1;
break;
default:
i |= I365_MEM_WS1 | I365_MEM_WS0;
break;
}
i365_set_pair (s, base + I365_W_STOP, i);
i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
if (mem->flags & MAP_WRPROT)
i |= I365_MEM_WRPROT;
if (mem->flags & MAP_ATTRIB)
i |= I365_MEM_REG;
i365_set_pair (s, base + I365_W_OFF, i);
/* Turn on the window if necessary */
if (mem->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
return 0;
} /* i365_set_mem_map */
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
{
u_char map, ioctl;
map = io->map;
/* comment out: comparison is always false due to limited range of data type */
if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
(io->stop < io->start))
return -1;
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
if (io->speed)
ioctl |= I365_IOCTL_WAIT (map);
if (io->flags & MAP_0WS)
ioctl |= I365_IOCTL_0WS (map);
if (io->flags & MAP_16BIT)
ioctl |= I365_IOCTL_16BIT (map);
if (io->flags & MAP_AUTOSZ)
ioctl |= I365_IOCTL_IOCS16 (map);
i365_set (s, I365_IOCTL, ioctl);
/* Turn on the window if necessary */
if (io->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
return 0;
} /* i365_set_io_map */
/*====================================================================*/
int i82365_init (void)
{
u_int val;
int i;
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
/* Controller not found */
return 1;
}
debug ("i82365 Device Found!\n");
pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
socket.cb_phys &= ~0xf;
get_bridge_state (&socket);
set_bridge_opts (&socket);
i = i365_get_status (&socket, &val);
if (val & SS_DETECT) {
if (val & SS_3VCARD) {
state.Vcc = state.Vpp = 33;
puts (" 3.3V card found: ");
} else if (!(val & SS_XVCARD)) {
state.Vcc = state.Vpp = 50;
puts (" 5.0V card found: ");
} else {
puts ("i82365: unsupported voltage key\n");
state.Vcc = state.Vpp = 0;
}
} else {
/* No card inserted */
puts ("No card\n");
return 1;
}
state.flags = SS_IOCARD | SS_OUTPUT_ENA;
state.csc_mask = 0;
state.io_irq = 0;
i365_set_socket (&socket, &state);
for (i = 500; i; i--) {
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
break;
udelay (1000);
}
if (i == 0) {
/* PC Card not ready for data transfer */
puts ("i82365 PC Card not ready for data transfer\n");
return 1;
}
debug (" PC Card ready for data transfer: ");
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
io.map = 0;
io.flags = MAP_AUTOSZ | MAP_ACTIVE;
io.speed = 0;
io.start = 0x0100;
io.stop = 0x010F;
i365_set_io_map (&socket, &io);
#ifdef DEBUG
i82365_dump_regions (socket.dev);
#endif
return 0;
}
void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
io.speed = 0;
io.start = 0;
io.stop = 0x1;
i365_set_io_map (&socket, &io);
mem.map = 0;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
socket.state.sysctl &= 0xFFFF00FF;
state.Vcc = state.Vpp = 0;
i365_set_socket (&socket, &state);
}
int pcmcia_on (void)
{
u_int rc;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
rc = i82365_init();
if (rc)
goto exit;
rc = check_ide_device(0);
if (rc == 0)
goto exit;
i82365_exit();
exit:
return rc;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
i82365_exit();
return 0;
}
#endif
/*======================================================================
Debug stuff
======================================================================*/
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
printf ("PCI CONF: %08X ... %08X\n",
tmp[0], tmp[1]);
printf ("PCI MEM: ... %08X ... %08X\n",
mem[0x8 / 4], mem[0x800 / 4]);
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
printf ("CIS CONF: %02X %02X %02X ...\n",
cis[0x200], cis[0x202], cis[0x204]);
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ide[0], ide[1], ide[2], ide[3],
ide[4], ide[5], ide[6], ide[7]);
}
#endif /* DEBUG */
#endif /* CONFIG_I82365 */

2
board/c2mon/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

284
board/c2mon/pcmcia.c Normal file
View File

@ -0,0 +1,284 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "C2MON"
static void cfg_ports (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
ushort sreg;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure Port C for TPS2211 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
sreg = immap->im_ioport.iop_pcdat;
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */
sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */
immap->im_ioport.iop_pcdat = sreg;
immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS;
debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n",
immap->im_ioport.iop_pcpar,
immap->im_ioport.iop_pcdir,
immap->im_ioport.iop_pcdat);
/*
* Configure Port B for TPS2211 PC-Card Power-Interface Switch
*
* Over-Current Input only
*/
cp->cp_pbpar &= ~(TPS2211_INPUTS);
cp->cp_pbdir &= ~(TPS2211_INPUTS);
debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
ushort sreg;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
sreg = immap->im_ioport.iop_pcdat;
if ((pipr & mask) == mask) {
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
TPS2211_VCCD1); /* 5V on */
sreg &= ~(TPS2211_VCCD0); /* 3V off */
puts (" 5.0V card found: ");
} else {
sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */
TPS2211_VCCD0); /* 3V on */
sreg &= ~(TPS2211_VCCD1); /* 5V off */
puts (" 3.3V card found: ");
}
debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
sreg,
( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
(!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off"
);
immap->im_ioport.iop_pcdat = sreg;
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if ((cp->cp_pbdat & TPS2211_OC) == 0) {
printf (" *** Overcurrent - Safety shutdown ***\n");
immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* ALl voltages off / Hi-Z */
immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
TPS2211_VCCD0 | TPS2211_VCCD1 );
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
ushort sreg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
sreg = immap->im_ioport.iop_pcdat;
sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
switch(vcc) {
case 0: break; /* Switch off */
case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
sreg &= ~TPS2211_VCCD1;
break;
case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
sreg |= TPS2211_VCCD1;
break;
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
immap->im_ioport.iop_pcdat = sreg;
#ifdef DEBUG
{
char *s;
if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
s = "at 3.3V";
} else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) {
s = "at 5.0V";
} else {
s = "down";
}
printf ("PCMCIA powered %s\n", s);
}
#endif
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

802
board/cpc45/pd67290.c
View File

@ -1,4 +1,6 @@
/* pd67290.c - system configuration module for SPD67290
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -18,51 +20,799 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de>
********************************************************************
*
* Lots of code copied from:
*
* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>
/* imports */
#include <mpc824x.h>
#ifdef CONFIG_I82365
#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>
#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#include <pcmcia/cirrus.h>
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
{}
{0, 0}
};
/***************************************************************************
*
* SPD67290Init -
*
* RETURNS: -1 on error, 0 if OK
*/
#define CYCLE_TIME 120
int SPD67290Init (void)
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif
typedef struct socket_info_t {
pci_dev_t dev;
u_short bcr;
u_char pci_lat, cb_lat, sub_bus, cache;
u_int cb_phys;
socket_cap_t cap;
u_short type;
u_int flags;
cirrus_state_t c_state;
} socket_info_t;
/* These definitions must match the pcic table! */
typedef enum pcic_id {
IS_PD6710, IS_PD672X, IS_VT83C469
} pcic_id;
typedef struct pcic_t {
char *name;
} pcic_t;
static pcic_t pcic[] = {
{" Cirrus PD6710: "},
{" Cirrus PD672x: "},
{" VIA VT83C469: "},
};
static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;
/*====================================================================*/
/* Some PCI shortcuts */
static int pci_readb (socket_info_t * s, int r, u_char * v)
{
pci_dev_t devno;
int idx = 0; /* general index */
ulong membaseCsr; /* base address of device memory space */
return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
return pci_write_config_word (s->dev, r, v);
}
/* find PD67290 device */
if ((devno = pci_find_devices (supported, idx++)) < 0) {
printf ("No PD67290 device found !!\n");
/*====================================================================*/
#define cb_readb(s) readb((s)->cb_phys + 1)
#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
u_char val;
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
val = I365_REG (slot, reg);
cb_writeb (s, val);
val = cb_readb (s);
debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
return val;
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
u_char val;
val = I365_REG (slot, reg);
cb_writeb (s, val);
cb_writeb2 (s, data);
debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
}
static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) | mask);
}
static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) & ~mask);
}
#if 0 /* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
u_char d = i365_get (s, reg);
i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}
static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif /* not used */
static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
i365_set (s, reg, data & 0xff);
i365_set (s, reg + 1, data >> 8);
}
/*======================================================================
Code to save and restore global state information for Cirrus
PD67xx controllers, and to set and report global configuration
options.
======================================================================*/
#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
static void cirrus_get_state (socket_info_t * s)
{
int i;
cirrus_state_t *p = &s->c_state;
p->misc1 = i365_get (s, PD67_MISC_CTL_1);
p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
p->misc2 = i365_get (s, PD67_MISC_CTL_2);
for (i = 0; i < 6; i++)
p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
}
static void cirrus_set_state (socket_info_t * s)
{
int i;
u_char misc;
cirrus_state_t *p = &s->c_state;
misc = i365_get (s, PD67_MISC_CTL_2);
i365_set (s, PD67_MISC_CTL_2, p->misc2);
if (misc & PD67_MC2_SUSPEND)
udelay (50000);
misc = i365_get (s, PD67_MISC_CTL_1);
misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
for (i = 0; i < 6; i++)
i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
}
static u_int cirrus_set_opts (socket_info_t * s)
{
cirrus_state_t *p = &s->c_state;
u_int mask = 0xffff;
#if DEBUG
char buf[200];
memset (buf, 0, 200);
#endif
if (has_ring == -1)
has_ring = 1;
flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
#if DEBUG
if (p->misc2 & PD67_MC2_IRQ15_RI)
strcat (buf, " [ring]");
if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
strcat (buf, " [dyn mode]");
if (p->misc1 & PD67_MC1_INPACK_ENA)
strcat (buf, " [inpack]");
#endif
if (p->misc2 & PD67_MC2_IRQ15_RI)
mask &= ~0x8000;
if (has_led > 0) {
#if DEBUG
strcat (buf, " [led]");
#endif
mask &= ~0x1000;
}
if (has_dma > 0) {
#if DEBUG
strcat (buf, " [dma]");
#endif
mask &= ~0x0600;
flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
#if DEBUG
if (p->misc2 & PD67_MC2_FREQ_BYPASS)
strcat (buf, " [freq bypass]");
#endif
}
if (setup_time >= 0)
p->timer[0] = p->timer[3] = setup_time;
if (cmd_time > 0) {
p->timer[1] = cmd_time;
p->timer[4] = cmd_time * 2 + 4;
}
if (p->timer[1] == 0) {
p->timer[1] = 6;
p->timer[4] = 16;
if (p->timer[0] == 0)
p->timer[0] = p->timer[3] = 1;
}
if (recov_time >= 0)
p->timer[2] = p->timer[5] = recov_time;
debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
buf,
p->timer[0], p->timer[1], p->timer[2],
p->timer[3], p->timer[4], p->timer[5]);
return mask;
}
/*======================================================================
Routines to handle common CardBus options
======================================================================*/
/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
static void cb_get_state (socket_info_t * s)
{
pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}
static void cb_set_state (socket_info_t * s)
{
pci_writew (s, PCI_COMMAND, CMD_DFLT);
pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}
static void cb_set_opts (socket_info_t * s)
{
}
/*======================================================================
Power control for Cardbus controllers: used both for 16-bit and
Cardbus cards.
======================================================================*/
static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
u_int reg = 0;
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
if (state->Vpp != 0) {
if (state->Vpp == 120) {
reg |= I365_VPP1_12V;
puts (" 12V card found: ");
} else if (state->Vpp == state->Vcc) {
reg |= I365_VPP1_5V;
} else {
puts (" power not found: ");
return -1;
}
}
if (state->Vcc != 0) {
reg |= I365_VCC_5V;
if (state->Vcc == 33) {
puts (" 3.3V card found: ");
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else if (state->Vcc == 50) {
puts (" 5V card found: ");
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
puts (" power not found: ");
return -1;
}
}
if (reg != i365_get (s, I365_POWER)) {
reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
i365_set (s, I365_POWER, reg);
}
return 0;
}
/*======================================================================
Generic routines to get and set controller options
======================================================================*/
static void get_bridge_state (socket_info_t * s)
{
cirrus_get_state (s);
cb_get_state (s);
}
static void set_bridge_state (socket_info_t * s)
{
cb_set_state (s);
i365_set (s, I365_GBLCTL, 0x00);
i365_set (s, I365_GENCTL, 0x00);
cirrus_set_state (s);
}
static void set_bridge_opts (socket_info_t * s)
{
cirrus_set_opts (s);
cb_set_opts (s);
}
/*====================================================================*/
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
#define pd67_ext_get(s, r) \
(i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
static int i365_get_status (socket_info_t * s, u_int * value)
{
u_int status;
u_char val;
u_char power, vcc, vpp;
u_int powerstate;
status = i365_get (s, I365_IDENT);
status = i365_get (s, I365_STATUS);
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
} else {
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
}
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
*value |= (status & I365_CS_READY) ? SS_READY : 0;
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
/* Check for Cirrus CL-PD67xx chips */
i365_set (s, PD67_CHIP_INFO, 0);
val = i365_get (s, PD67_CHIP_INFO);
s->type = -1;
if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
val = i365_get (s, PD67_CHIP_INFO);
if ((val & PD67_INFO_CHIP_ID) == 0) {
s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
i365_set (s, PD67_EXT_INDEX, 0xe5);
if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
s->type = IS_VT83C469;
}
} else {
printf ("no Cirrus Chip found\n");
*value = 0;
return -1;
}
/* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */
membaseCsr = PCMCIA_IO_BASE - 0xfe000000;
power = i365_get (s, I365_POWER);
state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
vcc = power & I365_VCC_MASK;
vpp = power & I365_VPP1_MASK;
state.Vcc = state.Vpp = 0;
if((vcc== 0) || (vpp == 0)) {
/*
* On the Cirrus we get the info which card voltage
* we have in EXTERN DATA and write it to MISC_CTL1
*/
powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
if (powerstate & PD67_EXD_VS1(0)) {
/* 5V Card */
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
/* 3.3V Card */
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
}
i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
power = i365_get (s, I365_POWER);
}
if (power & I365_VCC_5V) {
state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
}
if (power == I365_VPP1_12V)
state.Vpp = 120;
/* IO card, RESET flags, IO interrupt */
power = i365_get (s, I365_INTCTL);
state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
if (power & I365_PC_IOCARD)
state.flags |= SS_IOCARD;
state.io_irq = power & I365_IRQ_MASK;
/* Card status change mask */
power = i365_get (s, I365_CSCINT);
state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
if (state.flags & SS_IOCARD)
state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
else {
state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
}
debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
"io_irq %d, csc_mask %#2.2x\n", state.flags,
state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
return 0;
} /* i365_get_status */
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
{
u_char reg;
set_bridge_state (s);
/* IO card, RESET flag */
reg = 0;
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
i365_set (s, I365_INTCTL, reg);
cb_set_power (s, state);
#if 0
/* Card status change interrupt mask */
reg = s->cs_irq << 4;
if (state->csc_mask & SS_DETECT)
reg |= I365_CSC_DETECT;
if (state->flags & SS_IOCARD) {
if (state->csc_mask & SS_STSCHG)
reg |= I365_CSC_STSCHG;
} else {
if (state->csc_mask & SS_BATDEAD)
reg |= I365_CSC_BVD1;
if (state->csc_mask & SS_BATWARN)
reg |= I365_CSC_BVD2;
if (state->csc_mask & SS_READY)
reg |= I365_CSC_READY;
}
i365_set (s, I365_CSCINT, reg);
i365_get (s, I365_CSC);
#endif /* 0 */
return 0;
} /* i365_set_socket */
/*====================================================================*/
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
{
u_short base, i;
u_char map;
debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
mem->map, mem->flags, mem->speed,
mem->sys_start, mem->sys_stop, mem->card_start);
map = mem->map;
if ((map > 4) ||
(mem->card_start > 0x3ffffff) ||
(mem->sys_start > mem->sys_stop) ||
(mem->speed > 1000)) {
return -1;
}
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
/* Take care of high byte, for PCI controllers */
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
base = I365_MEM (map);
i = (mem->sys_start >> 12) & 0x0fff;
if (mem->flags & MAP_16BIT)
i |= I365_MEM_16BIT;
if (mem->flags & MAP_0WS)
i |= I365_MEM_0WS;
i365_set_pair (s, base + I365_W_START, i);
i = (mem->sys_stop >> 12) & 0x0fff;
switch (mem->speed / CYCLE_TIME) {
case 0:
break;
case 1:
i |= I365_MEM_WS0;
break;
case 2:
i |= I365_MEM_WS1;
break;
default:
i |= I365_MEM_WS1 | I365_MEM_WS0;
break;
}
i365_set_pair (s, base + I365_W_STOP, i);
i = 0;
if (mem->flags & MAP_WRPROT)
i |= I365_MEM_WRPROT;
if (mem->flags & MAP_ATTRIB)
i |= I365_MEM_REG;
i365_set_pair (s, base + I365_W_OFF, i);
/* set System Memory map Upper Adress */
i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
/* Turn on the window if necessary */
if (mem->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
return 0;
} /* i365_set_mem_map */
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
{
u_char map, ioctl;
map = io->map;
/* comment out: comparison is always false due to limited range of data type */
if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
(io->stop < io->start))
return -1;
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
if (io->speed)
ioctl |= I365_IOCTL_WAIT (map);
if (io->flags & MAP_0WS)
ioctl |= I365_IOCTL_0WS (map);
if (io->flags & MAP_16BIT)
ioctl |= I365_IOCTL_16BIT (map);
if (io->flags & MAP_AUTOSZ)
ioctl |= I365_IOCTL_IOCS16 (map);
i365_set (s, I365_IOCTL, ioctl);
/* Turn on the window if necessary */
if (io->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
return 0;
} /* i365_set_io_map */
/*====================================================================*/
/*
* PCI_ADDR = (HOST_ADDR - 0xfe000000)
* see MPC 8245 Users Manual Adress Map B
*/
#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
int i82365_init (void)
{
u_int val;
int i;
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
/* Controller not found */
printf ("No PD67290 device found !!\n");
return 1;
}
debug ("i82365 Device Found!\n");
socket.cb_phys = PCMCIA_IO_BASE;
/* set base address */
pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr);
pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0,
HOST_TO_PCI(socket.cb_phys));
/* enable mapped memory and IO addresses */
pci_write_config_dword (devno,
pci_write_config_dword (socket.dev,
PCI_COMMAND,
PCI_COMMAND_MEMORY |
PCI_COMMAND_IO | PCI_COMMAND_WAIT);
get_bridge_state (&socket);
set_bridge_opts (&socket);
i = i365_get_status (&socket, &val);
if (i > -1) {
puts (pcic[socket.type].name);
} else {
printf ("i82365: Controller not found.\n");
return 1;
}
if((val & SS_DETECT) != SS_DETECT){
puts ("No card\n");
return 1;
}
state.flags |= SS_OUTPUT_ENA;
i365_set_socket (&socket, &state);
for (i = 500; i; i--) {
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
break;
udelay (1000);
}
if (i == 0) {
/* PC Card not ready for data transfer */
puts ("i82365 PC Card not ready for data transfer\n");
return 1;
}
debug (" PC Card ready for data transfer: ");
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
mem.map = 1;
mem.flags = MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#ifdef DEBUG
i82365_dump_regions (socket.dev);
#endif
return 0;
}
void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
io.speed = 0;
io.start = 0;
io.stop = 0x1;
i365_set_io_map (&socket, &io);
mem.map = 0;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
mem.map = 1;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
state.Vcc = state.Vpp = 0;
i365_set_socket (&socket, &state);
}
int pcmcia_on (void)
{
u_int rc;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
rc = i82365_init();
if (rc)
goto exit;
rc = check_ide_device(0);
if (rc == 0)
goto exit;
i82365_exit();
exit:
return rc;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
i82365_exit();
return 0;
}
#endif
/*======================================================================
Debug stuff
======================================================================*/
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
printf ("PCI CONF: %08X ... %08X\n",
tmp[0], tmp[1]);
printf ("PCI MEM: ... %08X ... %08X\n",
mem[0x8 / 4], mem[0x800 / 4]);
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
printf ("CIS CONF: %02X %02X %02X ...\n",
cis[0x200], cis[0x202], cis[0x204]);
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ide[0], ide[1], ide[2], ide[3],
ide[4], ide[5], ide[6], ide[7]);
}
#endif /* DEBUG */
#endif /* CONFIG_I82365 */

24
board/cpu87/cpu87.c
View File

@ -197,7 +197,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int checkboard (void)
{
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
return 0;
}
@ -280,7 +280,7 @@ long int initdram (int board_type)
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
ulong size8, size9;
ulong size8, size9, size10;
#endif
long psize;
@ -294,17 +294,25 @@ long int initdram (int board_type)
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
(uchar *) CFG_SDRAM_BASE);
psize = max(size8,max(size9,size10));
if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
}
} else if (psize == size9){
psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:9COL) ");
} else
printf ("(60x:10COL) ");
#endif /* CFG_RAMBOOT */

40
board/etin/kvme080/Makefile Normal file
View File

@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o multiverse.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

30
board/etin/kvme080/config.mk Normal file
View File

@ -0,0 +1,30 @@
#
# (C) Copyright 2005
# Sangmoon, Etin Systems, dogoil@etinsys.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# KVME080 board
#
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

193
board/etin/kvme080/kvme080.c Normal file
View File

@ -0,0 +1,193 @@
/*
* (C) Copyright 2005
* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
#include <asm/processor.h>
int checkboard(void)
{
puts ("Board: KVME080\n");
return 0;
}
unsigned long setdram(int m, int row, int col, int bank)
{
int i;
unsigned long start, end;
uint32_t mccr1;
uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
uint8_t mber = 0;
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
start = CFG_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
if (i < 4) {
msar1 |= ((start >> 20) & 0xff) << i * 8;
emsar1 |= ((start >> 28) & 0xff) << i * 8;
mear1 |= ((end >> 20) & 0xff) << i * 8;
emear1 |= ((end >> 28) & 0xff) << i * 8;
} else {
msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
}
mber |= 1 << i;
start += (1 << (col + row + 3) ) * bank;
end += (1 << (col + row + 3) ) * bank;
}
for (; i < 8; i++) {
if (i < 4) {
msar1 |= 0xff << i * 8;
emsar1 |= 0x30 << i * 8;
mear1 |= 0xff << i * 8;
emear1 |= 0x30 << i * 8;
} else {
msar2 |= 0xff << (i-4) * 8;
emsar2 |= 0x30 << (i-4) * 8;
mear2 |= 0xff << (i-4) * 8;
emear2 |= 0x30 << (i-4) * 8;
}
}
CONFIG_WRITE_WORD(MCCR1, mccr1);
CONFIG_WRITE_WORD(MSAR1, msar1);
CONFIG_WRITE_WORD(EMSAR1, emsar1);
CONFIG_WRITE_WORD(MEAR1, mear1);
CONFIG_WRITE_WORD(EMEAR1, emear1);
CONFIG_WRITE_WORD(MSAR2, msar2);
CONFIG_WRITE_WORD(EMSAR2, emsar2);
CONFIG_WRITE_WORD(MEAR2, mear2);
CONFIG_WRITE_WORD(EMEAR2, emear2);
CONFIG_WRITE_BYTE(MBER, mber);
return (1 << (col + row + 3) ) * bank * m;
}
long int initdram(int board_type)
{
unsigned int msr;
long int size = 0;
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
mtmsr(msr);
if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
size = 0x20000000; /* 512MB */
else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
size = 0x04000000; /* 64MB */
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT2L, CFG_IBAT2L);
mtspr(IBAT2U, CFG_IBAT2U);
mtspr(DBAT2L, CFG_DBAT2L);
mtspr(DBAT2U, CFG_DBAT2U);
mtmsr(msr);
return size;
}
struct pci_controller hose;
void pci_init_board(void)
{
pci_mpc824x_init(&hose);
}
int board_early_init_f(void)
{
*(volatile unsigned char *)(0xff080120) = 0xfb;
return 0;
}
int board_early_init_r(void)
{
unsigned int msr;
CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
mtmsr(msr);
return 0;
}
extern int multiverse_init(void);
int misc_init_r(void)
{
multiverse_init();
return 0;
}
void *nvram_read(void *dest, const long src, size_t count)
{
volatile uchar *d = (volatile uchar*) dest;
volatile uchar *s = (volatile uchar*) src;
while(count--) {
*d++ = *s++;
asm volatile("sync");
}
return dest;
}
void nvram_write(long dest, const void *src, size_t count)
{
volatile uchar *d = (volatile uchar*)dest;
volatile uchar *s = (volatile uchar*)src;
while(count--) {
*d++ = *s++;
asm volatile("sync");
}
}

186
board/etin/kvme080/multiverse.c Normal file
View File

@ -0,0 +1,186 @@
/*
* multiverse.c
*
* VME driver for Multiverse
*
* Author : Sangmoon Kim
* dogoil@etinsys.com
*
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include "multiverse.h"
static unsigned long vme_asi_addr;
static unsigned long vme_iack_addr;
static unsigned long pci_reg_addr;
static unsigned long vme_reg_addr;
int multiv_reset(unsigned long base)
{
writeb(0x09, base + VME_SLAVE32_AM);
writeb(0x39, base + VME_SLAVE24_AM);
writeb(0x29, base + VME_SLAVE16_AM);
writeb(0x2f, base + VME_SLAVE_REG_AM);
writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
#ifdef A32_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
base + VME_SLAVE32_MASK);
writeb(0x01, base + VME_SLAVE32_EN);
} else {
writeb(0xff, base + VME_SLAVE32_MASK);
writeb(0x00, base + VME_SLAVE32_EN);
}
#else
writeb(0xff, base + VME_SLAVE32_MASK);
writeb(0x00, base + VME_SLAVE32_EN);
#endif
#ifdef A24_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
base + VME_SLAVE24_MASK);
writeb(0x01, base + VME_SLAVE24_EN);
} else {
writeb(0xff, base + VME_SLAVE24_MASK);
writeb(0x00, base + VME_SLAVE24_EN);
}
#else
writeb(0xff, base + VME_SLAVE24_MASK);
writeb(0x00, base + VME_SLAVE24_EN);
#endif
#ifdef A16_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
base + VME_SLAVE16_MASK);
writeb(0x01, base + VME_SLAVE16_EN);
} else {
writeb(0xff, base + VME_SLAVE16_MASK);
writeb(0x00, base + VME_SLAVE16_EN);
}
#else
writeb(0xff, base + VME_SLAVE16_MASK);
writeb(0x00, base + VME_SLAVE16_EN);
#endif
#ifdef REG_SLV_WINDOW
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
base + VME_SLAVE_REG_MASK);
writeb(0x01, base + VME_SLAVE_REG_EN);
} else {
writeb(0xf8, base + VME_SLAVE_REG_MASK);
}
#else
writeb(0xf8, base + VME_SLAVE_REG_MASK);
#endif
writeb(0x09, base + VME_MASTER32_AM);
writeb(0x39, base + VME_MASTER24_AM);
writeb(0x29, base + VME_MASTER16_AM);
writeb(0x2f, base + VME_MASTER_REG_AM);
writel(0x00000000, base + VME_RMW_ADRS);
writeb(0x00, base + VME_IRQ);
writeb(0x00, base + VME_INT_EN);
writel(0x00000000, base + VME_IRQ1_REG);
writel(0x00000000, base + VME_IRQ2_REG);
writel(0x00000000, base + VME_IRQ3_REG);
writel(0x00000000, base + VME_IRQ4_REG);
writel(0x00000000, base + VME_IRQ5_REG);
writel(0x00000000, base + VME_IRQ6_REG);
writel(0x00000000, base + VME_IRQ7_REG);
return 0;
}
void multiv_auto_slot_id(unsigned long base)
{
unsigned int vector;
int slot_id = 1;
if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
base + VME_CTRL);
while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
while (readb(base + VME_INT) & 0x04) {
vector = *(volatile unsigned int*)
(vme_iack_addr + VME_IACK2);
*(unsigned char*)(vme_asi_addr + 0x7ffff)
= (slot_id << 3) & 0xff;
slot_id ++;
if (slot_id > 31)
break;
}
}
}
}
int multiverse_init(void)
{
int i;
pci_dev_t pdev;
unsigned int bar[6];
pdev = pci_find_device(0x1895, 0x0001, 0);
if (pdev == 0)
return -1;
for (i = 0; i < 6; i++)
pci_read_config_dword (pdev,
PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
pci_reg_addr = bar[0];
vme_reg_addr = bar[1] + 0x00F00000;
vme_iack_addr = bar[1] + 0x00200000;
vme_asi_addr = bar[3];
pci_write_config_dword (pdev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
writel(0xFF000000, pci_reg_addr + P_TA1);
writel(0x04, pci_reg_addr + P_IMG_CTRL1);
writel(0xf0000000, pci_reg_addr + P_TA2);
writel(0x04, pci_reg_addr + P_IMG_CTRL2);
writel(0xF1000000, pci_reg_addr + P_TA3);
writel(0x04, pci_reg_addr + P_IMG_CTRL3);
writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
writel(0x04, pci_reg_addr + P_IMG_CTRL5);
writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
writel(0x04, pci_reg_addr + W_IMG_CTRL1);
writel(0xF0000000, pci_reg_addr + W_BA2);
writel(0xFF000000, pci_reg_addr + W_AM2);
writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
writel(0x04, pci_reg_addr + W_IMG_CTRL2);
writel(0xFF000000, pci_reg_addr + W_BA3);
writel(0xFF000000, pci_reg_addr + W_AM3);
writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
writel(0x04, pci_reg_addr + W_IMG_CTRL3);
writel(0x00000001, pci_reg_addr + W_ERR_CS);
writel(0x00000001, pci_reg_addr + P_ERR_CS);
multiv_reset(vme_reg_addr);
writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
vme_reg_addr + VME_CTRL);
multiv_auto_slot_id(vme_reg_addr);
return 0;
}

176
board/etin/kvme080/multiverse.h Normal file
View File

@ -0,0 +1,176 @@
/*
* multiverse.h
*
* VME driver for Multiverse
*
* Author : Sangmoon Kim
* dogoil@etinsys.com
*
* Copyright 2005 ETIN SYSTEMS Co.,Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MULTIVERSE_H__
#define __MULTIVERSE_H__
#define VME_A32_MSTR_BUS 0x90000000
#define VME_A32_MSTR_SIZE 0x01000000
#define VME_A32_SLV_SIZE 0x01000000
#define VME_A32_SLV_BUS 0x90000000
#define VME_A24_SLV_BUS 0x00000000
#define VME_A16_SLV_BUS 0x00000000
#define VME_A32_SLV_LOCAL 0x00000000
#define VME_A24_SLV_LOCAL 0x00000000
#define VME_A16_SLV_LOCAL 0x00000000
#define A32_SLV_WINDOW
#undef A24_SLV_WINDOW
#undef A16_SLV_WINDOW
#undef REG_SLV_WINDOW
/* PCI Registers */
#define P_IMG_CTRL0 0x100
#define P_BA0 0x104
#define P_AM0 0x108
#define P_TA0 0x10C
#define P_IMG_CTRL1 0x110
#define P_BA1 0x114
#define P_AM1 0x118
#define P_TA1 0x11C
#define P_IMG_CTRL2 0x120
#define P_BA2 0x124
#define P_AM2 0x128
#define P_TA2 0x12C
#define P_IMG_CTRL3 0x130
#define P_BA3 0x134
#define P_AM3 0x138
#define P_TA3 0x13C
#define P_IMG_CTRL4 0x140
#define P_BA4 0x144
#define P_AM4 0x148
#define P_TA4 0x14C
#define P_IMG_CTRL5 0x150
#define P_BA5 0x154
#define P_AM5 0x158
#define P_TA5 0x15C
#define P_ERR_CS 0x160
#define P_ERR_ADDR 0x164
#define P_ERR_DATA 0x168
#define WB_CONF_SPC_BAR 0x180
#define W_IMG_CTRL1 0x184
#define W_BA1 0x188
#define W_AM1 0x18C
#define W_TA1 0x190
#define W_IMG_CTRL2 0x194
#define W_BA2 0x198
#define W_AM2 0x19C
#define W_TA2 0x1A0
#define W_IMG_CTRL3 0x1A4
#define W_BA3 0x1A8
#define W_AM3 0x1AC
#define W_TA3 0x1B0
#define W_IMG_CTRL4 0x1B4
#define W_BA4 0x1B8
#define W_AM4 0x1BC
#define W_TA4 0x1C0
#define W_IMG_CTRL5 0x1C4
#define W_BA5 0x1C8
#define W_AM5 0x1CC
#define W_TA5 0x1D0
#define W_ERR_CS 0x1D4
#define W_ERR_ADDR 0x1D8
#define W_ERR_DATA 0x1DC
#define CNF_ADDR 0x1E0
#define CNF_DATA 0x1E4
#define INT_ACK 0x1E8
#define ICR 0x1EC
#define ISR 0x1F0
/* VME registers */
#define VME_SLAVE32_AM 0x03
#define VME_SLAVE24_AM 0x02
#define VME_SLAVE16_AM 0x01
#define VME_SLAVE_REG_AM 0x00
#define VME_SLAVE32_A 0x07
#define VME_SLAVE24_A 0x06
#define VME_SLAVE16_A 0x05
#define VME_SLAVE_REG_A 0x04
#define VME_SLAVE32_MASK 0x0B
#define VME_SLAVE24_MASK 0x0A
#define VME_SLAVE16_MASK 0x09
#define VME_SLAVE_REG_MASK 0x08
#define VME_SLAVE32_EN 0x0F
#define VME_SLAVE24_EN 0x0E
#define VME_SLAVE16_EN 0x0D
#define VME_SLAVE_REG_EN 0x0C
#define VME_MASTER32_AM 0x13
#define VME_MASTER24_AM 0x12
#define VME_MASTER16_AM 0x11
#define VME_MASTER_REG_AM 0x10
#define VME_RMW_ADRS 0x14
#define VME_MBOX 0x18
#define VME_STATUS 0x1E
#define VME_CTRL 0x1C
#define VME_IRQ 0x20
#define VME_INT_EN 0x21
#define VME_INT 0x22
#define VME_IRQ1_REG 0x24
#define VME_IRQ2_REG 0x28
#define VME_IRQ3_REG 0x2C
#define VME_IRQ4_REG 0x30
#define VME_IRQ5_REG 0x34
#define VME_IRQ6_REG 0x38
#define VME_IRQ7_REG 0x3C
/* VME control register */
#define VME_CTRL_BRDRST 0x01
#define VME_CTRL_SYSRST 0x02
#define VME_CTRL_RMW 0x04
#define VME_CTRL_SHORT_D 0x08
#define VME_CTRL_SYSFAIL 0x10
#define VME_CTRL_VOWN 0x20
#define VME_CTRL_A16_REG_MODE 0x40
/* VME status register */
#define VME_STATUS_SYSCON 0x01
#define VME_STATUS_SYSFAIL 0x02
#define VME_STATUS_ACFAIL 0x04
#define VME_STATUS_SYSRST 0x08
#define VME_STATUS_VOWN 0x10
/* Interrupt types */
#define LVL1 0x0002
#define LVL2 0x0004
#define LVL3 0x0008
#define LVL4 0x0010
#define LVL5 0x0020
#define LVL6 0x0040
#define LVL7 0x0080
#define MULTIVERSE_INTI_INT 0x0100
#define MULTIVERSE_WB_INT 0x0200
#define MULTIVERSE_PCI_INT 0x0400
/* interrupt acknowledge */
#define VME_IACK1 0x04
#define VME_IACK2 0x08
#define VME_IACK3 0x0c
#define VME_IACK4 0x10
#define VME_IACK5 0x14
#define VME_IACK6 0x18
#define VME_IACK7 0x1c
#endif /* __MULTIVERSE_H__ */

128
board/etin/kvme080/u-boot.lds Normal file
View File

@ -0,0 +1,128 @@
/*
* (C) Copyright 2001-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc824x/start.o (.text)
lib_ppc/board.o (.text)
lib_ppc/ppcstring.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/fads/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o lamp.o
OBJS = $(BOARD).o flash.o lamp.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/fads/fads.h
View File

@ -467,7 +467,9 @@
#define CONFIG_ISO_PARTITION 1
#undef CONFIG_ATAPI
#if 0 /* does not make sense when CFG_CMD_IDE is not enabled, too */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#endif
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */

84
board/fads/pcmcia.c Normal file
View File

@ -0,0 +1,84 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#ifdef CONFIG_ADS
#define PCMCIA_BOARD_MSG "ADS"
#else
#define PCMCIA_BOARD_MSG "FADS"
#endif
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
u_long reg = 0;
switch(vpp) {
case 0: reg = 0; break;
case 50: reg = 1; break;
case 120: reg = 2; break;
default: return 1;
}
switch(vcc) {
case 0: reg = 0; break;
#ifdef CONFIG_ADS
case 50: reg = BCSR1_PCCVCCON; break;
#endif
#ifdef CONFIG_FADS
case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
case 50: reg = BCSR1_PCCVCC1; break;
#endif
default: return 1;
}
/* first, turn off all power */
#ifdef CONFIG_ADS
*((uint *)BCSR1) |= BCSR1_PCCVCCON;
#endif
#ifdef CONFIG_FADS
*((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
#endif
*((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
/* enable new powersettings */
#ifdef CONFIG_ADS
*((uint *)BCSR1) &= ~reg;
#endif
#ifdef CONFIG_FADS
*((uint *)BCSR1) |= reg;
#endif
*((uint *)BCSR1) |= reg << 20;
return 0;
}
int pcmcia_hardware_enable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#endif /* CFG_CMD_PCMCIA */
#endif /* CONFIG_PCMCIA */

2
board/gth/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ee_access.o
OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

93
board/gth/pcmcia.c Normal file
View File

@ -0,0 +1,93 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{ /* Do nothing */
return 0;
}
int pcmcia_hardware_enable (int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
immap = (immap_t *) CFG_IMMR;
sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/*
* Make sure there is a card in the slot,
* then configure the interface.
*/
udelay (10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__, __FUNCTION__,
&(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & 0x98000000) {
printf (" No Card found\n");
return (1);
}
mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
return 0; /* No hardware to disable */
}
#endif
#endif /* CONFIG_PCMCIA */

1
board/gth2/config.mk
View File

@ -39,4 +39,3 @@ TEXT_BASE = 0x90000000
endif
endif
endif

82
board/gth2/ee_access.c
View File

@ -8,7 +8,7 @@
For documentaion, see data sheet for DS2438, 2438.pdf
By Thomas.Lange@corelatus.com 001025
Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
@ -105,7 +105,7 @@ static u8 make_new_crc( u8 Old_crc, u8 New_value ){
/* Compute a new checksum with new byte, using previous checksum as input
See DS app note 17, understanding and using cyclic redundancy checks...
Also see DS2438, page 11 */
return( crc_lookup[Old_crc ^ New_value ]);
return( crc_lookup[Old_crc ^ New_value ]);
}
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
@ -119,16 +119,16 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
Curr_byte++;
}
E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
if(Curr_crc == Crc){
/* Good */
/* Good */
return(TRUE);
}
printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
return(FALSE);
}
static void
static void
set_idle(void){
/* Send idle and keep start time
Continous 1 is idle */
@ -136,7 +136,7 @@ set_idle(void){
}
static int
static int
do_cpu_reset(void){
/* Release reset and verify that chip responds with presence pulse */
int Retries=0;
@ -146,10 +146,10 @@ do_cpu_reset(void){
/* Send reset */
WRITE_PORT(0);
udelay(RESET_LOW_TIME);
/* Release reset */
WRITE_PORT(1);
/* Wait for EEPROM to drive output */
udelay(PRESENCE_TIMEOUT);
if(!READ_PORT){
@ -166,17 +166,17 @@ do_cpu_reset(void){
}
printk(KERN_ERR"eeprom did not respond when releasing reset\n");
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
/* Set to idle again */
set_idle();
return(-EIO);
}
static u8
static u8
read_cpu_byte(void){
/* Read a single byte from EEPROM
Read LSb first */
@ -186,36 +186,36 @@ read_cpu_byte(void){
u32 Flags;
E_DEBUG("Reading byte\n");
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
#ifdef __KERNEL__
/* Disable irq */
#ifdef __KERNEL__
/* Disable irq */
save_flags(Flags);
cli();
#endif
#endif
/* Pull down pin short time to start read
See page 26 in data sheet */
WRITE_PORT(0);
udelay(READ_LOW);
WRITE_PORT(1);
/* Wait for chip to drive pin */
udelay(READ_TIMEOUT);
Value = READ_PORT;
if(Value)
Value=1;
#ifdef __KERNEL__
/* Enable irq */
/* Enable irq */
restore_flags(Flags);
#endif
/* Wait for chip to release pin */
udelay(TOTAL_READ_LOW-READ_TIMEOUT);
@ -230,30 +230,30 @@ read_cpu_byte(void){
return(Result);
}
static void
static void
write_cpu_byte(u8 Byte){
/* Write a single byte to EEPROM
Write LSb first */
int i;
int Value;
u32 Flags;
E_DEBUG("Writing byte 0x%x\n",Byte);
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
Value = Byte&1;
#ifdef __KERNEL__
/* Disable irq */
/* Disable irq */
save_flags(Flags);
cli();
#endif
#endif
/* Pull down pin short time for a 1, long time for a 0
See page 26 in data sheet */
WRITE_PORT(0);
if(Value){
/* Write a 1 */
@ -267,54 +267,54 @@ write_cpu_byte(u8 Byte){
WRITE_PORT(1);
#ifdef __KERNEL__
/* Enable irq */
/* Enable irq */
restore_flags(Flags);
#endif
if(Value)
/* Wait for chip to read the 1 */
udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
/* E_DEBUG("Wrote %d\n",Value); */
Byte>>=1;
}
}
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
/* Execute this command string, including
/* Execute this command string, including
giving reset and setting to idle after command
if Rx_len is set, we read out data from EEPROM */
if Rx_len is set, we read out data from EEPROM */
int i;
E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
if(do_cpu_reset()){
/* Failed! */
return(-EIO);
}
if(Send_skip)
/* Always send SKIP_ROM first to tell chip we are sending a command,
/* Always send SKIP_ROM first to tell chip we are sending a command,
except when we read out rom data for chip */
write_cpu_byte(SKIP_ROM);
/* Always have Tx data */
for(i=0;i<Tx_len;i++){
write_cpu_byte(Tx[i]);
}
if(Rx_len){
for(i=0;i<Rx_len;i++){
Rx[i]=read_cpu_byte();
}
}
set_idle();
E_DEBUG("Command done\n");
return(0);
}
}
int ee_init_cpu_data(void){
int i;
@ -323,7 +323,7 @@ int ee_init_cpu_data(void){
/* Leave it floting since altera is driving the same pin */
set_idle();
/* Copy all User EEPROM data to scratchpad */
/* Copy all User EEPROM data to scratchpad */
for(i=0;i<USER_PAGES;i++){
Tx[0]=RECALL_MEMORY;
Tx[1]=EE_USER_PAGE_0+i;
@ -332,16 +332,16 @@ int ee_init_cpu_data(void){
/* Make sure chip doesnt store measurements in NVRAM */
Tx[0]=WRITE_SCRATCHPAD;
Tx[1]=0; /* Page */
Tx[1]=0; /* Page */
Tx[2]=9;
if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
Tx[0]=COPY_SCRATCHPAD;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
for(i=0;i<10;i++){
udelay(1000);
}
return(0);
}

2
board/gth2/ee_access.h
View File

@ -21,7 +21,7 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
#define EE_BUSY 0x40000000
#define EE_ERROR 0x20000000
/* Commands */
/* Commands */
#define EE_CMD_NOP 0
#define EE_CMD_INIT_RES 1
#define EE_CMD_WR_BYTE 2

2
board/gth2/ee_dev.h
View File

@ -21,7 +21,7 @@
#ifndef INCeedevh
#define INCeedevh
#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
/* MIPS */
#define WRITE_PORT(Value) write_gpio_data(Value)

18
board/gth2/gth2.c
View File

@ -61,13 +61,13 @@ void init_log_serial(void){
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
/* Copy buffer from last run */
memcpy(serial_log_buffer + 4096,
serial_log_buffer,
memcpy(serial_log_buffer + 4096,
serial_log_buffer,
4096);
memset(serial_log_buffer, 0, 4096);
*serial_log_offsetp = 4;
*serial_log_offsetp = 4;
}
@ -118,7 +118,7 @@ void set_ledcard(u32 value){
udelay(1);
*sys_outputclr = GPIO_LEDCLK;
udelay(1);
value<<=1;
}
/* Data is enable output */
@ -228,7 +228,7 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
printf ("Invalid boot count %u, setting 1\n", Count);
Count = 1;
}
printf ("Boot attempt %d\n", Count);
data = (System << 8) | Count;
@ -241,9 +241,9 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
}
static int random_system(void){
/* EEPROM read failed. Just try to choose one
/* EEPROM read failed. Just try to choose one
system release and hope it works */
/* FIXME */
return(SYSTEM_BOOT);
}
@ -320,8 +320,8 @@ static void check_boot_tries (void)
data = *addr;
system = data >> 8;
count = data & 0xFF;
if ((system != SYSTEM_BOOT) &
(system != SYSTEM2_BOOT) &
if ((system != SYSTEM_BOOT) &
(system != SYSTEM2_BOOT) &
(system != FAILSAFE_BOOT)) {
printf ("*** Wrong system %d\n", system);
system = FAILSAFE_BOOT;

18
board/gth2/lowlevel_init.S
View File

@ -197,11 +197,11 @@ noCacheJump:
/* RCE2 CP Altera */
li t0, MEM_STCFG2
li t1, 0x00000280 /* BE, EW */
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME2
li t1, 0x0303000c
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR2
@ -210,11 +210,11 @@ noCacheJump:
/* RCE3 DP Altera */
li t0, MEM_STCFG3
li t1, 0x00000280 /* BE, EW */
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x0303000c
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR3
@ -428,14 +428,14 @@ mt0: sw t0, 0(t0)
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt1: lw t2, 0(t0)
bne t0, t2, memhang
bne t0, t2, memhang
add t1, -1
add t0, 4
bne t1, zero, mt1
nop
nop
.globl clearmem
clearmem:
clearmem:
/* Clear memory */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
@ -445,10 +445,10 @@ mtc: sw zero, 0(t0)
bne t1, zero, mtc
nop
nop
memtestend:
memtestend:
j ra
nop
memhang:
memhang:
b memhang
nop

2
board/icu862/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

268
board/icu862/pcmcia.c Normal file
View File

@ -0,0 +1,268 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "ICU862"
static void cfg_port_B (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
uint reg;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure Port B for TPS2205 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
reg = cp->cp_pbdat;
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
TPS2205_SHDN); /* enable switch */
cp->cp_pbdat = reg;
cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
cp->cp_pbdir = reg | TPS2205_OUTPUTS;
debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
cfg_port_B ();
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
reg = cp->cp_pbdat;
if ((pipr & mask) == mask) {
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC3); /* 3V off */
reg &= ~(TPS2205_VCC5); /* 5V on */
puts (" 5.0V card found: ");
} else {
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC5); /* 5V off */
reg &= ~(TPS2205_VCC3); /* 3V on */
puts (" 3.3V card found: ");
}
debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
reg,
(reg & TPS2205_VCC3) ? "off" : "on",
(reg & TPS2205_VCC5) ? "off" : "on",
(reg & TPS2205_VPP_PGM) ? "off" : "on",
(reg & TPS2205_VPP_VCC) ? "off" : "on" );
cp->cp_pbdat = reg;
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if ((cp->cp_pbdat & TPS2205_OC) == 0) {
printf (" *** Overcurrent - Safety shutdown ***\n");
cp->cp_pbdat &= ~(TPS2205_SHDN);
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Shut down */
cp->cp_pbdat &= ~(TPS2205_SHDN);
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_port_B (); /* Enables switch, but all in Hi-Z */
reg = cp->cp_pbdat;
switch(vcc) {
case 0: break; /* Switch off */
case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */
case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
cp->cp_pbdat = reg;
#ifdef DEBUG
{
char *s;
if ((reg & TPS2205_VCC3) == 0) {
s = "at 3.3V";
} else if ((reg & TPS2205_VCC5) == 0) {
s = "at 5.0V";
} else {
s = "down";
}
printf ("PCMCIA powered %s\n", s);
}
#endif
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

225
board/kup/common/pcmcia.c Normal file
View File

@ -0,0 +1,225 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "KUP"
#define KUP4K_PCMCIA_B_3V3 (0x00020000)
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(slot);
pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(2500);
/*
* Configure Port B pins for
* 3 Volts enable
*/
if (slot) { /* Slot A is built-in */
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
/* remove all power */
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
}
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
puts (" 5.0V card found: NOT SUPPORTED !!!\n");
} else {
if(slot)
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
puts (" 3.3V card found: ");
}
#if 0
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
cp->cp_pbdir &= ~(0x0020 | 0x0010);
cp->cp_pbpar &= ~(0x0020 | 0x0010);
udelay(500000);
#endif
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* remove all power */
if (slot)
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: " \
PCMCIA_BOARD_MSG \
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
if (!slot) /* Slot A is not configurable */
return 0;
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("PCMCIA power OFF\n");
/*
* Configure Port B pins for
* 3 Volts enable
*/
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
/* remove all power */
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
switch(vcc) {
case 0: break;
case 33:
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
debug ("PCMCIA powered at 3.3V\n");
break;
case 50:
debug ("PCMCIA: 5Volt vcc not supported\n");
break;
default:
puts("PCMCIA: vcc not supported");
break;
}
udelay(10000);
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
? "only 5 V --> NOT SUPPORTED"
: "can do 3.3V");
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

2
board/kup/kup4k/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/kup/kup4x/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

2
board/lwmon/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

240
board/lwmon/pcmcia.c Normal file
View File

@ -0,0 +1,240 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include <i2c.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "LWMON"
/* #define's for MAX1604 Power Switch */
#define MAX1604_OP_SUS 0x80
#define MAX1604_VCCBON 0x40
#define MAX1604_VCC_35 0x20
#define MAX1604_VCCBHIZ 0x10
#define MAX1604_VPPBON 0x08
#define MAX1604_VPPBPBPGM 0x04
#define MAX1604_VPPBHIZ 0x02
/* reserved 0x01 */
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
uchar val;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
/* Switch on PCMCIA port in PIC register 0x60 */
reg = pic_read (0x60);
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
reg &= ~0x10;
/* reg |= 0x08; Vpp not needed */
pic_write (0x60, reg);
#ifdef DEBUG
reg = pic_read (0x60);
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
#endif
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */
puts (" 5.0V card found: ");
} else {
val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */
puts (" 3.3V card found: ");
}
/* switch VCC on */
val |= MAX1604_OP_SUS | MAX1604_VCCBON;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
udelay(500000);
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
uchar val;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* remove all power, put output in high impedance state */
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* Switch off PCMCIA port in PIC register 0x60 */
reg = pic_read (0x60);
debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
reg |= 0x10;
reg &= ~0x08;
pic_write (0x60, reg);
#ifdef DEBUG
reg = pic_read (0x60);
printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg);
#endif
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
uchar val;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Turn off all power (switch to high impedance)
*/
debug ("PCMCIA power OFF\n");
val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
val = 0;
switch(vcc) {
case 0: break;
case 33: val = MAX1604_VCC_35; break;
case 50: break;
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
if (val) {
debug ("PCMCIA powered at %sV\n",
(val & MAX1604_VCC_35) ? "3.3" : "5.0");
} else {
debug ("PCMCIA powered down\n");
}
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

2
board/mbx8xx/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o vpd.o
OBJS = $(BOARD).o flash.o vpd.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

166
board/mbx8xx/pcmcia.c Normal file
View File

@ -0,0 +1,166 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include "csr.h"
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
/* A lot of this has been taken from the RPX code in this file it works from me.
I have added the voltage selection for the MBX board. */
/* MBX voltage bit in control register #2 */
#define CR2_VPP12 ((uchar)0x10)
#define CR2_VPPVDD ((uchar)0x20)
#define CR2_VDD5 ((uchar)0x40)
#define CR2_VDD3 ((uchar)0x80)
#define PCMCIA_BOARD_MSG "MBX860"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{
uchar reg = 0;
debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10);
switch (vcc) {
case 0:
break;
case 33:
reg |= CR2_VDD3;
break;
case 50:
reg |= CR2_VDD5;
break;
default:
return 1;
}
switch (vpp) {
case 0:
break;
case 33:
case 50:
if (vcc == vpp) {
reg |= CR2_VPPVDD;
} else {
return 1;
}
break;
case 120:
reg |= CR2_VPP12;
break;
default:
return 1;
}
/* first, turn off all power */
MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL);
/* enable new powersettings */
MBX_CSR2 |= reg;
debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2);
return (0);
}
int pcmcia_hardware_enable (int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
'A' + slot);
udelay (10000);
immap = (immap_t *) CFG_IMMR;
sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/* remove all power */
pcmcia_voltage_set (slot, 0, 0);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
#ifndef CONFIG_HMI10
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
#else
if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
#endif /* CONFIG_HMI10 */
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
if ((reg & mask) == mask) {
pcmcia_voltage_set (_slot_, 50, 0);
printf (" 5.0V card found: ");
} else {
pcmcia_voltage_set (_slot_, 33, 0);
printf (" 3.3V card found: ");
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable (int slot)
{
return 0; /* No hardware to disable */
}
#endif /* CFG_CMD_PCMCIA */
#endif /* CONFIG_PCMCIA */

10
board/mcc200/config.mk
View File

@ -26,16 +26,18 @@
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFE000000 boot low
# 0xFC000000 boot low (standard configuration)
# 0xFFF00000 boot high
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## Standard: boot low
TEXT_BASE = 0xFC000000
## Boot high
# TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif

9
board/mcc200/mcc200.c
View File

@ -32,7 +32,12 @@
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
#include "mt48lc16m32s2-75.h"
/* #include "mt48lc16m32s2-75.h" */
#if defined (CONFIG_MCC200_SDRAM)
#include "mt48lc16m16a2-75.h"
#else
#include "mt46v16m16-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -249,7 +254,7 @@ int misc_init_r (void)
*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[0].start[0] + flash_info[0].size / 2,
(flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
(flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
}

80
board/netstar/crcek.S
View File

@ -13,6 +13,7 @@
* u32 - crc32
*/
#include <config.h>
#include "crcek.h"
/**
@ -39,7 +40,7 @@
.macro crcuj, offset, size
mov r0, #0
ldr r1, \offset
ldr r2, [r1]
ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem
beq 2f
tst r2, #3 @ unaligned size
@ -47,7 +48,6 @@
ldr r3, \size
cmp r2, r3 @ bogus size
bhi 2f
add r1, r1, #4
do_crc32
ldr r1, [r1]
2:
@ -55,16 +55,71 @@
.endm
.macro wait, reg
mov \reg, #0x1000
mov \reg, #0x100000
3:
subs \reg, \reg, #0x1
bne 3b
.endm
.text
.globl crcek
crcek:
b crc2_bad
/* Enable I-cache */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
mov r1, #0x00
mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
nop
nop
nop
nop
/* Setup clocking mode */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0
loop:
cmp r2, #1 @ this loop will wait for at least 100 cycles
streqh r1, [r0, #0x18] @ before issuing next request from MPU
add r2, r2, #1 @ on the 1st run code is loaded into I-cache
cmp r2, #16 @ and second run will set clocking mode
bne loop
nop
/* Setup clock dividers */
ldr r1, CKCTL_VAL
orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, DPLL1_BASE @ base of DPLL1 register
mov r1, #0x0010 @ set PLL_ENABLE
orr r1, r1, #0x2000 @ set IOB to new locking
orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
strh r1, [r0] @ write
locking:
ldrh r1, [r0] @ get DPLL value
tst r1, #0x01
beq locking @ while LOCK not set
/* Enable clock */
ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
mov r1, #(1 << 10) @ disable idle mode do not check
@ nWAKEUP pin, other remain active
strh r1, [r0, #0x04]
ldr r1, EN_CLK_VAL
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad
@ -76,9 +131,8 @@ crc1_bad:
crc2_bad:
ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET
b boot_2nd
tst r6, #3
beq one_is_bad @ one of them (or both) has bad crc
teq r6, #3
bne one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4]
ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ
@ -90,6 +144,7 @@ one_is_bad:
tst r6, #2
bne boot_2nd
@ We are doomed, so let user know.
hell:
ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08]
@ -171,6 +226,15 @@ CRC32_TABLE:
GPIO_BASE:
.word 0xfffce000
MPU_CLKM_BASE:
.word 0xfffece00
DPLL1_BASE:
.word 0xfffecf00
CKCTL_VAL:
.word OMAP5910_ARM_CKCTL
EN_CLK_VAL:
.word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION:
.word 0x0000ffe7

BIN
board/netstar/crcit
View File

Binary file not shown.

2
board/netstar/crcit.c
View File

@ -77,7 +77,7 @@ int main(int argc, char **argv)
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0);
if (nptr != '\0' && endptr == '\0')
if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver);
}
fprintf(stderr, "Usage: crcit [-v version] <image>\n");

5
board/netstar/netstar.c
View File

@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of NetStar board */
/* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692;
/* adress of boot parameters */
@ -51,15 +50,11 @@ int dram_init(void)
return 0;
}
extern void partition_flash(void);
int misc_init_r(void)
{
return 0;
}
extern void nand_init(void);
int board_late_init(void)
{
return 0;

27
board/netstar/setup.S
View File

@ -145,25 +145,23 @@ lowlevel_init:
nop
/* Setup clocking mode */
ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
ldrh r1, [r0, #0x18] @ get reset status
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
mov r2, #0 @ set wait counter to 100 clock cycles
icache_loop:
cmp r2, #0x01
streqh r1, [r0, #0x18]
add r2, r2, #0x01
cmp r2, #0x10
bne icache_loop
mov r2, #0
loop:
cmp r2, #1 @ this loop will wait for at least 100 cycles
streqh r1, [r0, #0x18] @ before issuing next request from MPU
add r2, r2, #1 @ on the 1st run code is loaded into I-cache
cmp r2, #16 @ and second run will set clocking mode
bne loop
nop
/* Setup clock divisors */
ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
/* Setup clock dividers */
ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock
strh r1, [r0, #0x00] @ setup clock divisors
strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@ -186,8 +184,7 @@ locking:
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
@ max delayed ( 32 x CLKIN )
strh r1, [r0, #0x0c]
strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
/* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE

2
board/netta/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o dsp.o codec.o
OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

370
board/netta/pcmcia.c Normal file
View File

@ -0,0 +1,370 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
#define PCMCIA_BOARD_MSG "NETTA"
static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
static void cfg_vppd(int no)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
return;
mask = vppd_masks[no];
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_vppd(int no, int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
return;
mask = vppd_masks[no];
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
static void cfg_vccd(int no)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
return;
mask = vccd_masks[no];
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_vccd(int no, int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
return;
mask = vccd_masks[no];
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static const unsigned short oc_mask = _BW(8);
static void cfg_oc(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask = oc_mask;
immap->im_ioport.iop_pcdir &= ~mask;
immap->im_ioport.iop_pcso &= ~mask;
immap->im_ioport.iop_pcint &= ~mask;
immap->im_ioport.iop_pcpar &= ~mask;
}
static int get_oc(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask = oc_mask;
int what;
what = !!(immap->im_ioport.iop_pcdat & mask);;
return what;
}
static const unsigned short shdn_mask = _BW(12);
static void cfg_shdn(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
mask = shdn_mask;
immap->im_ioport.iop_papar &= ~mask;
immap->im_ioport.iop_paodr &= ~mask;
immap->im_ioport.iop_padir |= mask;
}
static void set_shdn(int what)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
unsigned short mask;
mask = shdn_mask;
if (what)
immap->im_ioport.iop_padat |= mask;
else
immap->im_ioport.iop_padat &= ~mask;
}
static void cfg_ports (void)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
cfg_shdn();
cfg_oc();
/*
* Configure Port A for TPS2211 PC-Card Power-Interface Switch
*
* Switch off all voltages, assert shutdown
*/
set_vppd(0, 1); set_vppd(1, 1);
set_vccd(0, 0); set_vccd(1, 0);
set_shdn(1);
udelay(100000);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
int i;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
pipr,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((pipr & mask) == mask) {
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */
puts (" 5.0V card found: ");
} else {
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */
puts (" 3.3V card found: ");
}
/* Wait 500 ms; use this to check for over-current */
for (i=0; i<5000; ++i) {
if (!get_oc()) {
printf (" *** Overcurrent - Safety shutdown ***\n");
set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */
return (1);
}
udelay (100);
}
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
/* All voltages off / Hi-Z */
set_vppd(0, 1); set_vppd(1, 1);
set_vccd(0, 1); set_vccd(1, 1);
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
ushort sreg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
sreg = immap->im_ioport.iop_pcdat;
set_vppd(0, 1); set_vppd(1, 1);
switch(vcc) {
case 0:
break; /* Switch off */
case 33:
set_vccd(0, 1); set_vccd(1, 0);
break;
case 50:
set_vccd(0, 0); set_vccd(1, 1);
break;
default:
goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

7
board/ppmc7xx/config.mk
View File

@ -1,6 +1,6 @@
#
# (C) Copyright 2005
# Richard Danter, Wind River Systems
# Richard Danter, Wind River Systems
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -22,11 +22,6 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
#
#
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000

34
board/ppmc7xx/flash.c
View File

@ -1,10 +1,10 @@
/*
* flash.c
* -------
*
*
* Flash programming routines for the Wind River PPMC 74xx/7xx
* based on flash.c from the TQM8260 board.
*
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@ -27,13 +27,13 @@ void flash_reset (void)
{
unsigned long msr;
DWORD cmd_reset = 0x00F000F000F000F0LL;
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
msr = get_msr ();
set_msr (msr | MSR_FP);
write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
set_msr (msr);
}
}
@ -50,16 +50,16 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
set_msr (msr | MSR_FP);
/* Write auto-select command sequence */
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
/* Restore FPU */
set_msr (msr);
/* Read manufacturer ID */
flashtest = *(volatile DWORD*)baseaddr;
switch ((int)flashtest) {
@ -70,7 +70,7 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
info->flash_id = FLASH_MAN_FUJ;
break;
default:
/* No, faulty or unknown flash */
/* No, faulty or unknown flash */
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
@ -291,7 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0080008000800080LL, 0x00AA00AA00AA00AALL,
0x0055005500550055LL, 0x0030003000300030LL };
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
@ -319,7 +319,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
/* Enable FPU */
msr = get_msr();
set_msr ( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@ -344,7 +344,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
/* Restore FPU */
set_msr (msr);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
@ -373,7 +373,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
DONE:
/* reset to read mode */
flash_reset ();
printf (" done\n");
return 0;
}
@ -446,7 +446,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
DWORD data;
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x00A000A000A000A0LL };
for (data = 0, i = 0; i < 8; i++)
data = (data << 8) + *pdata++;
@ -454,11 +454,11 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
if ((*(DWORD*)dest & data) != data) {
return (2);
}
/* Enable FPU */
msr = get_msr();
set_msr( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@ -473,7 +473,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
/* Restore FPU */
set_msr(msr);
/* data polling for D7 */
start = get_timer (0);
while (*(volatile DWORD*)dest != data ) {

214
board/ppmc7xx/init.S
View File

@ -21,314 +21,314 @@ board_asm_init:
ori r4,r4,0x0000
lis r5,0xFEE0
ori r5,r5,0x0000
lis r3,0x8000 # ADDR_00
lis r3,0x8000 # ADDR_00
ori r3,r3,0x0000
stwbrx r3,0,r4
li r3,0x1057 # VENDOR
li r3,0x1057 # VENDOR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_02
lis r3,0x8000 # ADDR_02
ori r3,r3,0x0002
stwbrx r3,0,r4
li r3,0x0004 # ID
li r3,0x0004 # ID
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_04
lis r3,0x8000 # ADDR_04
ori r3,r3,0x0004
stwbrx r3,0,r4
li r3,0x0006 # PCICMD
li r3,0x0006 # PCICMD
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_06
lis r3,0x8000 # ADDR_06
ori r3,r3,0x0006
stwbrx r3,0,r4
li r3,0x00A0 # PCISTAT
li r3,0x00A0 # PCISTAT
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_08
lis r3,0x8000 # ADDR_08
ori r3,r3,0x0008
stwbrx r3,0,r4
li r3,0x10 # REVID
li r3,0x10 # REVID
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_09
lis r3,0x8000 # ADDR_09
ori r3,r3,0x0009
stwbrx r3,0,r4
li r3,0x00 # PROGIR
li r3,0x00 # PROGIR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0A
lis r3,0x8000 # ADDR_0A
ori r3,r3,0x000A
stwbrx r3,0,r4
li r3,0x00 # SUBCCODE
li r3,0x00 # SUBCCODE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0B
lis r3,0x8000 # ADDR_0B
ori r3,r3,0x000B
stwbrx r3,0,r4
li r3,0x06 # PBCCR
li r3,0x06 # PBCCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_0C
lis r3,0x8000 # ADDR_0C
ori r3,r3,0x000C
stwbrx r3,0,r4
li r3,0x08 # PCLSR
li r3,0x08 # PCLSR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_0D
lis r3,0x8000 # ADDR_0D
ori r3,r3,0x000D
stwbrx r3,0,r4
li r3,0x00 # PLTR
li r3,0x00 # PLTR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0E
lis r3,0x8000 # ADDR_0E
ori r3,r3,0x000E
stwbrx r3,0,r4
li r3,0x00 # HEADTYPE
li r3,0x00 # HEADTYPE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0F
lis r3,0x8000 # ADDR_0F
ori r3,r3,0x000F
stwbrx r3,0,r4
li r3,0x00 # BISTCTRL
li r3,0x00 # BISTCTRL
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_10
lis r3,0x8000 # ADDR_10
ori r3,r3,0x0010
stwbrx r3,0,r4
lis r3,0x0000 # LMBAR
lis r3,0x0000 # LMBAR
ori r3,r3,0x0008
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_14
lis r3,0x8000 # ADDR_14
ori r3,r3,0x0014
stwbrx r3,0,r4
lis r3,0xF000 # PCSRBAR
lis r3,0xF000 # PCSRBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_3C
lis r3,0x8000 # ADDR_3C
ori r3,r3,0x003C
stwbrx r3,0,r4
li r3,0x00 # ILR
li r3,0x00 # ILR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_3D
lis r3,0x8000 # ADDR_3D
ori r3,r3,0x003D
stwbrx r3,0,r4
li r3,0x01 # INTPIN
li r3,0x01 # INTPIN
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_3E
lis r3,0x8000 # ADDR_3E
ori r3,r3,0x003E
stwbrx r3,0,r4
li r3,0x00 # MIN_GNT
li r3,0x00 # MIN_GNT
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_3F
lis r3,0x8000 # ADDR_3F
ori r3,r3,0x003F
stwbrx r3,0,r4
li r3,0x00 # MAX_LAT
li r3,0x00 # MAX_LAT
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_40
lis r3,0x8000 # ADDR_40
ori r3,r3,0x0040
stwbrx r3,0,r4
li r3,0x00 # BUSNB
li r3,0x00 # BUSNB
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_41
lis r3,0x8000 # ADDR_41
ori r3,r3,0x0041
stwbrx r3,0,r4
li r3,0x00 # SBUSNB
li r3,0x00 # SBUSNB
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_46
lis r3,0x8000 # ADDR_46
ori r3,r3,0x0046
stwbrx r3,0,r4
# li r3,0xE080 # PCIARB
li r3,-0x1F80 # PCIARB
# li r3,0xE080 # PCIARB
li r3,-0x1F80 # PCIARB
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_70
lis r3,0x8000 # ADDR_70
ori r3,r3,0x0070
stwbrx r3,0,r4
li r3,0x0000 # PMCR1
li r3,0x0000 # PMCR1
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_72
lis r3,0x8000 # ADDR_72
ori r3,r3,0x0072
stwbrx r3,0,r4
li r3,0xC0 # PMCR2
li r3,0xC0 # PMCR2
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_73
lis r3,0x8000 # ADDR_73
ori r3,r3,0x0073
stwbrx r3,0,r4
li r3,0xEF # ODCR
li r3,0xEF # ODCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_74
lis r3,0x8000 # ADDR_74
ori r3,r3,0x0074
stwbrx r3,0,r4
li r3,0x7D00 # CLKDCR
li r3,0x7D00 # CLKDCR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_76
lis r3,0x8000 # ADDR_76
ori r3,r3,0x0076
stwbrx r3,0,r4
li r3,0x00 # MDCR
li r3,0x00 # MDCR
stb r3,0x2(r5)
lis r6,0xFCE0
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
lis r3,0x8000 # ADDR_78
lis r3,0x8000 # ADDR_78
ori r3,r3,0x0078
stwbrx r3,0,r4
lis r3,0xFCE0 # EUMBBAR
lis r3,0xFCE0 # EUMBBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_80
lis r3,0x8000 # ADDR_80
ori r3,r3,0x0080
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR1
lis r3,0xFFFF # MSADDR1
ori r3,r3,0x4000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_84
lis r3,0x8000 # ADDR_84
ori r3,r3,0x0084
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR2
lis r3,0xFFFF # MSADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_88
lis r3,0x8000 # ADDR_88
ori r3,r3,0x0088
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR1
lis r3,0x0303 # EMSADDR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_8C
lis r3,0x8000 # ADDR_8C
ori r3,r3,0x008C
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR2
lis r3,0x0303 # EMSADDR2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_90
lis r3,0x8000 # ADDR_90
ori r3,r3,0x0090
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR1
lis r3,0xFFFF # EMEADDR1
ori r3,r3,0x7F3F
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_94
lis r3,0x8000 # ADDR_94
ori r3,r3,0x0094
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR2
lis r3,0xFFFF # EMEADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_98
lis r3,0x8000 # ADDR_98
ori r3,r3,0x0098
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM1
lis r3,0x0303 # EXTEMEM1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_9C
lis r3,0x8000 # ADDR_9C
ori r3,r3,0x009C
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM2
lis r3,0x0303 # EXTEMEM2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A0
lis r3,0x8000 # ADDR_A0
ori r3,r3,0x00A0
stwbrx r3,0,r4
li r3,0x03 # MEMBNKEN
li r3,0x03 # MEMBNKEN
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_A3
lis r3,0x8000 # ADDR_A3
ori r3,r3,0x00A3
stwbrx r3,0,r4
li r3,0x00 # MEMPMODE
li r3,0x00 # MEMPMODE
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_B8
lis r3,0x8000 # ADDR_B8
ori r3,r3,0x00B8
stwbrx r3,0,r4
li r3,0x00 # ECCCNT
li r3,0x00 # ECCCNT
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_B9
lis r3,0x8000 # ADDR_B9
ori r3,r3,0x00B9
stwbrx r3,0,r4
li r3,0x00 # ECCTRG
li r3,0x00 # ECCTRG
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C0
lis r3,0x8000 # ADDR_C0
ori r3,r3,0x00C0
stwbrx r3,0,r4
li r3,0xFF # ERRENR1
li r3,0xFF # ERRENR1
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C1
lis r3,0x8000 # ADDR_C1
ori r3,r3,0x00C1
stwbrx r3,0,r4
li r3,0x00 # ERRDR1
li r3,0x00 # ERRDR1
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C3
lis r3,0x8000 # ADDR_C3
ori r3,r3,0x00C3
stwbrx r3,0,r4
li r3,0x50 # IPBESR
li r3,0x50 # IPBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C4
lis r3,0x8000 # ADDR_C4
ori r3,r3,0x00C4
stwbrx r3,0,r4
li r3,0xBF # ERRENR2
li r3,0xBF # ERRENR2
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C5
lis r3,0x8000 # ADDR_C5
ori r3,r3,0x00C5
stwbrx r3,0,r4
li r3,0x00 # ERRDR2
li r3,0x00 # ERRDR2
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C7
lis r3,0x8000 # ADDR_C7
ori r3,r3,0x00C7
stwbrx r3,0,r4
li r3,0x00 # PCIBESR
li r3,0x00 # PCIBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C8
lis r3,0x8000 # ADDR_C8
ori r3,r3,0x00C8
stwbrx r3,0,r4
lis r3,0x0000 # BERRADDR
lis r3,0x0000 # BERRADDR
ori r3,r3,0xE0FE
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_E0
lis r3,0x8000 # ADDR_E0
ori r3,r3,0x00E0
stwbrx r3,0,r4
li r3,0xC0 # AMBOR
li r3,0xC0 # AMBOR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_F4
lis r3,0x8000 # ADDR_F4
ori r3,r3,0x00F4
stwbrx r3,0,r4
lis r3,0x0000 # MCCR2
lis r3,0x0000 # MCCR2
ori r3,r3,0x020C
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F8
lis r3,0x8000 # ADDR_F8
ori r3,r3,0x00F8
stwbrx r3,0,r4
lis r3,0x0230 # MCCR3
lis r3,0x0230 # MCCR3
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_FC
lis r3,0x8000 # ADDR_FC
ori r3,r3,0x00FC
stwbrx r3,0,r4
lis r3,0x2532 # MCCR4
lis r3,0x2532 # MCCR4
ori r3,r3,0x2220
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F0
lis r3,0x8000 # ADDR_F0
ori r3,r3,0x00F0
stwbrx r3,0,r4
lis r3,0xFFC8 # MCCR1
lis r3,0xFFC8 # MCCR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A8
lis r3,0x8000 # ADDR_A8
ori r3,r3,0x00A8
stwbrx r3,0,r4
lis r3,0xFF14 # PICR1
lis r3,0xFF14 # PICR1
ori r3,r3,0x1CC8
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_AC
lis r3,0x8000 # ADDR_AC
ori r3,r3,0x00AC
stwbrx r3,0,r4
lis r3,0x0000 # PICR2
lis r3,0x0000 # PICR2
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5

22
board/ppmc7xx/ppmc7xx.c
View File

@ -1,9 +1,9 @@
/*
* ppmc7xx.c
* ---------
*
*
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
*
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@ -24,7 +24,7 @@ extern void _start_warm(void);
/*
* initdram()
*
*
* This function normally initialises the (S)DRAM of the system. For this board
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
@ -37,12 +37,12 @@ long initdram( int board_type )
/*
* after_reloc()
*
*
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
* us an opportunity to do some additional setup before the rest of the system
* is initialised. We don't need to do anything, so we just call board_init_r()
* which should never return.
*/
*/
void after_reloc( ulong dest_addr, gd_t* gd )
{
/* Jump to the main U-Boot board init code */
@ -52,7 +52,7 @@ void after_reloc( ulong dest_addr, gd_t* gd )
/*
* checkboard()
*
*
* We could do some board level checks here, such as working out what version
* it is, but for this board we simply display it's name (on the console).
*/
@ -65,7 +65,7 @@ int checkboard( void )
/*
* misc_init_r
*
*
* Used for other setup which needs to be done late in the bring-up phase.
*/
int misc_init_r( void )
@ -78,27 +78,27 @@ int misc_init_r( void )
/* Enable the I-Cache */
icache_enable();
return 0;
}
/*
* do_reset()
*
*
* Shell command to reset the board.
*/
void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
printf( "Resetting...\n" );
/* Disabe and invalidate cache */
icache_disable();
dcache_disable();
/* Jump to warm start (in RAM) */
_start_warm();
/* Should never get here */
while(1);
}

2
board/r360mpi/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o flash.o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

236
board/r360mpi/pcmcia.c Normal file
View File

@ -0,0 +1,236 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "R360MPI"
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Ports A, B & C pins for
* 5 Volts Enable and 3 Volts enable
*/
immap->im_ioport.iop_pcpar &= ~(0x0400);
immap->im_ioport.iop_pcso &= ~(0x0400);/*
immap->im_ioport.iop_pcdir |= 0x0400;*/
immap->im_ioport.iop_papar &= ~(0x0200);/*
immap->im_ioport.iop_padir |= 0x0200;*/
#if 0
immap->im_ioport.iop_pbpar &= ~(0xC000);
immap->im_ioport.iop_pbdir &= ~(0xC000);
#endif
/* remove all power */
immap->im_ioport.iop_pcdat |= 0x0400;
immap->im_ioport.iop_padat |= 0x0200;
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
immap->im_ioport.iop_pcdat &= ~(0x4000);
puts (" 5.0V card found: ");
} else {
immap->im_ioport.iop_padat &= ~(0x0002);
puts (" 3.3V card found: ");
}
immap->im_ioport.iop_pcdir |= 0x0400;
immap->im_ioport.iop_padir |= 0x0200;
#if 0
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
cp->cp_pbdir &= ~(0x0020 | 0x0010);
cp->cp_pbpar &= ~(0x0020 | 0x0010);
udelay(500000);
#endif
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* remove all power */
immap->im_ioport.iop_pcdat |= 0x0400;
immap->im_ioport.iop_padat |= 0x0200;
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Ports A & C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn off all power
*/
debug ("PCMCIA power OFF\n");
immap->im_ioport.iop_pcpar &= ~(0x0400);
immap->im_ioport.iop_pcso &= ~(0x0400);/*
immap->im_ioport.iop_pcdir |= 0x0400;*/
immap->im_ioport.iop_papar &= ~(0x0200);/*
immap->im_ioport.iop_padir |= 0x0200;*/
immap->im_ioport.iop_pcdat |= 0x0400;
immap->im_ioport.iop_padat |= 0x0200;
reg = 0;
switch(vcc) {
case 0: break;
case 33: reg |= 0x0200; break;
case 50: reg |= 0x0400; break;
default: goto done;
}
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
if (reg & 0x0200)
immap->im_ioport.iop_pcdat &= !reg;
if (reg & 0x0400)
immap->im_ioport.iop_padat &= !reg;
immap->im_ioport.iop_pcdir |= 0x0200;
immap->im_ioport.iop_padir |= 0x0400;
if (reg) {
debug ("PCMCIA powered at %sV\n",
(reg&0x0400) ? "5.0" : "3.3");
} else {
debug ("PCMCIA powered down\n");
}
done:
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CCONFIG_PCMCIA */

47
board/sbc2410x/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := sbc2410x.o flash.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

23
board/sbc2410x/config.mk Normal file
View File

@ -0,0 +1,23 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
#
# see http://www.samsung.com/ for more information on SAMSUNG
#
#
# SMDK2410 has 1 bank of 64 MB DRAM
#
# 3000'0000 to 3400'0000
#
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000
#
# we load ourself to 33F8'0000
#
# download area is 3300'0000
TEXT_BASE = 0x33F80000

431
board/sbc2410x/flash.c Normal file
View File

@ -0,0 +1,431 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
ulong myflush (void);
#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define CMD_READ_ARRAY 0x000000F0
#define CMD_UNLOCK1 0x000000AA
#define CMD_UNLOCK2 0x00000055
#define CMD_ERASE_SETUP 0x00000080
#define CMD_ERASE_CONFIRM 0x00000030
#define CMD_PROGRAM 0x000000A0
#define CMD_UNLOCK_BYPASS 0x00000020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
#define BIT_ERASE_DONE 0x00000080
#define BIT_RDY_MASK 0x00000080
#define BIT_PROGRAM_ERROR 0x00000020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define READY 1
#define ERR 2
#define TMO 4
/*-----------------------------------------------------------------------
*/
ulong flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
#if defined(CONFIG_AMD_LV400)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV400B & FLASH_TYPEMASK);
#elif defined(CONFIG_AMD_LV800)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV800B & FLASH_TYPEMASK);
#else
#error "Unknown flash configured"
#endif
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured too many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j <= 3) {
/* 1st one is 16 KB */
if (j == 0) {
flash_info[i].start[j] =
flashbase + 0;
}
/* 2nd and 3rd are both 8 KB */
if ((j == 1) || (j == 2)) {
flash_info[i].start[j] =
flashbase + 0x4000 + (j -
1) *
0x2000;
}
/* 4th 32 KB */
if (j == 3) {
flash_info[i].start[j] =
flashbase + 0x8000;
}
} else {
flash_info[i].start[j] =
flashbase + (j - 3) * MAIN_SECT_SIZE;
}
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV400B & FLASH_TYPEMASK):
printf ("1x Amd29LV400BB (4Mbit)\n");
break;
case (AMD_ID_LV800B & FLASH_TYPEMASK):
printf ("1x Amd29LV800BB (8Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
Done:;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
ushort result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
chip = 0;
do {
result = *addr;
/* check timeout */
if (get_timer_masked () >
CFG_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip = TMO;
break;
}
if (!chip
&& (result & 0xFFFF) & BIT_ERASE_DONE)
chip = READY;
if (!chip
&& (result & 0xFFFF) & BIT_PROGRAM_ERROR)
chip = ERR;
} while (!chip);
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip == ERR) {
rc = ERR_PROG_ERROR;
goto outahere;
}
if (chip == TMO) {
rc = ERR_TIMOUT;
goto outahere;
}
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
}
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked (10000);
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash
*/
volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
int rc = ERR_OK;
int cflag, iflag;
int chip;
/*
* Check if Flash is (sufficiently) erased
*/
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
*addr = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait until flash is ready */
chip = 0;
do {
result = *addr;
/* check timeout */
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
chip = ERR | TMO;
break;
}
if (!chip && ((result & 0x80) == (data & 0x80)))
chip = READY;
if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
result = *addr;
if ((result & 0x80) == (data & 0x80))
chip = READY;
else
chip = ERR;
}
} while (!chip);
*addr = CMD_READ_ARRAY;
if (chip == ERR || *addr != data)
rc = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
int l;
int i, rc;
ushort data;
wp = (addr & ~1); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
for (; i < 2 && cnt > 0; ++i) {
data = (data >> 8) | (*src++ << 8);
--cnt;
++cp;
}
for (; cnt == 0 && i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
if ((rc = write_hword (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
}
/*
* handle word aligned part
*/
while (cnt >= 2) {
data = *((vu_short *) src);
if ((rc = write_hword (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) {
return ERR_OK;
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 8);
--cnt;
}
for (; i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
return write_hword (info, wp, data);
}

163
board/sbc2410x/lowlevel_init.S Normal file
View File

@ -0,0 +1,163 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* Modified for the friendly-arm SBC-2410X by
* (C) Copyright 2005
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
/*
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
*
* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
*/
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW16)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
#define B0_Tacs 0x0
#define B0_Tcos 0x0
#define B0_Tacc 0x7
#define B0_Tcoh 0x0
#define B0_Tah 0x0
#define B0_Tacp 0x0
#define B0_PMC 0x0
#define B1_Tacs 0x0
#define B1_Tcos 0x0
#define B1_Tacc 0x7
#define B1_Tcoh 0x0
#define B1_Tah 0x0
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0xc
#define B3_Tcos 0x7
#define B3_Tacc 0xf
#define B3_Tcoh 0x1
#define B3_Tah 0x0
#define B3_Tacp 0x0
#define B3_PMC 0x0
#define B4_Tacs 0x0
#define B4_Tcos 0x0
#define B4_Tacc 0x7
#define B4_Tcoh 0x0
#define B4_Tah 0x0
#define B4_Tacp 0x0
#define B4_PMC 0x0
#define B5_Tacs 0xc
#define B5_Tcos 0x7
#define B5_Tacc 0xf
#define B5_Tcoh 0x1
#define B5_Tah 0x0
#define B5_Tacp 0x0
#define B5_PMC 0x0
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
/* REFRESH parameter */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFCNT 0x0459
/**************************************/
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */
ldr r0, =SMRDATA
ldr r1, _TEXT_BASE
sub r0, r0, r1
ldr r1, =BWSCON /* Bus Width Status Controller */
add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
/* everything is fine now */
mov pc, lr
.ltorg
/* the literal pools origin */
SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.word 0xb2
.word 0x30
.word 0x30

183
board/sbc2410x/sbc2410x.c Normal file
View File

@ -0,0 +1,183 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2005
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <s3c2410.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#endif
/* ------------------------------------------------------------------------- */
#define FCLK_SPEED 1
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
#define M_MDIV 0x5c
#define M_PDIV 0x4
#define M_SDIV 0x0
#endif
#define USB_CLOCK 1
#if USB_CLOCK==0
#define U_M_MDIV 0xA1
#define U_M_PDIV 0x3
#define U_M_SDIV 0x1
#elif USB_CLOCK==1
#define U_M_MDIV 0x48
#define U_M_PDIV 0x3
#define U_M_SDIV 0x2
#endif
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x00044556;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFF95FF3A;
gpio->GPGUP = 0x0000FFFF;
gpio->GPHCON = 0x0016FAAA;
gpio->GPHUP = 0x000007FF;
gpio->EXTINT0=0x22222222;
gpio->EXTINT1=0x22222222;
gpio->EXTINT2=0x22222222;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
icache_enable();
dcache_enable();
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
extern ulong nand_probe(ulong physadr);
static inline void NF_Reset(void)
{
int i;
NF_SetCE(NFCE_LOW);
NF_Cmd(0xFF); /* reset command */
for(i = 0; i < 10; i++); /* tWB = 100ns. */
NF_WaitRB(); /* wait 200~500us; */
NF_SetCE(NFCE_HIGH);
}
static inline void NF_Init(void)
{
#if 1
#define TACLS 0
#define TWRPH0 3
#define TWRPH1 0
#else
#define TACLS 0
#define TWRPH0 4
#define TWRPH1 2
#endif
NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
/* 1 1 1 1, 1 xxx, r xxx, r xxx */
/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
NF_Reset();
}
void nand_init(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
NF_Init();
#ifdef DEBUG
printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
#endif
printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */

56
board/sbc2410x/u-boot.lds Normal file
View File

@ -0,0 +1,56 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

40
board/spc1920/Makefile Normal file
View File

@ -0,0 +1,40 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

35
board/spc1920/config.mk Normal file
View File

@ -0,0 +1,35 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
# MPC885ADS boards
#
#TEXT_BASE = 0xFE000000
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920
HOST_CFLAGS += -I$(TOPDIR)/board/spc1920
HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920

14
board/spc1920/pld.h Normal file
View File

@ -0,0 +1,14 @@
#ifndef __PLD_H__
#define __PLD_H__
typedef struct spc1920_pld {
uchar com1_en;
uchar dsp_reset;
uchar dsp_hpi_on;
uchar codec_dsp_power_en;
uchar clk2_en;
uchar clk3_select;
uchar clk4_select;
} spc1920_pld_t;
#endif /* __PLD_H__ */

236
board/spc1920/spc1920.c Normal file
View File

@ -0,0 +1,236 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mpc8xx.h>
#include "pld.h"
#define _NOT_USED_ 0xFFFFFFFF
/* #define debug(fmt,args...) printf (fmt ,##args) */
static long int dram_size (long int, long int *, long int);
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMB RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMB RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMB RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMB RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMB RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMB RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMB RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
long int initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
long int size_b0;
long int size8, size9;
int i;
/*
* Configure UPMB for SDRAM
*/
upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
udelay(100);
memctl->memc_mptpr = CFG_MPTPR;
/* burst length=4, burst type=sequential, CAS latency=2 */
memctl->memc_mar = CFG_MAR;
/*
* Map controller bank 1 to the SDRAM bank at preliminary address.
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
/* initialize memory address register */
memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
/* mode initialization (offset 5) */
udelay (200); /* 0x80006105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
udelay (1); /* 0x80006130 */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
udelay (1); /* 0x80006130 */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
udelay (1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
udelay (200);
/* Need at least 10 DRAM accesses to stabilize */
for (i = 0; i < 10; ++i) {
volatile unsigned long *addr =
(volatile unsigned long *) CFG_SDRAM_BASE;
unsigned long val;
val = *(addr + i);
*(addr + i) = val;
}
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
udelay (500);
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
udelay (500);
}
/*
* Final mapping:
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
udelay (1000);
/* PLD Setup */
memctl->memc_or5 = CFG_OR5_PRELIM;
memctl->memc_br5 = CFG_BR5_PRELIM;
udelay(1000);
return (size_b0);
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mbmr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mbmr = mbmr_value;
return (get_ram_size (base, maxsize));
}
/************* other stuff ******************/
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/* Turn on LED PD9 */
immap->im_ioport.iop_pdpar &= ~(0x0040);
immap->im_ioport.iop_pddir |= 0x0040;
immap->im_ioport.iop_pddat |= 0x0040;
/* Enable PD10 (COM2_EN) */
immap->im_ioport.iop_pdpar &= ~0x0020;
immap->im_ioport.iop_pddir &= ~0x4000;
immap->im_ioport.iop_pddir |= 0x0020;
immap->im_ioport.iop_pddat |= 0x0020;
#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
immap->im_cpm.cp_simode |= 0x7000;
immap->im_cpm.cp_simode &= ~(0x8000);
#endif
return 0;
}
int checkboard (void)
{
puts("Board: SPC1920\n");
return 0;
}

144
board/spc1920/u-boot.lds Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/tqm5200/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o cmd_stk52xx.o
OBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

6
board/tqm5200/cmd_stk52xx.c
View File

@ -22,7 +22,7 @@
*/
/*
* SKT52XX specific functions
* STK52XX specific functions
*/
/*#define DEBUG*/
@ -30,6 +30,7 @@
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
#if defined (CONFIG_STK52XX)
#define DEFAULT_VOL 45
#define DEFAULT_FREQ 500
@ -60,7 +61,6 @@ static int spi_transmit(unsigned char data);
static void pcm1772_write_reg(unsigned char addr, unsigned char data);
static void set_attenuation(unsigned char attenuation);
#ifdef CONFIG_STK52XX
static void spi_init(void)
{
struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
@ -1209,7 +1209,7 @@ U_BOOT_CMD(
fkt , 4, 1, cmd_fkt,
"fkt - Function test routines\n",
"led number on/off\n"
" - 'number's like printed on SKT52XX board\n"
" - 'number's like printed on STK52XX board\n"
"fkt can\n"
" - loopback plug for X83 required\n"
"fkt rs232 number\n"

104
board/tqm5200/cmd_tb5200.c Normal file
View File

@ -0,0 +1,104 @@
/*
* (C) Copyright 2005 - 2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* TB5200 specific functions
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
#if defined (CONFIG_TB5200)
#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
static void led_init(void)
{
struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
/* configure timer 4 for simple GPIO output */
gpt->gpt4.emsr |= 0x00000024;
}
int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
led_init();
if (strcmp (argv[1], "on") == 0) {
debug ("switch status LED on\n");
gpt->gpt4.emsr |= (1 << 4);
} else if (strcmp (argv[1], "off") == 0) {
debug ("switch status LED off\n");
gpt->gpt4.emsr &= ~(1 << 4);
} else {
printf ("Usage:\nled on/off\n");
return 1;
}
return 0;
}
static void sm501_backlight (unsigned int state)
{
if (state == 1) {
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
(1 << 26) | (1 << 27);
} else if (state == 0)
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
~((1 << 26) | (1 << 27));
}
int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (strcmp (argv[1], "on") == 0) {
debug ("switch backlight on\n");
sm501_backlight (1);
} else if (strcmp (argv[1], "off") == 0) {
debug ("switch backlight off\n");
sm501_backlight (0);
} else {
printf ("Usage:\nbacklight on/off\n");
return 1;
}
return 0;
}
U_BOOT_CMD(
led , 2, 1, cmd_led,
"led - switch status LED on or off\n",
"on/off\n"
);
U_BOOT_CMD(
backlight , 2, 1, cmd_backlight,
"backlight - switch backlight on or off\n",
"on/off\n"
);
#endif /* CONFIG_STK52XX */
#endif /* CFG_CMD_BSP */

5
board/tqm5200/config.mk
View File

@ -28,12 +28,17 @@
#
# 0xFC000000 boot low (standard configuration with room for max 64 MByte
# Flash ROM)
# 0xFFF00000 boot high (for a backup copy of U-Boot)
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot low
TEXT_BASE = 0xFC000000
## For a backup copy of U-Boot at the end of flash: boot high
# TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif

68
board/tqm5200/tqm5200.c
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2003-2004
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2004-2005
* (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
@ -30,6 +30,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
@ -101,6 +102,8 @@ long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
#ifndef CFG_RAMBOOT
ulong test1, test2;
@ -190,11 +193,31 @@ long int initdram (int board_type)
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
/* return dramsize + dramsize2; */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
}
#if defined(CONFIG_TQM5200_B)
return dramsize + dramsize2;
#else
return dramsize;
#endif /* CONFIG_TQM5200_B */
}
#elif defined(CONFIG_MGT5100)
@ -250,20 +273,36 @@ long int initdram (int board_type)
int checkboard (void)
{
#if defined (CONFIG_AEVFIFO)
#if defined(CONFIG_AEVFIFO)
puts ("Board: AEVFIFO\n");
return 0;
#endif
#if defined (CONFIG_TQM5200)
puts ("Board: TQM5200 (TQ-Components GmbH)\n");
#if defined(CONFIG_TQM5200S)
# define MODULE_NAME "TQM5200S"
#else
# define MODULE_NAME "TQM5200"
#endif
#if defined (CONFIG_STK52XX)
puts (" on a STK52XX baseboard\n");
#if defined(CONFIG_STK52XX)
# define CARRIER_NAME "STK52xx"
#elif defined(CONFIG_TB5200)
# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
# define CARRIER_NAME "Cam5200"
#else
# error "Unknown carrier board"
#endif
puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
" on a " CARRIER_NAME " carrier board\n");
return 0;
}
#undef MODULE_NAME
#undef CARRIER_NAME
void flash_preinit(void)
{
/*
@ -405,7 +444,6 @@ int board_early_init_r (void)
#endif
#endif /* CONFIG_PS2MULT */
#if defined(CONFIG_CS_AUTOCONF)
int last_stage_init (void)
{
/*
@ -500,7 +538,6 @@ int last_stage_init (void)
return 0;
}
#endif /* CONFIG_CS_AUTOCONF */
#ifdef CONFIG_VIDEO_SM501
@ -567,9 +604,14 @@ void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_STK52XX)
#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
} else if (line_number == 2) {
strcpy (info, " on a STK52XX baseboard");
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#endif
#if defined (CONFIG_TB5200)
strcpy (info, " on a TB5200 carrier board");
#endif
#endif
}
else {

6
board/tqm834x/tqm834x.c
View File

@ -424,10 +424,12 @@ static void set_ddr_config(void) {
* which has to be written with a certain value defined by
* errata sheet.
*/
u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
#if defined(DDR_CASLAT_20)
*((u8 *)im + 0x2f00) = 0x201c0000;
*reserved_p = 0x201c0000;
#else
*((u8 *)im + 0x2f00) = 0x202c0000;
*reserved_p = 0x202c0000;
#endif
}
}

9
board/tqm85xx/tqm85xx.c
View File

@ -27,10 +27,6 @@
* MA 02111-1307 USA
*/
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
@ -47,6 +43,10 @@ void local_bus_init (void);
long int fixed_sdram (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
@ -423,4 +423,3 @@ int board_early_init_r (void)
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

5
board/tqm8xx/flash.c
View File

@ -33,12 +33,13 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
&& !defined(CONFIG_TQM885D)
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
# endif
#endif /* CONFIG_TQM8xxL/M, !TQM866M */
#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
#ifndef CFG_ENV_ADDR
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)

22
board/tqm8xx/tqm8xx.c
View File

@ -119,6 +119,10 @@ int checkboard (void)
gd->board_type = 'M';
}
if ((*(s + 6) == 'D')) { /* a TQM885D type */
gd->board_type = 'D';
}
for (; *s; ++s) {
if (*s == ' ')
break;
@ -178,7 +182,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
(board_type != 'M') &&
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
@ -197,7 +202,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
(board_type != 'M') &&
(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
@ -214,8 +220,7 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@ -223,8 +228,7 @@ long int initdram (int board_type)
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
@ -233,8 +237,7 @@ long int initdram (int board_type)
/*
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
@ -255,7 +258,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
(board_type != 'M') &&
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
/*
* Check Bank 1 Memory Size
* use current column settings

8
board/trab/auto_update.c
View File

@ -57,9 +57,9 @@
* valid then run it.
* 2) if preinst.img is found load it into memory. If it is
* valid then run it. Update the EEPROM.
* 3) if firmware.img is found load it into memory. If it is valid,
* 3) if firmw_01.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
* 4) if kernel.img is found load it into memory. If it is valid,
* 4) if kernl_01.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
* 5) if app.img is found load it into memory. If it is valid,
* burn it into FLASH and update the EEPROM.
@ -81,8 +81,8 @@
/* possible names of files on the USB stick. */
#define AU_PREPARE "prepare.img"
#define AU_PREINST "preinst.img"
#define AU_FIRMWARE "firmware.img"
#define AU_KERNEL "kernel.img"
#define AU_FIRMWARE "firmw_01.img"
#define AU_KERNEL "kernl_01.img"
#define AU_APP "app.img"
#define AU_DISK "disk.img"
#define AU_POSTINST "postinst.img"

32
board/trab/flash.c
View File

@ -281,10 +281,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
if (chip1 == ERR || chip2 == ERR) {
rc = ERR_PROG_ERROR;
printf ("Flash erase error\n");
goto outahere;
}
if (chip1 == TMO) {
rc = ERR_TIMOUT;
printf ("Flash erase timeout error\n");
goto outahere;
}
}
@ -340,7 +342,9 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
#endif
iflag = disable_interrupts ();
*addr = CMD_PROGRAM;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
@ -352,7 +356,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
result = *addr;
/* check timeout */
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
chip1 = ERR | TMO;
break;
}
@ -384,8 +388,13 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
*addr = CMD_READ_ARRAY;
if (chip1 == ERR || chip2 == ERR || *addr != data)
if (chip1 == ERR || chip2 == ERR || *addr != data) {
rc = ERR_PROG_ERROR;
printf ("Flash program error\n");
debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, "
"data: %#lx\n",
chip1, chip2, addr, *addr, data);
}
if (iflag)
enable_interrupts ();
@ -408,10 +417,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
int l;
int i, rc;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
wp = (addr & ~3); /* get lower word aligned address */
/*
@ -479,9 +484,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
Done:
MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
return (rc);
}
@ -515,7 +517,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = 0x00FF00FF; /* restore read mode */
addr[0] = CMD_READ_ARRAY; /* restore read mode */
debug ("## flash_init: unknown manufacturer\n");
return (0); /* no or unknown flash */
}
@ -530,7 +532,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 71;
info->size = 0x00800000;
addr[0] = 0x00FF00FF; /* restore read mode */
addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 8 MB */
case AMD_ID_LV640U:
@ -538,7 +540,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 128;
info->size = 0x01000000;
addr[0] = 0x00F000F0; /* restore read mode */
addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 16 MB */
case MX_ID_LV320B:
@ -546,13 +548,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 71;
info->size = 0x00800000;
addr[0] = 0x00FF00FF; /* restore read mode */
addr[0] = CMD_READ_ARRAY; /* restore read mode */
break; /* => 8 MB */
default:
debug ("## flash_init: unknown flash chip\n");
info->flash_id = FLASH_UNKNOWN;
addr[0] = 0x00FF00FF; /* restore read mode */
addr[0] = CMD_READ_ARRAY; /* restore read mode */
return (0); /* => no or unknown flash */
}

22
board/trab/vfd.c
View File

@ -251,19 +251,17 @@ void create_vfd_table(void)
unsigned long adr = gd->fb_base;
unsigned int bit_nr = 0;
if (vfd_table[x][y][color][display][entry]) {
pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;
/*
* wrap arround if offset
* (see manual S3C2400)
*/
if (pixel>=FRAME_BUF_SIZE*8)
pixel = pixel-(FRAME_BUF_SIZE*8);
adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
bit_nr = pixel%8;
bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;
/*
* wrap arround if offset
* (see manual S3C2400)
*/
if (pixel>=FRAME_BUF_SIZE*8)
pixel = pixel-(FRAME_BUF_SIZE*8);
adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
bit_nr = pixel%8;
bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
}
adr_vfd_table[x][y][color][display][entry] = adr;
bit_vfd_table[x][y][color][display][entry] = bit_nr;
}

4
board/uc100/Makefile
View File

@ -25,8 +25,8 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
#OBJS = $(BOARD).o flash.o
OBJS = $(BOARD).o
#OBJS = $(BOARD).o flash.o pcmcia.o
OBJS = $(BOARD).o pcmcia.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

198
board/uc100/pcmcia.c Normal file
View File

@ -0,0 +1,198 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "UC100"
/*
* Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
* This leads to board-hangup! (sr, 8 Dez. 2004)
*/
static void cfg_ports (void)
{
volatile immap_t *immap;
immap = (immap_t *)CFG_IMMR;
/*
* Configure Port A for MAX1602 PC-Card Power-Interface Switch
*/
immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
immap->im_ioport.iop_padat);
}
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
immap = (immap_t *)CFG_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
if ((reg & mask) == mask) {
puts (" 5.0V card found: ");
} else {
puts (" 3.3V card found: ");
}
/* switch VCC on */
immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
udelay(10000);
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/* switch VCC off */
immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
PCMCIA_PGCRX(_slot_) = reg;
udelay(10000);
return (0);
}
#endif /* CFG_CMD_PCMCIA */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
* Turn all power pins to Hi-Z
*/
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(_slot_) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
slot+'A');
return (0);
}
#endif /* CONFIG_PCMCIA */

5
common/cmd_bdinfo.c
View File

@ -61,11 +61,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440SP)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */

2
common/cmd_mem.c
View File

@ -707,7 +707,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#if defined(CFG_MEMTEST_SCRATCH)
vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH;
#else
vu_long *dummy = NULL;
vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */
#endif
int j;
int iterations = 1;

5
common/cmd_mii.c
View File

@ -57,6 +57,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
int rcode = 0;
char *devname;
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
#endif

3471
common/cmd_pcmcia.c
View File

File diff suppressed because it is too large Load Diff

2
common/cmd_reginfo.c
View File

@ -328,7 +328,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
printf ("\tSDRAMCS0: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
printf ("\tSDRAMCS0: %08X\n",
printf ("\tSDRAMCS1: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#endif /* CONFIG_MPC5200 */
return 0;

7
common/cmd_usb.c
View File

@ -186,7 +186,7 @@ void usb_display_conf_desc(struct usb_config_descriptor *config,struct usb_devic
void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,struct usb_device *dev)
{
printf(" Interface: %d\n",ifdesc->bInterfaceNumber);
printf(" - Alternate Settings %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints);
printf(" - Alternate Setting %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints);
printf(" - Class ");
usb_display_class_sub(ifdesc->bInterfaceClass,ifdesc->bInterfaceSubClass,ifdesc->bInterfaceProtocol);
printf("\n");
@ -444,6 +444,7 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int i;
struct usb_device *dev = NULL;
extern char usb_started;
#ifdef CONFIG_USB_STORAGE
block_dev_desc_t *stor_dev;
#endif
@ -477,6 +478,10 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
usb_stop();
return 0;
}
if (!usb_started) {
printf("USB is stopped. Please issue 'usb start' first.\n");
return 1;
}
if (strncmp(argv[1],"tree",4) == 0) {
printf("\nDevice Tree:\n");
usb_show_tree(usb_get_dev_index(0));

Some files were not shown because too many files have changed in this diff Show More