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snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS = timer.o clock.o prcmu.o
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COBJS = timer.o clock.o prcmu.o cpu.o
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SOBJS = lowlevel.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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41
arch/arm/cpu/armv7/u8500/cpu.c
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41
arch/arm/cpu/armv7/u8500/cpu.c
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@ -0,0 +1,41 @@
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/*
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* Copyright (C) 2012 Linaro Limited
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* Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* Based on original code from Joakim Axelsson at ST-Ericsson
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* (C) Copyright 2010 ST-Ericsson
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/prcmu.h>
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#ifdef CONFIG_ARCH_CPU_INIT
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/*
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* SOC specific cpu init
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*/
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int arch_cpu_init(void)
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{
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db8500_prcmu_init();
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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@ -40,6 +40,8 @@
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#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
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#define I2C_MBOX_BIT (1 << 5)
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static int prcmu_is_ready(void)
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{
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int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
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@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
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return -1;
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}
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}
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void u8500_prcmu_enable(u32 *reg)
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{
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writel(readl(reg) | (1 << 8), reg);
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}
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void db8500_prcmu_init(void)
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{
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/* Enable timers */
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writel(1 << 17, PRCM_TCR);
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u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
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/* PER4CLK does not exist */
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u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
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/* Only exists in ED but is always ok to write to */
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u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
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u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
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/* Clean up the mailbox interrupts after pre-u-boot code. */
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writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
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}
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@ -27,12 +27,23 @@
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#define I2C_RD_OK 2
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#define I2CWRITE 0
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#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE
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#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */
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#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */
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#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */
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#define PRCMU_BASE U8500_PRCMU_BASE
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#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
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#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
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#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
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#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
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#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
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#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
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#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
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#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
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#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
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#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
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#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
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#define PRCM_TCR (PRCMU_BASE + 0x1C8)
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#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44)
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#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4)
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#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC)
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/* Mailbox 5 Requests */
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#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
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#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
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@ -52,4 +63,7 @@
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extern int prcmu_i2c_read(u8 reg, u16 slave);
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extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
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void u8500_prcmu_enable(u32 *reg);
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void db8500_prcmu_init(void);
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#endif /* __MACH_PRCMU_FW_V1_H */
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@ -26,8 +26,8 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_MMC
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#include <asm/arch/prcmu.h>
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#ifdef CONFIG_MMC
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#include "../../../drivers/mmc/arm_pl180_mmci.h"
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#endif
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@ -42,7 +42,6 @@
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* SGA: Smart Graphic accelerator
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* B2R2: Graphic blitter
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*/
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#define PRCMU_BASE CFG_PRCMU_BASE /* 0x80157000 for U8500 */
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#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
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#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
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#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
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@ -31,6 +31,7 @@
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#define CONFIG_SNOWBALL
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_ARCH_CPU_INIT
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/*
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* High Level Configuration Options
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