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ARC: Cache: Fix SLC operations when SLC is bypassed for data
If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory. If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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@ -168,6 +168,15 @@ static inline bool slc_exists(void)
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return false;
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}
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static inline bool slc_data_bypass(void)
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{
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/*
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* If L1 data cache is disabled SL$ is bypassed and all load/store
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* requests are sent directly to main memory.
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*/
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return !dcache_enabled();
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}
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static inline bool ioc_exists(void)
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{
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if (is_isa_arcv2()) {
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@ -412,7 +421,13 @@ void invalidate_icache_all(void)
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{
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__ic_entire_invalidate();
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if (is_isa_arcv2())
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/*
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* If SL$ is bypassed for data it is used only for instructions,
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* so we need to invalidate it too.
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* TODO: HS 3.0 supports SLC disable so we need to check slc
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* enable/disable status here.
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*/
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if (is_isa_arcv2() && slc_data_bypass())
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__slc_entire_op(OP_INV);
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}
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@ -520,14 +535,15 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
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return;
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/*
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* ARCv1 -> call __dc_line_op
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* ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op
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* ARCv2 && IOC enabled -> nothing
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* ARCv1 -> call __dc_line_op
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* ARCv2 && L1 D$ disabled -> nothing
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* ARCv2 && L1 D$ enabled && IOC enabled -> nothing
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* ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
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*/
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if (!is_isa_arcv2() || !ioc_enabled())
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__dc_line_op(start, end - start, OP_INV);
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if (is_isa_arcv2() && !ioc_enabled())
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if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
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__slc_rgn_op(start, end - start, OP_INV);
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}
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@ -537,14 +553,15 @@ void flush_dcache_range(unsigned long start, unsigned long end)
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return;
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/*
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* ARCv1 -> call __dc_line_op
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* ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op
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* ARCv2 && IOC enabled -> nothing
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* ARCv1 -> call __dc_line_op
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* ARCv2 && L1 D$ disabled -> nothing
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* ARCv2 && L1 D$ enabled && IOC enabled -> nothing
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* ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
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*/
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if (!is_isa_arcv2() || !ioc_enabled())
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__dc_line_op(start, end - start, OP_FLUSH);
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if (is_isa_arcv2() && !ioc_enabled())
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if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
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__slc_rgn_op(start, end - start, OP_FLUSH);
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}
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@ -563,7 +580,7 @@ void flush_n_invalidate_dcache_all(void)
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{
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__dc_entire_op(OP_FLUSH_N_INV);
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if (is_isa_arcv2())
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if (is_isa_arcv2() && !slc_data_bypass())
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__slc_entire_op(OP_FLUSH_N_INV);
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}
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@ -571,6 +588,6 @@ void flush_dcache_all(void)
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{
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__dc_entire_op(OP_FLUSH);
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if (is_isa_arcv2())
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if (is_isa_arcv2() && !slc_data_bypass())
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__slc_entire_op(OP_FLUSH);
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}
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