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imx: ventana: add GW560x support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
8d1a6ff825
commit
94a1d6c602
@ -51,6 +51,20 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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/* 8-bit eMMC on SD2/NAND */
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static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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@ -365,6 +379,39 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
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/* RS232_EN# */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
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/* CAN_STBY */
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
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/* USB_HUBRST# */
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IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
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/* PANLEDG# */
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
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/* PANLEDR# */
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
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/* MX6_LOCLED# */
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
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/* IOEXP_PWREN# */
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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/* IOEXP_IRQ# */
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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/* DIOI2C_DIS# */
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
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/* VID_EN */
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
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/* PCI_RST# */
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IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
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/* RS485_EN */
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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/* USBH2_PEN (OTG) */
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
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/* 12V0_PWR_EN */
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IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
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/* USB_HUBRST# */
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IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
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@ -614,6 +661,33 @@ struct dio_cfg gw553x_dio[] = {
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},
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};
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struct dio_cfg gw560x_dio[] = {
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{
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{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
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IMX_GPIO_NR(1, 16),
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{ 0, 0 },
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0
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},
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{
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{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
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IMX_GPIO_NR(1, 19),
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{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
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2
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},
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{
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{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
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IMX_GPIO_NR(1, 17),
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{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
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3
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},
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{
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{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
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IMX_GPIO_NR(1, 20),
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{ 0, 0 },
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0
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},
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};
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struct dio_cfg gw5904_dio[] = {
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{
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{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
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@ -856,6 +930,27 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
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.mmc_cd = IMX_GPIO_NR(7, 0),
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},
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/* GW560x */
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{
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.gpio_pads = gw560x_gpio_pads,
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.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
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.dio_cfg = gw560x_dio,
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.dio_num = ARRAY_SIZE(gw560x_dio),
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 7),
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IMX_GPIO_NR(4, 15),
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},
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.pcie_rst = IMX_GPIO_NR(4, 31),
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.mezz_pwren = IMX_GPIO_NR(2, 19),
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.mezz_irq = IMX_GPIO_NR(2, 18),
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.rs232_en = GP_RS232_EN,
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.vidin_en = IMX_GPIO_NR(3, 31),
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.wdis = IMX_GPIO_NR(7, 12),
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.otgpwr_en = IMX_GPIO_NR(4, 15),
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.mmc_cd = IMX_GPIO_NR(7, 0),
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},
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/* GW5904 */
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{
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.gpio_pads = gw5904_gpio_pads,
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@ -988,6 +1083,10 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
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/* Anything else board specific */
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switch(board) {
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case GW560x:
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gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
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gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
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break;
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case GW5904:
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gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
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gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
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@ -1095,6 +1194,8 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
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void setup_pmic(void)
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{
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struct pmic *p;
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struct ventana_board_info ventana_info;
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int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
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u32 reg;
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i2c_set_bus_num(CONFIG_I2C_PMIC);
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@ -1127,23 +1228,27 @@ void setup_pmic(void)
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debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
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power_ltc3676_init(CONFIG_I2C_PMIC);
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p = pmic_get("LTC3676_PMIC");
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if (p && !pmic_probe(p)) {
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puts("PMIC: LTC3676\n");
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/*
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* set board-specific scalar for max CPU frequency
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* per CPU based on the LDO enabled Operating Ranges
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* defined in the respective IMX6DQ and IMX6SDL
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* datasheets. The voltage resulting from the R1/R2
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* feedback inputs on Ventana is 1308mV. Note that this
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* is a bit shy of the Vmin of 1350mV in the datasheet
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* for LDO enabled mode but is as high as we can go.
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*
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* We will rely on an OS kernel driver to properly
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* regulate these per CPU operating point and use LDO
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* bypass mode when using the higher frequency
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* operating points to compensate as LDO bypass mode
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* allows the rails be 125mV lower.
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*/
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if (!p || pmic_probe(p))
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return;
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puts("PMIC: LTC3676\n");
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/*
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* set board-specific scalar for max CPU frequency
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* per CPU based on the LDO enabled Operating Ranges
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* defined in the respective IMX6DQ and IMX6SDL
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* datasheets. The voltage resulting from the R1/R2
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* feedback inputs on Ventana is 1308mV. Note that this
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* is a bit shy of the Vmin of 1350mV in the datasheet
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* for LDO enabled mode but is as high as we can go.
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*/
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switch (board) {
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case GW560x:
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/* mask PGOOD during SW3 transition */
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pmic_reg_write(p, LTC3676_DVB3B,
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0x1f | LTC3676_PGOOD_MASK);
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/* set SW3 (VDD_ARM) */
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pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
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break;
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default:
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/* mask PGOOD during SW1 transition */
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pmic_reg_write(p, LTC3676_DVB1B,
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0x1f | LTC3676_PGOOD_MASK);
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@ -1160,7 +1265,7 @@ void setup_pmic(void)
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}
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
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static struct fsl_esdhc_cfg usdhc_cfg[2];
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int board_mmc_init(bd_t *bis)
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{
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@ -1175,17 +1280,32 @@ int board_mmc_init(bd_t *bis)
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case GW553x:
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/* usdhc3: 4bit microSD */
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SETUP_IOMUX_PADS(usdhc3_pads);
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usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg.max_bus_width = 4;
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return fsl_esdhc_initialize(bis, &usdhc_cfg);
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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case GW560x:
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/* usdhc2: 8-bit eMMC */
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SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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usdhc_cfg[0].max_bus_width = 8;
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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if (ret)
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return ret;
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/* usdhc3: 4-bit microSD */
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SETUP_IOMUX_PADS(usdhc3_pads);
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usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
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case GW5904:
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/* usdhc3: 8bit eMMC */
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SETUP_IOMUX_PADS(gw5904_emmc_pads);
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usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg.max_bus_width = 8;
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return fsl_esdhc_initialize(bis, &usdhc_cfg);
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 8;
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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default:
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/* doesn't have MMC */
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return -1;
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@ -1201,6 +1321,11 @@ int board_mmc_getcd(struct mmc *mmc)
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/* Card Detect */
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switch (board) {
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case GW560x:
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/* emmc is always present */
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if (cfg->esdhc_base == USDHC2_BASE_ADDR)
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return 1;
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break;
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case GW5904:
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/* emmc is always present */
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if (cfg->esdhc_base == USDHC3_BASE_ADDR)
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@ -93,6 +93,10 @@ read_eeprom(int bus, struct ventana_board_info *info)
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break;
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}
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break;
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case '6':
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if (info->model[4] == '0')
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type = GW560x;
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break;
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case '9':
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if (info->model[4] == '0' && info->model[5] == '4')
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type = GW5904;
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@ -137,6 +137,10 @@ int gsc_info(int verbose)
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break;
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case '5': /* GW55xx */
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break;
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case '6': /* GW560x */
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read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
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read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
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break;
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}
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return 0;
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}
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@ -694,6 +694,7 @@ int checkboard(void)
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static const struct boot_mode board_boot_modes[] = {
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/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
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{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
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{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
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{ NULL, 0 },
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};
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#endif
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@ -745,7 +746,8 @@ int misc_init_r(void)
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setenv("fdt_file1", fdt);
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if (board_type != GW551x &&
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board_type != GW552x &&
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board_type != GW553x)
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board_type != GW553x &&
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board_type != GW560x)
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str[4] = 'x';
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str[5] = 'x';
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str[6] = 0;
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@ -112,6 +112,7 @@ enum {
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GW551x,
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GW552x,
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GW553x,
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GW560x,
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GW5904,
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GW_UNKNOWN,
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GW_BADCRC,
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@ -100,7 +100,6 @@
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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/* Filesystem support */
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#define CONFIG_CMD_UBIFS
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