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ipu common: reset ipuv3 correctly

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This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
This commit is contained in:
Liu Ying 2012-10-06 04:16:04 +00:00 committed by Anatolij Gustschin
parent 1cc619be8b
commit 945d069fb5
1 changed files with 10 additions and 0 deletions
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10
drivers/video/ipu_common.c
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@ -94,6 +94,7 @@ struct ipu_ch_param {
temp1; \
})
#define IPU_SW_RST_TOUT_USEC (10000)
void clk_enable(struct clk *clk)
{
@ -398,11 +399,20 @@ void ipu_reset(void)
{
u32 *reg;
u32 value;
int timeout = IPU_SW_RST_TOUT_USEC;
reg = (u32 *)SRC_BASE_ADDR;
value = __raw_readl(reg);
value = value | SW_IPU_RST;
__raw_writel(value, reg);
while (__raw_readl(reg) & SW_IPU_RST) {
udelay(1);
if (!(timeout--)) {
printf("ipu software reset timeout\n");
break;
}
};
}
/*