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pinctrl: rmobile: Add Renesas RCar pincontrol driver
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796 SoCs. This driver uses the PFC pin tables from Linux, thus letting us share the occassional fixes to those tables. This driver also has a DT support, so the pinmux is configured from DT instead of the ad-hoc setup in board file. This driver is meant to replace the pinmux part of SH_GPIO_PFC driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Nobuhiro Iwamatsu
parent
0e9b18c376
commit
910df4d07e
@ -292,6 +292,7 @@ endif
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source "drivers/pinctrl/meson/Kconfig"
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source "drivers/pinctrl/nxp/Kconfig"
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source "drivers/pinctrl/renesas/Kconfig"
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source "drivers/pinctrl/uniphier/Kconfig"
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source "drivers/pinctrl/exynos/Kconfig"
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source "drivers/pinctrl/mvebu/Kconfig"
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@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
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obj-y += nxp/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_ATH79) += ath79/
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obj-$(CONFIG_ARCH_RMOBILE) += renesas/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
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31
drivers/pinctrl/renesas/Kconfig
Normal file
31
drivers/pinctrl/renesas/Kconfig
Normal file
@ -0,0 +1,31 @@
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if ARCH_RMOBILE
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config PINCTRL_PFC
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bool "Renesas pin control drivers"
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depends on DM && ARCH_RMOBILE
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help
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Enable support for clock present on Renesas RCar SoCs.
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config PINCTRL_PFC_R8A7795
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bool "Renesas RCar Gen3 R8A7795 pin control driver"
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def_bool y if R8A7795
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depends on PINCTRL_PFC
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help
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Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
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The driver is controlled by a device tree node which contains both
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the GPIO definitions and pin control functions for each available
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multiplex function.
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config PINCTRL_PFC_R8A7796
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bool "Renesas RCar Gen3 R8A7796 pin control driver"
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def_bool y if R8A7796
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depends on PINCTRL_PFC
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help
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Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
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The driver is controlled by a device tree node which contains both
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the GPIO definitions and pin control functions for each available
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multiplex function.
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endif
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3
drivers/pinctrl/renesas/Makefile
Normal file
3
drivers/pinctrl/renesas/Makefile
Normal file
@ -0,0 +1,3 @@
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obj-$(CONFIG_PINCTRL_PFC) += pfc.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
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4898
drivers/pinctrl/renesas/pfc-r8a7795.c
Normal file
4898
drivers/pinctrl/renesas/pfc-r8a7795.c
Normal file
File diff suppressed because it is too large
Load Diff
5728
drivers/pinctrl/renesas/pfc-r8a7796.c
Normal file
5728
drivers/pinctrl/renesas/pfc-r8a7796.c
Normal file
File diff suppressed because it is too large
Load Diff
565
drivers/pinctrl/renesas/pfc.c
Normal file
565
drivers/pinctrl/renesas/pfc.c
Normal file
@ -0,0 +1,565 @@
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/*
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* Pin Control driver for SuperH Pin Function Controller.
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*
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* Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
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*
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2009 - 2012 Paul Mundt
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* Copyright (C) 2017 Marek Vasut
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#define DRV_NAME "sh-pfc"
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <dm/pinctrl.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "sh_pfc.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum sh_pfc_model {
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SH_PFC_R8A7795 = 0,
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SH_PFC_R8A7796,
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};
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struct sh_pfc_pin_config {
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u32 type;
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};
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struct sh_pfc_pinctrl {
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struct sh_pfc *pfc;
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struct sh_pfc_pin_config *configs;
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const char *func_prop_name;
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const char *groups_prop_name;
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const char *pins_prop_name;
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};
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struct sh_pfc_pin_range {
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u16 start;
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u16 end;
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};
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struct sh_pfc_pinctrl_priv {
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struct sh_pfc pfc;
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struct sh_pfc_pinctrl pmx;
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};
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
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{
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unsigned int offset;
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unsigned int i;
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for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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if (pin <= range->end)
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return pin >= range->start
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? offset + pin - range->start : -1;
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offset += range->end - range->start + 1;
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}
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return -EINVAL;
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}
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static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
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{
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if (enum_id < r->begin)
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return 0;
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if (enum_id > r->end)
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return 0;
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return 1;
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}
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u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
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{
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switch (reg_width) {
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case 8:
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return readb(mapped_reg);
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case 16:
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return readw(mapped_reg);
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case 32:
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return readl(mapped_reg);
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}
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BUG();
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return 0;
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}
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
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u32 data)
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{
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switch (reg_width) {
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case 8:
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writeb(data, mapped_reg);
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return;
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case 16:
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writew(data, mapped_reg);
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return;
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case 32:
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writel(data, mapped_reg);
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return;
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}
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BUG();
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}
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u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
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{
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return sh_pfc_read_raw_reg(pfc->regs + reg, width);
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}
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void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
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{
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
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sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int in_pos,
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void __iomem **mapped_regp, u32 *maskp,
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unsigned int *posp)
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{
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unsigned int k;
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*mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
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if (crp->field_width) {
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*maskp = (1 << crp->field_width) - 1;
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*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
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} else {
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*maskp = (1 << crp->var_field_width[in_pos]) - 1;
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*posp = crp->reg_width;
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for (k = 0; k <= in_pos; k++)
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*posp -= crp->var_field_width[k];
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}
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}
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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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const struct pinmux_cfg_reg *crp,
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unsigned int field, u32 value)
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{
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void __iomem *mapped_reg;
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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unsigned int pos;
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u32 mask, data;
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sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
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"r_width = %u, f_width = %u\n",
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crp->reg, value, field, crp->reg_width, crp->field_width);
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mask = ~(mask << pos);
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value = value << pos;
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data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
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data &= mask;
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data |= value;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
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const struct pinmux_cfg_reg **crp,
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unsigned int *fieldp, u32 *valuep)
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{
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unsigned int k = 0;
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while (1) {
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const struct pinmux_cfg_reg *config_reg =
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pfc->info->cfg_regs + k;
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unsigned int r_width = config_reg->reg_width;
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unsigned int f_width = config_reg->field_width;
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unsigned int curr_width;
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unsigned int bit_pos;
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unsigned int pos = 0;
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unsigned int m = 0;
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if (!r_width)
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break;
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for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
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u32 ncomb;
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u32 n;
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if (f_width)
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curr_width = f_width;
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else
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curr_width = config_reg->var_field_width[m];
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ncomb = 1 << curr_width;
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for (n = 0; n < ncomb; n++) {
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if (config_reg->enum_ids[pos + n] == enum_id) {
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*crp = config_reg;
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*fieldp = m;
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*valuep = n;
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return 0;
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}
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}
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pos += ncomb;
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m++;
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}
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k++;
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}
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return -EINVAL;
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}
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static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
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u16 *enum_idp)
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{
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const u16 *data = pfc->info->pinmux_data;
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unsigned int k;
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if (pos) {
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*enum_idp = data[pos + 1];
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return pos + 1;
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}
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for (k = 0; k < pfc->info->pinmux_data_size; k++) {
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if (data[k] == mark) {
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*enum_idp = data[k + 1];
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return k + 1;
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}
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}
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dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
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mark);
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return -EINVAL;
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}
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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{
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const struct pinmux_range *range;
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int pos = 0;
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switch (pinmux_type) {
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case PINMUX_TYPE_GPIO:
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case PINMUX_TYPE_FUNCTION:
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range = NULL;
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break;
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case PINMUX_TYPE_OUTPUT:
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range = &pfc->info->output;
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break;
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case PINMUX_TYPE_INPUT:
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range = &pfc->info->input;
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break;
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default:
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return -EINVAL;
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}
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/* Iterate over all the configuration fields we need to update. */
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while (1) {
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const struct pinmux_cfg_reg *cr;
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unsigned int field;
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u16 enum_id;
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u32 value;
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int in_range;
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int ret;
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pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
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if (pos < 0)
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return pos;
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if (!enum_id)
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break;
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/* Check if the configuration field selects a function. If it
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* doesn't, skip the field if it's not applicable to the
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* requested pinmux type.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
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if (!in_range) {
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if (pinmux_type == PINMUX_TYPE_FUNCTION) {
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/* Functions are allowed to modify all
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* fields.
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*/
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in_range = 1;
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} else if (pinmux_type != PINMUX_TYPE_GPIO) {
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/* Input/output types can only modify fields
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* that correspond to their respective ranges.
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*/
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in_range = sh_pfc_enum_in_range(enum_id, range);
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/*
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* special case pass through for fixed
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* input-only or output-only pins without
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* function enum register association.
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*/
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if (in_range && enum_id == range->force)
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continue;
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}
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/* GPIOs are only allowed to modify function fields. */
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}
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if (!in_range)
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continue;
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ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
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if (ret < 0)
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return ret;
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sh_pfc_write_config_reg(pfc, cr, field, value);
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}
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return 0;
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}
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const struct sh_pfc_bias_info *
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sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
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unsigned int num, unsigned int pin)
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{
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unsigned int i;
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for (i = 0; i < num; i++)
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if (info[i].pin == pin)
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return &info[i];
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printf("Pin %u is not in bias info list\n", pin);
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return NULL;
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}
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static int sh_pfc_init_ranges(struct sh_pfc *pfc)
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{
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struct sh_pfc_pin_range *range;
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unsigned int nr_ranges;
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unsigned int i;
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if (pfc->info->pins[0].pin == (u16)-1) {
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/* Pin number -1 denotes that the SoC doesn't report pin numbers
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* in its pin arrays yet. Consider the pin numbers range as
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* continuous and allocate a single range.
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*/
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pfc->nr_ranges = 1;
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pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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pfc->ranges->start = 0;
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pfc->ranges->end = pfc->info->nr_pins - 1;
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pfc->nr_gpio_pins = pfc->info->nr_pins;
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return 0;
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}
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/* Count, allocate and fill the ranges. The PFC SoC data pins array must
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* be sorted by pin numbers, and pins without a GPIO port must come
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* last.
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*/
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for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
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nr_ranges++;
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}
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pfc->nr_ranges = nr_ranges;
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pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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range = pfc->ranges;
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range->start = pfc->info->pins[0].pin;
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for (i = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
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continue;
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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range++;
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range->start = pfc->info->pins[i].pin;
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}
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range->end = pfc->info->pins[i-1].pin;
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if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
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pfc->nr_gpio_pins = range->end + 1;
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return 0;
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}
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static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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|
||||
return priv->pfc.info->nr_pins;
|
||||
}
|
||||
|
||||
static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pfc.info->pins[selector].name;
|
||||
}
|
||||
|
||||
static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pfc.info->nr_groups;
|
||||
}
|
||||
|
||||
static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pfc.info->groups[selector].name;
|
||||
}
|
||||
|
||||
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pfc.info->nr_functions;
|
||||
}
|
||||
|
||||
static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pfc.info->functions[selector].name;
|
||||
}
|
||||
|
||||
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
|
||||
unsigned func_selector)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
struct sh_pfc_pinctrl *pmx = &priv->pmx;
|
||||
struct sh_pfc *pfc = &priv->pfc;
|
||||
const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
|
||||
unsigned int i;
|
||||
int ret = 0;
|
||||
|
||||
for (i = 0; i < grp->nr_pins; ++i) {
|
||||
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
|
||||
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
|
||||
|
||||
if (cfg->type != PINMUX_TYPE_NONE) {
|
||||
ret = -EBUSY;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < grp->nr_pins; ++i) {
|
||||
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct pinctrl_ops sh_pfc_pinctrl_ops = {
|
||||
.get_pins_count = sh_pfc_pinctrl_get_pins_count,
|
||||
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
|
||||
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
|
||||
.get_group_name = sh_pfc_pinctrl_get_group_name,
|
||||
.get_functions_count = sh_pfc_pinctrl_get_functions_count,
|
||||
.get_function_name = sh_pfc_pinctrl_get_function_name,
|
||||
|
||||
.pinmux_group_set = sh_pfc_pinctrl_group_set,
|
||||
.set_state = pinctrl_generic_set_state,
|
||||
};
|
||||
|
||||
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* Allocate and initialize the pins and configs arrays. */
|
||||
pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
|
||||
GFP_KERNEL);
|
||||
if (unlikely(!pmx->configs))
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < pfc->info->nr_pins; ++i) {
|
||||
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
|
||||
cfg->type = PINMUX_TYPE_NONE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
enum sh_pfc_model model = dev_get_driver_data(dev);
|
||||
fdt_addr_t base;
|
||||
|
||||
base = devfdt_get_addr(dev);
|
||||
if (base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
|
||||
if (!priv->pfc.regs)
|
||||
return -ENOMEM;
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
if (model == SH_PFC_R8A7795)
|
||||
priv->pfc.info = &r8a7795_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
||||
if (model == SH_PFC_R8A7796)
|
||||
priv->pfc.info = &r8a7796_pinmux_info;
|
||||
#endif
|
||||
|
||||
priv->pmx.pfc = &priv->pfc;
|
||||
sh_pfc_init_ranges(&priv->pfc);
|
||||
sh_pfc_map_pins(&priv->pfc, &priv->pmx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7795",
|
||||
.data = SH_PFC_R8A7795,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7796",
|
||||
.data = SH_PFC_R8A7796,
|
||||
},
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_sh_pfc) = {
|
||||
.name = "sh_pfc_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = sh_pfc_pinctrl_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
|
||||
.ops = &sh_pfc_pinctrl_ops,
|
||||
.probe = sh_pfc_pinctrl_probe,
|
||||
};
|
||||
575
drivers/pinctrl/renesas/sh_pfc.h
Normal file
575
drivers/pinctrl/renesas/sh_pfc.h
Normal file
@ -0,0 +1,575 @@
|
||||
/*
|
||||
* SuperH Pin Function Controller Support
|
||||
*
|
||||
* Copyright (c) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SH_PFC_H
|
||||
#define __SH_PFC_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
enum {
|
||||
PINMUX_TYPE_NONE,
|
||||
PINMUX_TYPE_FUNCTION,
|
||||
PINMUX_TYPE_GPIO,
|
||||
PINMUX_TYPE_OUTPUT,
|
||||
PINMUX_TYPE_INPUT,
|
||||
};
|
||||
|
||||
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
|
||||
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
|
||||
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
|
||||
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
|
||||
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
|
||||
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
|
||||
|
||||
struct sh_pfc_pin {
|
||||
u16 pin;
|
||||
u16 enum_id;
|
||||
const char *name;
|
||||
unsigned int configs;
|
||||
};
|
||||
|
||||
#define SH_PFC_PIN_GROUP(n) \
|
||||
{ \
|
||||
.name = #n, \
|
||||
.pins = n##_pins, \
|
||||
.mux = n##_mux, \
|
||||
.nr_pins = ARRAY_SIZE(n##_pins), \
|
||||
}
|
||||
|
||||
struct sh_pfc_pin_group {
|
||||
const char *name;
|
||||
const unsigned int *pins;
|
||||
const unsigned int *mux;
|
||||
unsigned int nr_pins;
|
||||
};
|
||||
|
||||
/*
|
||||
* Using union vin_data saves memory occupied by the VIN data pins.
|
||||
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
|
||||
* in this case.
|
||||
*/
|
||||
#define VIN_DATA_PIN_GROUP(n, s) \
|
||||
{ \
|
||||
.name = #n#s, \
|
||||
.pins = n##_pins.data##s, \
|
||||
.mux = n##_mux.data##s, \
|
||||
.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
|
||||
}
|
||||
|
||||
union vin_data {
|
||||
unsigned int data24[24];
|
||||
unsigned int data20[20];
|
||||
unsigned int data16[16];
|
||||
unsigned int data12[12];
|
||||
unsigned int data10[10];
|
||||
unsigned int data8[8];
|
||||
unsigned int data4[4];
|
||||
};
|
||||
|
||||
#define SH_PFC_FUNCTION(n) \
|
||||
{ \
|
||||
.name = #n, \
|
||||
.groups = n##_groups, \
|
||||
.nr_groups = ARRAY_SIZE(n##_groups), \
|
||||
}
|
||||
|
||||
struct sh_pfc_function {
|
||||
const char *name;
|
||||
const char * const *groups;
|
||||
unsigned int nr_groups;
|
||||
};
|
||||
|
||||
struct pinmux_func {
|
||||
u16 enum_id;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
struct pinmux_cfg_reg {
|
||||
u32 reg;
|
||||
u8 reg_width, field_width;
|
||||
const u16 *enum_ids;
|
||||
const u8 *var_field_width;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe a config register consisting of several fields of the same width
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* - f_width: Width of the fixed-width register fields (in bits)
|
||||
* This macro must be followed by initialization data: For each register field
|
||||
* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
|
||||
* one for each possible combination of the register field bit values.
|
||||
*/
|
||||
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
|
||||
.reg = r, .reg_width = r_width, .field_width = f_width, \
|
||||
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
|
||||
|
||||
/*
|
||||
* Describe a config register consisting of several fields of different widths
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
|
||||
* From left to right (i.e. MSB to LSB)
|
||||
* This macro must be followed by initialization data: For each register field
|
||||
* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
|
||||
* one for each possible combination of the register field bit values.
|
||||
*/
|
||||
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.var_field_width = (const u8 [r_width]) \
|
||||
{ var_fw0, var_fwn, 0 }, \
|
||||
.enum_ids = (const u16 [])
|
||||
|
||||
struct pinmux_drive_reg_field {
|
||||
u16 pin;
|
||||
u8 offset;
|
||||
u8 size;
|
||||
};
|
||||
|
||||
struct pinmux_drive_reg {
|
||||
u32 reg;
|
||||
const struct pinmux_drive_reg_field fields[8];
|
||||
};
|
||||
|
||||
#define PINMUX_DRIVE_REG(name, r) \
|
||||
.reg = r, \
|
||||
.fields =
|
||||
|
||||
struct pinmux_data_reg {
|
||||
u32 reg;
|
||||
u8 reg_width;
|
||||
const u16 *enum_ids;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe a data register
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* This macro must be followed by initialization data: For each register bit
|
||||
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
|
||||
*/
|
||||
#define PINMUX_DATA_REG(name, r, r_width) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.enum_ids = (const u16 [r_width]) \
|
||||
|
||||
struct pinmux_irq {
|
||||
const short *gpios;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe the mapping from GPIOs to a single IRQ
|
||||
* - ids...: List of GPIOs that are mapped to the same IRQ
|
||||
*/
|
||||
#define PINMUX_IRQ(ids...) \
|
||||
{ .gpios = (const short []) { ids, -1 } }
|
||||
|
||||
struct pinmux_range {
|
||||
u16 begin;
|
||||
u16 end;
|
||||
u16 force;
|
||||
};
|
||||
|
||||
struct sh_pfc_bias_info {
|
||||
u16 pin;
|
||||
u16 reg : 11;
|
||||
u16 bit : 5;
|
||||
};
|
||||
|
||||
struct sh_pfc_pin_range;
|
||||
|
||||
struct sh_pfc {
|
||||
struct device *dev;
|
||||
const struct sh_pfc_soc_info *info;
|
||||
|
||||
void *regs;
|
||||
|
||||
struct sh_pfc_pin_range *ranges;
|
||||
unsigned int nr_ranges;
|
||||
|
||||
unsigned int nr_gpio_pins;
|
||||
|
||||
struct sh_pfc_chip *gpio;
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_operations {
|
||||
int (*init)(struct sh_pfc *pfc);
|
||||
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
|
||||
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
|
||||
};
|
||||
|
||||
struct sh_pfc_soc_info {
|
||||
const char *name;
|
||||
const struct sh_pfc_soc_operations *ops;
|
||||
|
||||
struct pinmux_range input;
|
||||
struct pinmux_range output;
|
||||
struct pinmux_range function;
|
||||
|
||||
const struct sh_pfc_pin *pins;
|
||||
unsigned int nr_pins;
|
||||
const struct sh_pfc_pin_group *groups;
|
||||
unsigned int nr_groups;
|
||||
const struct sh_pfc_function *functions;
|
||||
unsigned int nr_functions;
|
||||
|
||||
const struct pinmux_cfg_reg *cfg_regs;
|
||||
const struct pinmux_drive_reg *drive_regs;
|
||||
const struct pinmux_data_reg *data_regs;
|
||||
|
||||
const u16 *pinmux_data;
|
||||
unsigned int pinmux_data_size;
|
||||
|
||||
const struct pinmux_irq *gpio_irq;
|
||||
unsigned int gpio_irq_size;
|
||||
|
||||
u32 unlock_reg;
|
||||
};
|
||||
|
||||
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
|
||||
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
|
||||
const struct sh_pfc_bias_info *
|
||||
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
|
||||
unsigned int num, unsigned int pin);
|
||||
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Helper macros to create pin and port lists
|
||||
*/
|
||||
|
||||
/*
|
||||
* sh_pfc_soc_info pinmux_data array macros
|
||||
*/
|
||||
|
||||
/*
|
||||
* Describe generic pinmux data
|
||||
* - data_or_mark: *_DATA or *_MARK enum ID
|
||||
* - ids...: List of enum IDs to associate with data_or_mark
|
||||
*/
|
||||
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration without GPIO function that needs
|
||||
* configuration in a Peripheral Function Select Register (IPSR)
|
||||
* - ipsr: IPSR field (unused, for documentation purposes only)
|
||||
* - fn: Function name, referring to a field in the IPSR
|
||||
*/
|
||||
#define PINMUX_IPSR_NOGP(ipsr, fn) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function that needs configuration
|
||||
* in both a Peripheral Function Select Register (IPSR) and in a
|
||||
* GPIO/Peripheral Function Select Register (GPSR)
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
*/
|
||||
#define PINMUX_IPSR_GPSR(ipsr, fn) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration without GPIO function that needs
|
||||
* configuration in a Peripheral Function Select Register (IPSR), and where the
|
||||
* pinmux function has a representation in a Module Select Register (MOD_SEL).
|
||||
* - ipsr: IPSR field (unused, for documentation purposes only)
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function where the pinmux function
|
||||
* has no representation in a Peripheral Function Select Register (IPSR), but
|
||||
* instead solely depends on a group selection.
|
||||
* - gpsr: GPSR field
|
||||
* - fn: Function name, also referring to the GPSR field
|
||||
* - gsel: Group selector
|
||||
*/
|
||||
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function that needs configuration
|
||||
* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
|
||||
* Function Select Register (GPSR), and where the pinmux function has a
|
||||
* representation in a Module Select Register (MOD_SEL).
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration for a single-function pin with GPIO
|
||||
* capability.
|
||||
* - fn: Function name
|
||||
*/
|
||||
#define PINMUX_SINGLE(fn) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn)
|
||||
|
||||
/*
|
||||
* GP port style (32 ports banks)
|
||||
*/
|
||||
|
||||
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
|
||||
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
||||
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
||||
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
||||
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
|
||||
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
|
||||
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
||||
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
|
||||
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
|
||||
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_15(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
|
||||
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
|
||||
#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_17(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
|
||||
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
|
||||
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
|
||||
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
|
||||
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
|
||||
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
||||
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
||||
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
|
||||
#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_29(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
||||
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
||||
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_32_REV(bank, fn, sfx) \
|
||||
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
|
||||
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
|
||||
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
|
||||
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
|
||||
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
|
||||
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
|
||||
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
|
||||
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
|
||||
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
|
||||
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
|
||||
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
|
||||
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
|
||||
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
|
||||
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
|
||||
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
|
||||
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
|
||||
|
||||
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
|
||||
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
|
||||
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
|
||||
|
||||
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
|
||||
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
|
||||
{ \
|
||||
.pin = (bank * 32) + _pin, \
|
||||
.name = __stringify(_name), \
|
||||
.enum_id = _name##_DATA, \
|
||||
.configs = cfg, \
|
||||
}
|
||||
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
|
||||
|
||||
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
|
||||
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
|
||||
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
|
||||
|
||||
/*
|
||||
* PORT style (linear pin space)
|
||||
*/
|
||||
|
||||
#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
|
||||
|
||||
#define PORT_10(pn, fn, pfx, sfx) \
|
||||
PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
|
||||
PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
|
||||
PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
|
||||
PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
|
||||
PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
|
||||
|
||||
#define PORT_90(pn, fn, pfx, sfx) \
|
||||
PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
|
||||
PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
|
||||
PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
|
||||
PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
|
||||
PORT_10(pn+90, fn, pfx##9, sfx)
|
||||
|
||||
/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
|
||||
#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
|
||||
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
|
||||
|
||||
/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
|
||||
#define PINMUX_GPIO(_pin) \
|
||||
[GPIO_##_pin] = { \
|
||||
.pin = (u16)-1, \
|
||||
.name = __stringify(GPIO_##_pin), \
|
||||
.enum_id = _pin##_DATA, \
|
||||
}
|
||||
|
||||
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
|
||||
#define SH_PFC_PIN_CFG(_pin, cfgs) \
|
||||
{ \
|
||||
.pin = _pin, \
|
||||
.name = __stringify(PORT##_pin), \
|
||||
.enum_id = PORT##_pin##_DATA, \
|
||||
.configs = cfgs, \
|
||||
}
|
||||
|
||||
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
|
||||
#define SH_PFC_PIN_NAMED(row, col, _name) \
|
||||
{ \
|
||||
.pin = PIN_NUMBER(row, col), \
|
||||
.name = __stringify(PIN_##_name), \
|
||||
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
|
||||
}
|
||||
|
||||
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
|
||||
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
|
||||
{ \
|
||||
.pin = PIN_NUMBER(row, col), \
|
||||
.name = __stringify(PIN_##_name), \
|
||||
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
|
||||
}
|
||||
|
||||
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
|
||||
* PORT_name_OUT, PORT_name_IN marks
|
||||
*/
|
||||
#define _PORT_DATA(pn, pfx, sfx) \
|
||||
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
|
||||
PORT##pfx##_OUT, PORT##pfx##_IN)
|
||||
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
|
||||
|
||||
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
|
||||
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
|
||||
[gpio - (base)] = { \
|
||||
.name = __stringify(gpio), \
|
||||
.enum_id = data_or_mark, \
|
||||
}
|
||||
#define GPIO_FN(str) \
|
||||
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
|
||||
|
||||
/*
|
||||
* PORTnCR helper macro for SH-Mobile/R-Mobile
|
||||
*/
|
||||
#define PORTCR(nr, reg) \
|
||||
{ \
|
||||
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
|
||||
/* PULMD[1:0], handled by .set_bias() */ \
|
||||
0, 0, 0, 0, \
|
||||
/* IE and OE */ \
|
||||
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
|
||||
/* SEC, not supported */ \
|
||||
0, 0, \
|
||||
/* PTMD[2:0] */ \
|
||||
PORT##nr##_FN0, PORT##nr##_FN1, \
|
||||
PORT##nr##_FN2, PORT##nr##_FN3, \
|
||||
PORT##nr##_FN4, PORT##nr##_FN5, \
|
||||
PORT##nr##_FN6, PORT##nr##_FN7 \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* GPIO number helper macro for R-Car
|
||||
*/
|
||||
#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
|
||||
|
||||
#endif /* __SH_PFC_H */
|
||||
Loading…
Reference in New Issue
Block a user