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This commit is contained in:
Tom Rini 2021-04-05 11:29:57 -04:00
commit 90eba245a6
659 changed files with 22454 additions and 4551 deletions
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5
.azure-pipelines.yml
View File

@ -148,7 +148,7 @@ jobs:
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
@ -187,6 +187,9 @@ jobs:
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
sandbox_noinst:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
sandbox_flattree:
TEST_PY_BD: "sandbox_flattree"
evb_ast2500:

10
.gitlab-ci.yml
View File

@ -168,7 +168,8 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
--board sandbox_spl;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
@ -204,6 +205,13 @@ sandbox_spl test.py:
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
<<: *buildman_and_testpy_dfn
sandbox_noinst_test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
<<: *buildman_and_testpy_dfn
evb-ast2500 test.py:
tags: [ 'all' ]
variables:

22
Makefile
View File

@ -17,9 +17,13 @@ NAME =
# o Look for make include files relative to root of kernel src
MAKEFLAGS += -rR --include-dir=$(CURDIR)
# Determine host architecture
# Determine target architecture for the sandbox
include include/host_arch.h
MK_ARCH="${shell uname -m}"
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\s*\([^\/]*\/\)*\([^-]*\)-\S*/\2/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_X86_64)
@ -27,7 +31,7 @@ else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
export HOST_ARCH=$(HOST_ARCH_X86)
else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
export HOST_ARCH=$(HOST_ARCH_AARCH64)
else ifeq ("armv7l", $(MK_ARCH))
else ifneq (,$(findstring $(MK_ARCH), "arm" "armv7" "armv7l"))
export HOST_ARCH=$(HOST_ARCH_ARM)
else ifeq ("riscv32", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV32)
@ -1265,7 +1269,13 @@ u-boot.ldr: u-boot
# binman
# ---------------------------------------------------------------------------
# Use 'make BINMAN_DEBUG=1' to enable debugging
# Use 'make BINMAN_VERBOSE=3' to set vebosity level
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
# Tell binman whether we have a devicetree for SPL and TPL
have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL))
have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL))
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
@ -1276,6 +1286,9 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-a atf-bl31-path=${BL31} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@ -1666,6 +1679,9 @@ u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
ifeq ($(CONFIG_SPL),y)
spl/u-boot-spl-mtk.bin: spl/u-boot-spl
u-boot-mtk.bin: u-boot-with-spl.bin
$(call if_changed,copy)
else
MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \

2
arch/Kconfig
View File

@ -142,6 +142,8 @@ config SANDBOX
imply AVB_VERIFY
imply LIBAVB
imply CMD_AVB
imply SCP03
imply CMD_SCP03
imply UDP_FUNCTION_FASTBOOT
imply VIRTIO_MMIO
imply VIRTIO_PCI

4
arch/arc/lib/reset.c
View File

@ -7,7 +7,7 @@
#include <common.h>
#include <cpu_func.h>
__weak void reset_cpu(ulong addr)
__weak void reset_cpu(void)
{
/* Stop debug session here */
__builtin_arc_brk();
@ -17,7 +17,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("Resetting the board...\n");
reset_cpu(0);
reset_cpu();
return 0;
}

2
arch/arm/cpu/arm920t/ep93xx/cpu.c
View File

@ -14,7 +14,7 @@
#include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
extern void reset_cpu(ulong addr)
extern void reset_cpu(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;

2
arch/arm/cpu/arm920t/imx/timer.c
View File

@ -81,7 +81,7 @@ ulong get_tbclk(void)
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;

2
arch/arm/cpu/arm926ejs/armada100/timer.c
View File

@ -142,7 +142,7 @@ int timer_init(void)
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu(unsigned long ignored)
void reset_cpu(void)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;

2
arch/arm/cpu/arm926ejs/mx25/reset.c
View File

@ -23,7 +23,7 @@
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */

2
arch/arm/cpu/arm926ejs/mx27/reset.c
View File

@ -23,7 +23,7 @@
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */

4
arch/arm/cpu/arm926ejs/mxs/mxs.c
View File

@ -32,9 +32,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
__weak void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(void) __attribute__((noreturn));
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;

2
arch/arm/cpu/arm926ejs/spear/reset.c
View File

@ -11,7 +11,7 @@
#include <asm/arch/spr_syscntl.h>
#include <linux/delay.h>
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
struct syscntl_regs *syscntl_regs_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;

2
arch/arm/cpu/arm946es/cpu.c
View File

@ -56,7 +56,7 @@ static void cache_flush (void)
#ifndef CONFIG_ARCH_INTEGRATOR
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
__attribute__((noreturn)) void reset_cpu(void)
{
writew(0x0, 0xfffece10);
writew(0x8, 0xfffece10);

2
arch/arm/cpu/armv7/bcm281xx/reset.c
View File

@ -13,7 +13,7 @@
#define CLKS_SHIFT 20 /* Clock period shift */
#define LD_SHIFT 0 /* Reload value shift */
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
/*
* Set WD enable, RST enable,

2
arch/arm/cpu/armv7/bcmcygnus/reset.c
View File

@ -10,7 +10,7 @@
#define CRMU_MAIL_BOX1 0x03024028
#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
/* Send soft reset command via Mailbox. */
writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);

2
arch/arm/cpu/armv7/bcmnsp/reset.c
View File

@ -9,7 +9,7 @@
#define CRU_RESET_OFFSET 0x1803F184
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
/* Reset the cpu by setting software reset request bit */
writel(0x1, CRU_RESET_OFFSET);

3
arch/arm/cpu/armv7/cache_v7.c
View File

@ -176,9 +176,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
}
void arm_init_domains(void)
{
}
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)

2
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -375,7 +375,7 @@ void smp_kick_all_cpus(void)
}
#endif
void reset_cpu(ulong addr)
void reset_cpu(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

2
arch/arm/cpu/armv7/s5p4418/cpu.c
View File

@ -88,7 +88,7 @@ int print_cpuinfo(void)
}
#endif
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
const u32 sw_rst_enb_bitpos = 3;

2
arch/arm/cpu/armv7/stv0991/reset.c
View File

@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/arch/stv0991_wdru.h>
#include <linux/delay.h>
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
puts("System is going to reboot ...\n");
/*

2
arch/arm/cpu/armv7m/cpu.c
View File

@ -47,7 +47,7 @@ int cleanup_before_linux(void)
/*
* Perform the low-level reset.
*/
void reset_cpu(ulong addr)
void reset_cpu(void)
{
/*
* Perform reset but keep priority group unchanged.

4
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1231,7 +1231,7 @@ int timer_init(void)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(ulong addr)
void __efi_runtime reset_cpu(void)
{
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
/* clear the RST_REQ_MSK and SW_RST_REQ */
@ -1260,7 +1260,7 @@ void __efi_runtime EFIAPI efi_reset_system(
case EFI_RESET_COLD:
case EFI_RESET_WARM:
case EFI_RESET_PLATFORM_SPECIFIC:
reset_cpu(0);
reset_cpu();
break;
case EFI_RESET_SHUTDOWN:
/* Nothing we can do */

2
arch/arm/cpu/armv8/s32v234/generic.c
View File

@ -319,7 +319,7 @@ static char *get_reset_cause(void)
#define SRC_SCR_SW_RST (1<<12)
void reset_cpu(ulong addr)
void reset_cpu(void)
{
printf("Feature not supported.\n");
};

4
arch/arm/cpu/pxa/pxa2xx.c
View File

@ -267,9 +267,9 @@ void i2c_clk_enable(void)
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
uint32_t tmp;

2
arch/arm/cpu/sa1100/cpu.c
View File

@ -55,7 +55,7 @@ static void cache_flush (void)
#define RSRR 0x00
#define RCSR 0x04
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
__attribute__((noreturn)) void reset_cpu(void)
{
/* repeat endlessly */
while (1) {

5
arch/arm/dts/Makefile
View File

@ -822,6 +822,10 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774b1-beacon-rzg2n-kit.dtb \
r8a774e1-beacon-rzg2h-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a774c0-ek874-u-boot.dtb \
r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
@ -1009,6 +1013,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt8183-pumpkin.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb

8
arch/arm/dts/bitmain-antminer-s9.dts
View File

@ -50,6 +50,14 @@
ps-clk-frequency = <33333333>;
};
&nand0 {
status = "okay";
};
&smcc {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

64
arch/arm/dts/cat875.dtsi Normal file
View File

@ -0,0 +1,64 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/ {
model = "Silicon Linux sub board for CAT874 (CAT875)";
aliases {
ethernet0 = &avb;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&pciec0 {
status = "okay";
};
&pfc {
avb_pins: avb {
mux {
groups = "avb_mii";
function = "avb";
};
};
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
};

18
arch/arm/dts/mt7629-rfb-u-boot.dtsi
View File

@ -5,24 +5,6 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#include <config.h>
/ {
binman {
filename = "u-boot-mtk.bin";
pad-byte = <0xff>;
#ifdef CONFIG_SPL
blob {
filename = "spl/u-boot-spl-mtk.bin";
size = <CONFIG_SPL_PAD_TO>;
};
u-boot-img {
};
#endif
};
};
&infracfg {
u-boot,dm-pre-reloc;
};

10
arch/arm/dts/mt7629-rfb.dts
View File

@ -36,6 +36,16 @@
};
&pinctrl {
state_default: pinmux_conf {
u-boot,dm-pre-reloc;
mux {
function = "jtag";
groups = "ephy_leds_jtag";
u-boot,dm-pre-reloc;
};
};
snfi_pins: snfi-pins {
mux {
function = "flash";

6
arch/arm/dts/mt7629.dtsi
View File

@ -152,6 +152,12 @@
compatible = "mediatek,mt7629-pinctrl";
reg = <0x10217000 0x8000>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux_conf {
};
gpio: gpio-controller {
gpio-controller;
#gpio-cells = <2>;

99
arch/arm/dts/mt8183-pumpkin.dts Normal file
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 BayLibre SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
/dts-v1/;
#include <config.h>
#include "mt8183.dtsi"
/ {
model = "MediaTek MT8183 pumpkin board";
compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x30000>;
};
/* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
* | | TA_RAM 8MiB |
* + TZDRAM +--------------+ 0x4340_0000
* | | TEE_RAM 2MiB |
* +-----------------------+ 0x4320_0000
*/
optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
};
chosen {
stdout-path = &uart0;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&watchdog {
status = "okay";
};
&uart0 {
status = "okay";
};
&mmc0 {
bus-width = <4>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
status = "okay";
};
&usb {
status = "okay";
};
&ssusb {
mediatek,force-vbus;
maximum-speed = "high-speed";
dr_mode = "peripheral";
status = "okay";
};

274
arch/arm/dts/mt8183.dtsi Normal file
View File

@ -0,0 +1,274 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Copyright (C) 2021 BayLibre, SAS
* Author: Ben Ho <ben.ho@mediatek.com>
* Erin Lo <erin.lo@mediatek.com>
* Fabien Parent <fparent@baylibre.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt8183";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x002>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x003>;
enable-method = "psci";
capacity-dmips-mhz = <741>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt",
"mediatek,wdt";
reg = <0 0x10007000 0 0x100>;
status = "disabled";
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c100000 0 0x200000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
};
};
sysirq: interrupt-controller@c530a80 {
compatible = "mediatek,mt8183-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x0c530a80 0 0x50>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8183-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8183-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8183-uart",
"mediatek,hsuart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <26000000>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
<&infracfg CLK_INFRA_MSDC0>,
<&infracfg CLK_INFRA_MSDC0_SCK>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
u3phy: usb-phy@11f40000 {
compatible = "mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port0: usb-phy2@11f40000 {
reg = <0 0x11f40000 0 0x700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy3@11f40700 {
reg = <0 0x11f40700 0 0x900>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
usb: usb@11200000 {
compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
reg = <0 0x11200000 0 0x3e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>;
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
ssusb: ssusb@11200000 {
compatible = "mediatek,ssusb";
reg = <0 0x11200000 0 0x3e00>;
reg-names = "mac";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
usb_host: xhci@11200000 {
compatible = "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
&sata {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-ex.dts"
#include "r8a774b1-u-boot.dtsi"
&gpio3 {
bt_reg_on{
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "bt-reg-on";
};
};
&gpio4 {
wlan_reg_on{
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "wlan-reg-on";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};
/delete-node/ &audma0;
/delete-node/ &audma1;
/delete-node/ &can0;
/delete-node/ &can1;
/delete-node/ &canfd;
/delete-node/ &csi20;
/delete-node/ &csi40;
/delete-node/ &du;
/delete-node/ &fcpf0;
/delete-node/ &fcpvb0;
/delete-node/ &fcpvd0;
/delete-node/ &fcpvd1;
/delete-node/ &fcpvi0;
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &rcar_sound;
/delete-node/ &sdhi2;
/delete-node/ &sound_card;
/delete-node/ &vin0;
/delete-node/ &vin1;
/delete-node/ &vin2;
/delete-node/ &vin3;
/delete-node/ &vin4;
/delete-node/ &vin5;
/delete-node/ &vin6;
/delete-node/ &vin7;
/delete-node/ &vspb;
/delete-node/ &vspd0;
/delete-node/ &vspd1;
/delete-node/ &vspi0;
/ {
/delete-node/ hdmi0-out;
};
/ {
soc {
/delete-node/ fdp1@fe940000;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774c0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/tda998x.h>
/ {
model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
compatible = "si-linux,cat874", "renesas,r8a774c0";
aliases {
serial0 = &scif2;
serial1 = &hscif2;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&tda19988_out>;
};
};
};
leds {
compatible = "gpio-leds";
led0 {
gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
label = "LED0";
};
led1 {
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2 {
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3 {
gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "CAT874 HDMI sound";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&tda19988>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
wlan_en_reg: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&tda19988_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hscif2 {
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupt-parent = <&gpio6>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
tda19988: tda19988@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
video-ports = <0x234501>;
#sound-dai-cells = <0>;
audio-ports = <TDA998x_I2S 0x03>;
clocks = <&rcar_sound 1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tda19988_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
tda19988_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@32 {
compatible = "epson,rx8571";
reg = <0x32>;
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
};
&pfc {
du_pins: du {
groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp",
"du_clk_in_0";
function = "du";
};
hscif2_pins: hscif2 {
groups = "hscif2_data_a", "hscif2_ctrl_a";
function = "hscif2";
};
i2c1_pins: i2c1 {
groups = "i2c1_b";
function = "i2c1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clkout1_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data";
function = "ssi";
};
usb30_pins: usb30 {
groups = "usb30", "usb30_id";
function = "usb30";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
status = "okay";
pinctrl-0 = <&sdhi3_pins>;
pinctrl-names = "default";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
&usb2_phy0 {
renesas,no-otg-pins;
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Hihope board
*
* Copyright (C) 2021 Renesas Electronisc Corporation
*/
#include "r8a774c0-ek874.dts"
#include "r8a774c0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25m512jv", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};

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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a774c0-cat874.dts"
#include "cat875.dtsi"
/ {
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R8A774C0 SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
*/
#include "r8a779x-u-boot.dtsi"
/ {
soc {
rpc: rpc@ee200000 {
compatible = "renesas,rcar-gen3-rpc", "renesas,rpc-r8a774c0";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
/delete-node/ &can0;
/delete-node/ &can1;
/delete-node/ &canfd;
/delete-node/ &pwm0;
/delete-node/ &pwm1;
/delete-node/ &pwm2;
/delete-node/ &pwm3;
/delete-node/ &pwm4;
/delete-node/ &pwm5;
/delete-node/ &pwm6;
/delete-node/ &vin4;
/delete-node/ &vin5;
/delete-node/ &rcar_sound;
/delete-node/ &audma0;
/delete-node/ &sdhi1;
/delete-node/ &sdhi3;
/delete-node/ &vspb0;
/delete-node/ &vspd0;
/delete-node/ &vspd1;
/delete-node/ &vspi0;
/delete-node/ &fcpvb0;
/delete-node/ &fcpvd0;
/delete-node/ &fcpvd1;
/delete-node/ &fcpvi0;
/delete-node/ &csi40;
/delete-node/ &du;
/delete-node/ &lvds0;
/delete-node/ &lvds1;
/delete-node/ &hdmi_con_out;
/delete-node/ &sound;
/delete-node/ &tda19988;

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arch/arm/dts/r8a774c0.dtsi
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@ -256,7 +256,7 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a774c0";
reg = <0 0xe6060000 0 0x508>;
};
@ -960,6 +960,7 @@
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -1214,9 +1215,8 @@
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
@ -1698,6 +1698,25 @@
status = "disabled";
};
pciec0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a774c0-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xfe000000 0 0x80000>,
<0x0 0xfe100000 0 0x100000>,
<0x0 0xfe200000 0 0x200000>,
<0x0 0x30000000 0 0x8000000>,
<0x0 0x38000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
status = "disabled";
};
vspb0: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;

20
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
&sata {
status = "okay";
};

27
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts Normal file
View File

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h-ex.dts"
#include "r8a774e1-u-boot.dtsi"
&gpio3 {
bt_reg_on{
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "bt-reg-on";
};
};
&gpio4 {
wlan_reg_on{
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "wlan-reg-on";
};
};

41
arch/arm/dts/r8a774e1-hihope-rzg2h.dts Normal file
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H main board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};

59
arch/arm/dts/r8a774e1-u-boot.dtsi Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};
/delete-node/ &audma0;
/delete-node/ &audma1;
/delete-node/ &can0;
/delete-node/ &can1;
/delete-node/ &canfd;
/delete-node/ &csi20;
/delete-node/ &csi40;
/delete-node/ &du;
/delete-node/ &fcpf0;
/delete-node/ &fcpf1;
/delete-node/ &fcpvb0;
/delete-node/ &fcpvb1;
/delete-node/ &fcpvd0;
/delete-node/ &fcpvd1;
/delete-node/ &fcpvi0;
/delete-node/ &fcpvi1;
/delete-node/ &hdmi0;
/delete-node/ &lvds0;
/delete-node/ &rcar_sound;
/delete-node/ &sdhi2;
/delete-node/ &sound_card;
/delete-node/ &vin0;
/delete-node/ &vin1;
/delete-node/ &vin2;
/delete-node/ &vin3;
/delete-node/ &vin4;
/delete-node/ &vin5;
/delete-node/ &vin6;
/delete-node/ &vin7;
/delete-node/ &vspbc;
/delete-node/ &vspbd;
/delete-node/ &vspd0;
/delete-node/ &vspd1;
/delete-node/ &vspi0;
/delete-node/ &vspi1;
/ {
/delete-node/ hdmi0-out;
};
/ {
soc {
/delete-node/ fdp1@fe940000;
/delete-node/ fdp1@fe944000;
};
};

2
arch/arm/dts/zynq-zc702.dts
View File

@ -51,7 +51,7 @@
leds {
compatible = "gpio-leds";
ds23 {
led-ds23 {
label = "ds23";
gpios = <&gpio0 10 0>;
linux,default-trigger = "heartbeat";

2
arch/arm/dts/zynq-zturn-common.dtsi
View File

@ -112,7 +112,7 @@
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;

2
arch/arm/dts/zynq-zybo-z7.dts
View File

@ -31,7 +31,7 @@
gpio-leds {
compatible = "gpio-leds";
ld4 {
led-ld4 {
label = "zynq-zybo-z7:green:ld4";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};

22
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -284,18 +284,16 @@
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_dpsub {
clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
};
&xlnx_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
&zynqmp_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
&zynqmp_pcap {
clocks = <&zynqmp_clk PCAP>;
};
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
};

3
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View File

@ -88,9 +88,6 @@
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
/* phy-names = "...";
phys = <&lane0 PHY_TYPE_SGMII ... >
Note: lane0 sgmii/lane1 usb3 */
};
&gpio {

3
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View File

@ -118,9 +118,6 @@
reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
/* phy-names = "...";
phys = <&lane0 PHY_TYPE_SGMII ... >
Note: lane0 sgmii/lane1 usb3 */
};
&gpio {

2
arch/arm/dts/zynqmp-mini-emmc0.dts
View File

@ -51,6 +51,8 @@
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
bus-width = <8>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;

2
arch/arm/dts/zynqmp-mini-emmc1.dts
View File

@ -51,6 +51,8 @@
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
bus-width = <8>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;

2
arch/arm/dts/zynqmp-zc1232-revA.dts
View File

@ -78,8 +78,6 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
};
&uart0 {

23
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -175,26 +175,11 @@
dr_mode = "host";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&zynqmp_dp_snd_card0 {
status = "okay";
};
&zynqmp_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

8
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -124,6 +124,10 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-0";
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@ -154,6 +158,10 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-1";
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";

2
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@ -119,7 +119,7 @@
status = "okay";
};
&xlnx_dpdma {
&zynqmp_dpdma {
status = "okay";
};

48
arch/arm/dts/zynqmp-zcu100-revC.dts
View File

@ -69,27 +69,27 @@
leds {
compatible = "gpio-leds";
ds2 {
led-ds2 {
label = "ds2";
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds3 {
led-ds3 {
label = "ds3";
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx"; /* WLAN tx */
default-state = "off";
};
ds4 {
led-ds4 {
label = "ds4";
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0rx"; /* WLAN rx */
default-state = "off";
};
ds5 {
led-ds5 {
label = "ds5";
gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
@ -130,6 +130,18 @@
compatible = "iio-hwmon";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
si5335a_0: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5335a_1: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&dcc {
@ -212,7 +224,7 @@
compatible = "ti,tps65086";
reg = <0x5e>;
interrupt-parent = <&gpio>;
interrupts = <77 GPIO_ACTIVE_LOW>;
interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
@ -250,6 +262,13 @@
};
};
&psgtr {
status = "okay";
/* usb3, dps */
clocks = <&si5335a_0>, <&si5335a_1>;
clock-names = "ref0", "ref1";
};
&rtc {
status = "okay";
};
@ -281,10 +300,6 @@
};
};
&serdes {
status = "okay";
};
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
@ -318,8 +333,6 @@
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
maximum-speed = "super-speed";
};
@ -331,8 +344,6 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;
maximum-speed = "super-speed";
};
@ -347,3 +358,14 @@
&ams_ps {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};

110
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -137,6 +137,19 @@
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
};
&can1 {
@ -213,25 +226,25 @@
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
"", "", "", "", "", "", "", "", "";
gtr-sel0 {
gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr-sel1 {
gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel1";
};
gtr-sel2 {
gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
output-high; /* PCIE = 0, USB0 = 1 */
line-name = "sel2";
};
gtr-sel3 {
gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
output-high; /* PCIE = 0, SATA = 1 */
@ -494,8 +507,54 @@
si5341: clock-generator@36 { /* SI5341 - u69 */
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_4: out@4 {
/* refclk4 for PS-GT, used for PCIE slot */
reg = <4>;
always-on;
};
si5341_5: out@5 {
/* refclk5 for PS-GT, used for PCIE */
reg = <5>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_7: out@7 {
/* refclk7 PL CLK74 */
reg = <7>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
i2c@2 {
#address-cells = <1>;
@ -603,6 +662,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -649,7 +715,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -663,10 +729,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -684,8 +746,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -705,26 +765,12 @@
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&zynqmp_dp_snd_codec0 {
status = "okay";
};
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&zynqmp_dp_snd_card0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
};

44
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -40,6 +40,24 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can1 {
@ -226,6 +244,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -242,7 +267,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -253,10 +278,6 @@
disable-wp;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -274,8 +295,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -294,3 +313,14 @@
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};

44
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -46,6 +46,24 @@
compatible = "iio-hwmon";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can1 {
@ -243,6 +261,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
@ -255,7 +280,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -266,10 +291,6 @@
disable-wp;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -287,8 +308,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -307,3 +326,14 @@
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};

96
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -137,6 +137,19 @@
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
};
&can1 {
@ -147,6 +160,18 @@
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@ -490,8 +515,45 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u69 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_7: out@7 {
/* refclk7 PL CLK74 */
reg = <7>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
@ -528,8 +590,23 @@
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clock-output-names = "si5328";
si5328_clk: clk0@0 {
reg = <0>;
clock-frequency = <27000000>;
};
};
};
i2c@5 {
@ -601,6 +678,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -647,7 +731,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -660,10 +744,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -681,8 +761,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};
&watchdog0 {

78
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -121,6 +121,13 @@
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&dcc {
@ -386,10 +393,46 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u46 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
i2c@2 {
#address-cells = <1>;
@ -423,8 +466,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 { /* SI5328 - u48 */
compatible = "silabs,si5328";
si5382: clock-generator@69 { /* SI5382 - u48 */
compatible = "silabs,si5382";
reg = <0x69>;
};
};
@ -511,6 +554,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -557,7 +607,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -571,10 +621,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -582,12 +628,16 @@
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&dwc3_0 {
&zynqmp_dpdma {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};

63
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -120,6 +120,13 @@
compatible = "iio-hwmon";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&dcc {
@ -404,10 +411,41 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u43 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on; /* assigned-clocks does not enable, so do it here */
};
};
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;
@ -441,7 +479,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* U409B - 8a34001 */
idt_8a34001: phc@5b {
compatible = "idt,8a34001"; /* u409B */
reg = <0x5b>;
};
};
i2c_clk104: i2c@5 {
#address-cells = <1>;
@ -538,6 +579,13 @@
};
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -553,8 +601,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@ -568,10 +615,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -585,6 +628,4 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};

63
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -120,6 +120,20 @@
compatible = "iio-hwmon";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&dcc {
@ -408,10 +422,41 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u43 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on; /* assigned-clocks does not enable, so do it here */
};
};
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;
@ -445,7 +490,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* U409B - 8a34001 */
idt_8a34001: phc@5b {
compatible = "idt,8a34001"; /* u409B */
reg = <0x5b>;
};
};
i2c_clk104: i2c@5 {
#address-cells = <1>;
@ -557,8 +605,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@ -572,10 +619,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -589,6 +632,4 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};

156
arch/arm/dts/zynqmp.dtsi
View File

@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@ -160,11 +161,25 @@
mbox-names = "tx", "rx";
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc_revision@0 {
reg = <0x0 0x4>;
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
};
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
@ -198,16 +213,6 @@
ranges;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc_revision@0 {
reg = <0x0 0x4>;
};
};
amba: axi {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
@ -501,11 +506,11 @@
interrupts = <0 112 4>;
};
nand0: nand@ff100000 {
compatible = "arasan,nfc-v3p10";
nand0: nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
status = "disabled";
reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "clk_sys", "clk_flash";
clock-names = "controller", "bus";
interrupt-parent = <&gic>;
interrupts = <0 14 4>;
#address-cells = <1>;
@ -667,6 +672,15 @@
power-domains = <&zynqmp_firmware PD_QSPI>;
};
psgtr: phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <4>;
};
rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "disabled";
@ -677,45 +691,6 @@
calibration = <0x8000>;
};
serdes: zynqmp_phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>,
<0x0 0xff5e0000 0x0 0x1000>;
reg-names = "serdes", "siou", "lpd";
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
<&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
<&zynqmp_reset ZYNQMP_RESET_DP>,
<&zynqmp_reset ZYNQMP_RESET_GEM0>,
<&zynqmp_reset ZYNQMP_RESET_GEM1>,
<&zynqmp_reset ZYNQMP_RESET_GEM2>,
<&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "sata_rst", "usb0_crst", "usb1_crst",
"usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
"usb1_apbrst", "dp_rst", "gem0_rst",
"gem1_rst", "gem2_rst", "gem3_rst";
lane0: lane0 {
#phy-cells = <4>;
};
lane1: lane1 {
#phy-cells = <4>;
};
lane2: lane2 {
#phy-cells = <4>;
};
lane3: lane3 {
#phy-cells = <4>;
};
};
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
@ -740,11 +715,11 @@
xlnx,device_id = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
power-domains = <&zynqmp_firmware PD_SD_0>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
};
sdhci1: mmc@ff170000 {
@ -758,11 +733,11 @@
xlnx,device_id = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
power-domains = <&zynqmp_firmware PD_SD_1>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
};
smmu: iommu@fd800000 {
@ -962,37 +937,18 @@
};
};
xlnx_dpdma: dma@fd4c0000 {
compatible = "xlnx,dpdma";
zynqmp_dpdma: dma-controller@fd4c0000 {
compatible = "xlnx,zynqmp-dpdma";
status = "disabled";
reg = <0x0 0xfd4c0000 0x0 0x1000>;
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel {
compatible = "xlnx,video0";
};
dma-video1channel {
compatible = "xlnx,video1";
};
dma-video2channel {
compatible = "xlnx,video2";
};
dma-graphicschannel {
compatible = "xlnx,graphics";
};
dma-audio0channel {
compatible = "xlnx,audio0";
};
dma-audio1channel {
compatible = "xlnx,audio1";
};
};
zynqmp_dpsub: zynqmp-display@fd4a0000 {
zynqmp_dpsub: display@fd4a0000 {
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
@ -1002,51 +958,15 @@
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
vid-layer {
dma-names = "vid0", "vid1", "vid2";
dmas = <&xlnx_dpdma 0>,
<&xlnx_dpdma 1>,
<&xlnx_dpdma 2>;
};
gfx-layer {
dma-names = "gfx0";
dmas = <&xlnx_dpdma 3>;
};
/* dummy node to indicate there's no child i2c device */
i2c-bus {
};
zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
};
zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 4>;
dma-names = "tx";
};
zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 5>;
dma-names = "tx";
};
zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
<&zynqmp_dp_snd_pcm1>;
xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
};
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
dma-names = "vid0", "vid1", "vid2", "gfx0";
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
};
};
};

1
arch/arm/include/asm/cache.h
View File

@ -35,7 +35,6 @@ void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
void arm_init_before_mmu(void);
void arm_init_domains(void);
void cpu_cache_initialization(void);
void dram_bank_mmu_setup(int bank);

18
arch/arm/include/asm/system.h
View File

@ -397,20 +397,6 @@ static inline void set_cr(unsigned int val)
isb();
}
static inline unsigned int get_dacr(void)
{
unsigned int val;
asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
return val;
}
static inline void set_dacr(unsigned int val)
{
asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
: : "r" (val) : "cc");
isb();
}
#ifdef CONFIG_ARMV7_LPAE
/* Long-Descriptor Translation Table Level 1/2 Bits */
#define TTB_SECT_XN_MASK (1ULL << 54)
@ -475,7 +461,7 @@ enum dcache_option {
#define TTB_SECT_XN_MASK (1 << 4)
#define TTB_SECT_C_MASK (1 << 3)
#define TTB_SECT_B_MASK (1 << 2)
#define TTB_SECT (2 << 0)
#define TTB_SECT (2 << 0)
/*
* Short-descriptor format memory region attributes, without TEX remap
@ -489,7 +475,7 @@ enum dcache_option {
*/
enum dcache_option {
DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
};

13
arch/arm/lib/cache-cp15.c
View File

@ -22,10 +22,6 @@ __weak void arm_init_before_mmu(void)
{
}
__weak void arm_init_domains(void)
{
}
static void set_section_phys(int section, phys_addr_t phys,
enum dcache_option option)
{
@ -203,11 +199,12 @@ static inline void mmu_setup(void)
asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (gd->arch.tlb_addr) : "memory");
#endif
/* Set the access control to all-supervisor */
/*
* initial value of Domain Access Control Register (DACR)
* Set the access control to client (1U) for each of the 16 domains
*/
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
arm_init_domains();
: : "r" (0x55555555));
/* and enable the mmu */
reg = get_cr(); /* get control reg. */

2
arch/arm/lib/interrupts.c
View File

@ -53,7 +53,7 @@ int disable_interrupts(void)
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
reset_cpu(0);
reset_cpu();
}
static void show_efi_loaded_images(struct pt_regs *regs)

2
arch/arm/lib/interrupts_m.c
View File

@ -59,7 +59,7 @@ void dump_regs(struct autosave_regs *regs)
void bad_mode(void)
{
panic("Resetting CPU ...\n");
reset_cpu(0);
reset_cpu();
}
void do_hard_fault(struct autosave_regs *autosave_regs)

2
arch/arm/lib/reset.c
View File

@ -39,7 +39,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
disable_interrupts();
reset_misc();
reset_cpu(0);
reset_cpu();
/*NOTREACHED*/
return 0;

2
arch/arm/mach-at91/arm920t/reset.c
View File

@ -24,7 +24,7 @@ void __attribute__((weak)) board_reset(void)
/* true empty function for defining weak symbol */
}
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;

16
arch/arm/mach-at91/arm926ejs/lowlevel_init.S
View File

@ -71,10 +71,10 @@ POS1:
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_IXR_MOSCS
mov r6, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
ldr r3, [r2]
and r3, r4, r3
and r3, r6, r3
cmp r3, #AT91_PMC_IXR_MOSCS
bne MOSCS_Loop
@ -89,10 +89,10 @@ MOSCS_Loop:
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
mov r4, #AT91_PMC_IXR_LOCKA
mov r6, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
ldr r3, [r2]
and r3, r4, r3
and r3, r6, r3
cmp r3, #AT91_PMC_IXR_LOCKA
bne MOSCS_Loop1
@ -109,10 +109,10 @@ MOSCS_Loop1:
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
mov r6, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
ldr r3, [r2]
and r3, r4, r3
and r3, r6, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
@ -120,10 +120,10 @@ MCKRDY_Loop:
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
mov r6, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
ldr r3, [r2]
and r3, r4, r3
and r3, r6, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop1
PLL_setup_end:

2
arch/arm/mach-at91/arm926ejs/reset.c
View File

@ -12,7 +12,7 @@
#include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;

2
arch/arm/mach-at91/armv7/reset.c
View File

@ -15,7 +15,7 @@
#include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;

1
arch/arm/mach-at91/include/mach/atmel_pio4.h
View File

@ -44,6 +44,7 @@ struct atmel_pio4_port {
#define ATMEL_PIO_DIR_MASK BIT(8)
#define ATMEL_PIO_PUEN_MASK BIT(9)
#define ATMEL_PIO_PDEN_MASK BIT(10)
#define ATMEL_PIO_SR BIT(11)
#define ATMEL_PIO_IFEN_MASK BIT(12)
#define ATMEL_PIO_IFSCEN_MASK BIT(13)
#define ATMEL_PIO_OPD_MASK BIT(14)

2
arch/arm/mach-bcm283x/reset.c
View File

@ -48,7 +48,7 @@ __reset_cpu(struct bcm2835_wdog_regs *wdog_regs, ulong ticks)
writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
}
void reset_cpu(ulong ticks)
void reset_cpu(void)
{
struct bcm2835_wdog_regs *regs =
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;

2
arch/arm/mach-davinci/reset.c
View File

@ -12,7 +12,7 @@
#include <asm/arch/timer_defs.h>
#include <asm/arch/hardware.h>
void reset_cpu(unsigned long a)
void reset_cpu(void)
{
struct davinci_timer *const wdttimer =
(struct davinci_timer *)DAVINCI_WDOG_BASE;

2
arch/arm/mach-exynos/soc.c
View File

@ -20,7 +20,7 @@ extern void _main(void);
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
void reset_cpu(ulong addr)
void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());

2
arch/arm/mach-imx/imx8m/soc.c
View File

@ -923,7 +923,7 @@ usb_modify_speed:
#endif
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(ulong addr)
void reset_cpu(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

2
arch/arm/mach-imx/mx7ulp/soc.c
View File

@ -197,7 +197,7 @@ void s_init(void)
#endif
#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)
void reset_cpu(void)
{
setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
while (1)

2
arch/arm/mach-k3/common.c
View File

@ -320,7 +320,7 @@ int fdt_disable_node(void *blob, char *node_path)
#endif
#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
}
#endif

4
arch/arm/mach-keystone/ddr3.c
View File

@ -345,7 +345,7 @@ void ddr3_check_ecc_int(u32 base)
if (!ecc_test) {
puts("Reseting the device ...\n");
reset_cpu(0);
reset_cpu();
}
}
@ -445,7 +445,7 @@ void ddr3_err_reset_workaround(void)
tmp &= ~KS2_RSTYPE_PLL_SOFT;
__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
reset_cpu(0);
reset_cpu();
}
}
#endif

2
arch/arm/mach-keystone/init.c
View File

@ -192,7 +192,7 @@ int arch_cpu_init(void)
return 0;
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
u32 tmp;

2
arch/arm/mach-kirkwood/cpu.c
View File

@ -19,7 +19,7 @@
#include <asm/arch/soc.h>
#include <mvebu_mmc.h>
void reset_cpu(unsigned long ignored)
void reset_cpu(void)
{
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;

23
arch/arm/mach-lpc32xx/cpu.c
View File

@ -17,28 +17,17 @@
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
void reset_cpu(ulong addr)
void reset_cpu(void)
{
/* Enable watchdog clock */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
/* To be compatible with the original U-Boot code:
* addr: - 0: perform hard reset.
* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
if (addr == 0) {
/* Reset pulse length is 13005 peripheral clock frames */
writel(13000, &wdt->pulse);
/* Reset pulse length is 13005 peripheral clock frames */
writel(13000, &wdt->pulse);
/* Force WDOG_RESET2 and RESOUT_N signal active */
writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
| WDTIM_MCTRL_M_RES2, &wdt->mctrl);
} else {
/* Force match output active */
writel(0x01, &wdt->emr);
/* Internal reset on match output (no pulse on "RESOUT_N") */
writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
}
/* Force WDOG_RESET2 and RESOUT_N signal active */
writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
&wdt->mctrl);
while (1)
/* NOP */;

13
arch/arm/mach-mediatek/Kconfig
View File

@ -36,12 +36,20 @@ config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
select SPL
select BINMAN
help
The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
config TARGET_MT8183
bool "MediaTek MT8183 SoC"
select ARM64
help
The MediaTek MT8183 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@ -75,8 +83,9 @@ endchoice
source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
source "board/mediatek/mt8183/Kconfig"
source "board/mediatek/mt8512/Kconfig"
source "board/mediatek/mt8516/Kconfig"
source "board/mediatek/mt8518/Kconfig"
source "board/mediatek/pumpkin/Kconfig"
endif

1
arch/arm/mach-mediatek/Makefile
View File

@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/

2
arch/arm/mach-mediatek/mt7622/init.c
View File

@ -27,7 +27,7 @@ int dram_init(void)
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
psci_system_reset();
}

2
board/mediatek/pumpkin/Makefile → arch/arm/mach-mediatek/mt8183/Makefile
View File

@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += pumpkin.o
obj-y += init.o

80
arch/arm/mach-mediatek/mt8183/init.c Normal file
View File

@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 MediaTek Inc.
* Copyright (C) 2021 BayLibre, SAS
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <ram.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8516-clk.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
int ret;
ret = fdtdec_setup_memory_banksize();
if (ret)
return ret;
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
int mtk_pll_early_init(void)
{
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
psci_system_reset();
}
int print_cpuinfo(void)
{
printf("CPU: MediaTek MT8183\n");
return 0;
}
static struct mm_region mt8183_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8183_mem_map;

2
arch/arm/mach-mediatek/mt8512/init.c
View File

@ -43,7 +43,7 @@ int dram_init_banksize(void)
return 0;
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
struct udevice *watchdog_dev = NULL;

2
arch/arm/mach-mediatek/mt8516/init.c
View File

@ -85,7 +85,7 @@ int mtk_soc_early_init(void)
return 0;
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
psci_system_reset();
}

2
arch/arm/mach-mediatek/mt8518/init.c
View File

@ -42,7 +42,7 @@ int dram_init_banksize(void)
return 0;
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
psci_system_reset();
}

4
arch/arm/mach-meson/board-common.c
View File

@ -167,7 +167,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
return 0;
}
void reset_cpu(ulong addr)
void reset_cpu(void)
{
struct pt_regs regs;
@ -182,7 +182,7 @@ void reset_cpu(ulong addr)
;
}
#else
void reset_cpu(ulong addr)
void reset_cpu(void)
{
psci_system_reset();
}

2
arch/arm/mach-mvebu/armada3700/cpu.c
View File

@ -314,7 +314,7 @@ int a3700_fdt_fix_pcie_regions(void *blob)
return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
}
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
/*
* Write magic number of 0x1d1e to North Bridge Warm Reset register

2
arch/arm/mach-mvebu/armada8k/cpu.c
View File

@ -104,7 +104,7 @@ void enable_caches(void)
dcache_enable();
}
void reset_cpu(ulong ignored)
void reset_cpu(void)
{
u32 reg;

2
arch/arm/mach-mvebu/cpu.c
View File

@ -42,7 +42,7 @@ void lowlevel_init(void)
*/
}
void reset_cpu(unsigned long ignored)
void reset_cpu(void)
{
struct mvebu_system_registers *reg =
(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;

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