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dm: i2c: s3c24x0: adjust to dm-i2c api
This commit adjusts the s3c24x0 driver to new i2c api based on driver-model. The driver supports standard and high-speed i2c as previous. Tested on Trats2, Odroid U3, Arndale, Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Przemyslaw Marczak
Simon Glass
parent
fda0e27bfd
commit
8dfcbaa681
@ -9,8 +9,9 @@
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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#include <asm/arch/clk.h>
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@ -121,13 +122,23 @@
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#define CONFIG_MAX_I2C_NUM 1
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* For SPL boot some boards need i2c before SDRAM is initialised so force
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* variables to live in SRAM
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*/
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#ifdef CONFIG_SYS_I2C
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static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
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__attribute__((section(".data")));
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#endif
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enum exynos_i2c_type {
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EXYNOS_I2C_STD,
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EXYNOS_I2C_HS,
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};
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#ifdef CONFIG_SYS_I2C
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/**
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* Get a pointer to the given bus index
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*
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@ -147,6 +158,7 @@ static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
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debug("Undefined bus: %d\n", bus_idx);
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return NULL;
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}
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#endif
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#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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static int GetI2CSDA(void)
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@ -251,6 +263,7 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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#ifdef CONFIG_SYS_I2C
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static struct s3c24x0_i2c *get_base_i2c(int bus)
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{
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#ifdef CONFIG_EXYNOS4
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@ -267,6 +280,7 @@ static struct s3c24x0_i2c *get_base_i2c(int bus)
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return s3c24x0_get_base_i2c();
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#endif
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}
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#endif
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static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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{
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@ -326,7 +340,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
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return 0;
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}
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}
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return -1;
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return -EINVAL;
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}
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static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
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@ -398,18 +412,20 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
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hsi2c_ch_init(i2c_bus);
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}
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#ifdef CONFIG_SYS_I2C
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static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct s3c24x0_i2c *i2c;
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struct s3c24x0_i2c_bus *bus;
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#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#endif
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ulong start_time = get_timer(0);
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/* By default i2c channel 0 is the current bus */
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i2c = get_base_i2c(adap->hwadapnr);
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bus = &i2c_bus[adap->hwadapnr];
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if (!bus)
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return;
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/*
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* In case the previous transfer is still going, wait to give it a
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@ -470,12 +486,13 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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#endif
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}
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#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
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i2c_ch_init(i2c, speed, slaveadd);
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bus = &i2c_bus[adap->hwadapnr];
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bus->active = true;
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bus->regs = i2c;
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}
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#endif /* CONFIG_SYS_I2C */
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/*
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* Poll the appropriate bit of the fifo status register until the interface is
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@ -698,20 +715,27 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
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return rv;
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}
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#ifdef CONFIG_SYS_I2C
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static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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unsigned int speed)
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#else
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static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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#endif
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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#ifdef CONFIG_SYS_I2C
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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return -EFAULT;
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#else
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i2c_bus = dev_get_priv(dev);
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#endif
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i2c_bus->clock_frequency = speed;
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if (i2c_bus->is_highspeed) {
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if (hsi2c_get_clk_details(i2c_bus))
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return -1;
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return -EFAULT;
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hsi2c_ch_init(i2c_bus);
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} else {
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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@ -721,17 +745,6 @@ static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
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return 0;
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}
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#ifdef CONFIG_EXYNOS5
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static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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/* This will override the speed selected in the fdt for that port */
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debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
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if (i2c_set_bus_speed(speed))
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printf("i2c_init: failed to init bus %d for speed = %d\n",
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adap->hwadapnr, speed);
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}
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#endif
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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@ -844,15 +857,23 @@ bailout:
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return result;
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}
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#ifdef CONFIG_SYS_I2C
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static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
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#else
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static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
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#endif
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{
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struct s3c24x0_i2c_bus *i2c_bus;
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uchar buf[1];
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int ret;
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#ifdef CONFIG_SYS_I2C
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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return -EFAULT;
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#else
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i2c_bus = dev_get_priv(dev);
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#endif
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buf[0] = 0;
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/*
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@ -871,6 +892,7 @@ static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
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return ret != I2C_OK;
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}
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#ifdef CONFIG_SYS_I2C
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static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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@ -878,9 +900,13 @@ static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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uchar xaddr[4];
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int ret;
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -EFAULT;
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if (alen > 4) {
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debug("I2C read: addr len %d not supported\n", alen);
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return 1;
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return -EADDRNOTAVAIL;
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}
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if (alen > 0) {
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@ -906,10 +932,6 @@ static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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if (i2c_bus->is_highspeed)
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ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
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alen, buffer, len);
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@ -921,7 +943,7 @@ static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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if (i2c_bus->is_highspeed)
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exynos5_i2c_reset(i2c_bus);
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debug("I2c read failed %d\n", ret);
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return 1;
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return -EIO;
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}
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return 0;
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}
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@ -933,9 +955,13 @@ static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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uchar xaddr[4];
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int ret;
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -EFAULT;
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if (alen > 4) {
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debug("I2C write: addr len %d not supported\n", alen);
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return 1;
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return -EINVAL;
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}
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if (alen > 0) {
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@ -960,10 +986,6 @@ static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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i2c_bus = get_bus(adap->hwadapnr);
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if (!i2c_bus)
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return -1;
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if (i2c_bus->is_highspeed)
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ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
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alen, buffer, len, true);
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@ -985,7 +1007,7 @@ static void process_nodes(const void *blob, int node_list[], int count,
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int is_highspeed)
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{
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struct s3c24x0_i2c_bus *bus;
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int i;
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int i, flags;
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for (i = 0; i < count; i++) {
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int node = node_list[i];
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@ -997,12 +1019,15 @@ static void process_nodes(const void *blob, int node_list[], int count,
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bus->active = true;
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bus->is_highspeed = is_highspeed;
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if (is_highspeed)
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if (is_highspeed) {
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flags = PINMUX_FLAG_HS_MODE;
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bus->hsregs = (struct exynos5_hsi2c *)
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fdtdec_get_addr(blob, node, "reg");
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else
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} else {
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flags = 0;
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bus->regs = (struct s3c24x0_i2c *)
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fdtdec_get_addr(blob, node, "reg");
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}
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bus->id = pinmux_decode_periph_id(blob, node);
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bus->clock_frequency = fdtdec_get_int(blob, node,
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@ -1010,7 +1035,7 @@ static void process_nodes(const void *blob, int node_list[], int count,
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CONFIG_SYS_I2C_S3C24X0_SPEED);
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bus->node = node;
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bus->bus_num = i;
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exynos_pinmux_config(bus->id, 0);
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exynos_pinmux_config(PERIPH_ID_I2C0 + bus->id, flags);
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/* Mark position as used */
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node_list[i] = -1;
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@ -1033,7 +1058,6 @@ void board_i2c_init(const void *blob)
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COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
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CONFIG_MAX_I2C_NUM);
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process_nodes(blob, node_list, count, 1);
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}
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int i2c_get_bus_num_fdt(int node)
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@ -1046,7 +1070,7 @@ int i2c_get_bus_num_fdt(int node)
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}
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debug("%s: Can't find any matched I2C bus\n", __func__);
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return -1;
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return -EINVAL;
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}
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int i2c_reset_port_fdt(const void *blob, int node)
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@ -1057,18 +1081,18 @@ int i2c_reset_port_fdt(const void *blob, int node)
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bus = i2c_get_bus_num_fdt(node);
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if (bus < 0) {
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debug("could not get bus for node %d\n", node);
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return -1;
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return bus;
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}
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i2c_bus = get_bus(bus);
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if (!i2c_bus) {
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debug("get_bus() failed for node node %d\n", node);
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return -1;
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debug("get_bus() failed for node %d\n", node);
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return -EFAULT;
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}
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if (i2c_bus->is_highspeed) {
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if (hsi2c_get_clk_details(i2c_bus))
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return -1;
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return -EINVAL;
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hsi2c_ch_init(i2c_bus);
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} else {
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i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
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@ -1077,7 +1101,17 @@ int i2c_reset_port_fdt(const void *blob, int node)
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return 0;
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}
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#endif
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#endif /* CONFIG_OF_CONTROL */
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#ifdef CONFIG_EXYNOS5
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static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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/* This will override the speed selected in the fdt for that port */
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debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
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if (i2c_set_bus_speed(speed))
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error("i2c_init: failed to init bus for speed = %d", speed);
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}
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#endif /* CONFIG_EXYNOS5 */
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/*
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* Register s3c24x0 i2c adapters
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@ -1247,3 +1281,120 @@ U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
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CONFIG_SYS_I2C_S3C24X0_SPEED,
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CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
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#endif
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#endif /* CONFIG_SYS_I2C */
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#ifdef CONFIG_DM_I2C
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static int i2c_write_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip,
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uchar *buffer, int len, bool end_with_repeated_start)
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{
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int ret;
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if (i2c_bus->is_highspeed) {
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ret = hsi2c_write(i2c_bus->hsregs, chip, 0, 0,
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buffer, len, true);
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if (ret)
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exynos5_i2c_reset(i2c_bus);
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} else {
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ret = i2c_transfer(i2c_bus->regs, I2C_WRITE,
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chip << 1, 0, 0, buffer, len);
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}
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return ret != I2C_OK;
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}
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static int i2c_read_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip,
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uchar *buffer, int len)
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{
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int ret;
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if (i2c_bus->is_highspeed) {
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ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buffer, len);
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if (ret)
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exynos5_i2c_reset(i2c_bus);
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} else {
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ret = i2c_transfer(i2c_bus->regs, I2C_READ,
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chip << 1, 0, 0, buffer, len);
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}
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return ret != I2C_OK;
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}
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static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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int ret;
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for (; nmsgs > 0; nmsgs--, msg++) {
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bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
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if (msg->flags & I2C_M_RD) {
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ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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} else {
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ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len, next_is_read);
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}
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if (ret)
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return -EREMOTEIO;
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}
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return 0;
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}
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static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
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int node, flags;
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i2c_bus->is_highspeed = dev->of_id->data;
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node = dev->of_offset;
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if (i2c_bus->is_highspeed) {
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flags = PINMUX_FLAG_HS_MODE;
|
||||
i2c_bus->hsregs = (struct exynos5_hsi2c *)
|
||||
fdtdec_get_addr(blob, node, "reg");
|
||||
} else {
|
||||
flags = 0;
|
||||
i2c_bus->regs = (struct s3c24x0_i2c *)
|
||||
fdtdec_get_addr(blob, node, "reg");
|
||||
}
|
||||
|
||||
i2c_bus->id = pinmux_decode_periph_id(blob, node);
|
||||
|
||||
i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
|
||||
"clock-frequency",
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED);
|
||||
i2c_bus->node = node;
|
||||
i2c_bus->bus_num = dev->seq;
|
||||
|
||||
exynos_pinmux_config(i2c_bus->id, flags);
|
||||
|
||||
i2c_bus->active = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_i2c_ops s3c_i2c_ops = {
|
||||
.xfer = s3c24x0_i2c_xfer,
|
||||
.probe_chip = s3c24x0_i2c_probe,
|
||||
.set_bus_speed = s3c24x0_i2c_set_bus_speed,
|
||||
};
|
||||
|
||||
static const struct udevice_id s3c_i2c_ids[] = {
|
||||
{ .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
|
||||
{ .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(i2c_s3c) = {
|
||||
.name = "i2c_s3c",
|
||||
.id = UCLASS_I2C,
|
||||
.of_match = s3c_i2c_ids,
|
||||
.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
|
||||
.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
|
||||
.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
|
||||
.ops = &s3c_i2c_ops,
|
||||
};
|
||||
#endif /* CONFIG_DM_I2C */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user