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sh3/sh4: fix CONFIG_SYS_HZ to 1000

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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2009-06-04 12:06:47 +02:00 committed by Nobuhiro Iwamatsu
parent add380f51f
commit 8dd29c87ba
11 changed files with 44 additions and 27 deletions
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2
include/configs/MigoR.h
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@ -142,6 +142,6 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#endif /* __MIGO_R_H */

2
include/configs/ap325rxa.h
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@ -171,6 +171,6 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#endif /* __AP325RXA_H */

2
include/configs/mpr2.h
View File

@ -83,7 +83,7 @@
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
/* UART */
#define CONFIG_SCIF_CONSOLE 1

2
include/configs/ms7720se.h
View File

@ -102,7 +102,7 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1

2
include/configs/ms7722se.h
View File

@ -129,6 +129,6 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#endif /* __MS7722SE_H */

2
include/configs/ms7750se.h
View File

@ -102,6 +102,6 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#endif /* __MS7750SE_H */

2
include/configs/r2dplus.h
View File

@ -81,7 +81,7 @@
*/
#define CONFIG_SYS_CLK_FREQ 60000000
#define TMU_CLK_DIVIDER 4
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*

2
include/configs/r7780mp.h
View File

@ -122,7 +122,7 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)

2
include/configs/sh7763rdp.h
View File

@ -115,7 +115,7 @@
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
/* Ether */
#define CONFIG_NET_MULTI 1

2
include/configs/sh7785lcr.h
View File

@ -187,6 +187,6 @@
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
#define TMU_CLK_DIVIDER 4
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define CONFIG_SYS_HZ 1000
#endif /* __SH7785LCR_H */

51
lib_sh/time.c
View File

@ -1,4 +1,7 @@
/*
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* (C) Copyright 2007-2008
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
@ -25,11 +28,30 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/processor.h>
#include <asm/clk.h>
#include <asm/io.h>
#define TMU_MAX_COUNTER (~0UL)
static int clk_adj = 1;
static ulong timer_freq;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, timer_freq);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= timer_freq;
do_div(usec, 1000000);
return usec;
}
static void tmu_timer_start (unsigned int timer)
{
@ -65,15 +87,12 @@ int timer_init (void)
break;
case 4:
default:
bit = 0;
break;
}
writew(readw(TCR0) | bit, TCR0);
/* Clock adjustment calc */
clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000));
if (clk_adj < 1)
clk_adj = 1;
/* Calc clock rate */
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
@ -86,24 +105,22 @@ unsigned long long get_ticks (void)
return 0 - readl(TCNT0);
}
static unsigned long get_usec (void)
{
return (0 - readl(TCNT0));
}
void udelay (unsigned long usec)
{
unsigned int start = get_usec();
unsigned int end = start + (usec * clk_adj);
unsigned long long tmp;
ulong tmo;
while (get_usec() < end)
continue;
tmo = usec_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
unsigned long get_timer (unsigned long base)
{
/* return msec */
return ((get_usec() / clk_adj) / 1000) - base;
return tick_to_time(get_ticks()) - base;
}
void set_timer (unsigned long t)
@ -120,5 +137,5 @@ void reset_timer (void)
unsigned long get_tbclk (void)
{
return CONFIG_SYS_HZ;
return timer_freq;
}