mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-23 20:24:26 +08:00
Convert CONFIG_SYS_NAND_PAGE_COUNT to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_COUNT Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
a0de075392
commit
8db73ec106
@ -48,8 +48,6 @@
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#define CONFIG_SYS_NAND_ECCSIZE 0x100
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#endif /* CONFIG_NAND_LPC32XX_SLC */
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/* NOR Flash */
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@ -60,6 +60,7 @@ CONFIG_MMC_OMAP_HS_ADMA=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -64,6 +64,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -89,6 +89,7 @@ CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0x100
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -73,6 +73,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_MTD_UBI_FASTMAP=y
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@ -58,6 +58,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -61,6 +61,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SF_DEFAULT_SPEED=48000000
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@ -48,6 +48,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SF_DEFAULT_SPEED=48000000
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@ -64,6 +64,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SF_DEFAULT_SPEED=48000000
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@ -66,6 +66,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SF_DEFAULT_SPEED=48000000
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@ -74,6 +74,7 @@ CONFIG_MTD_RAW_NAND=y
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# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
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CONFIG_NAND_ATMEL=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -90,6 +90,7 @@ CONFIG_MISC=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -54,6 +54,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHY_SMSC=y
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@ -62,6 +62,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHY_ATHEROS=y
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@ -62,6 +62,7 @@ CONFIG_MTD_RAW_NAND=y
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# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
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CONFIG_NAND_ATMEL=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHYLIB=y
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@ -69,6 +69,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_DAVINCI=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -54,6 +54,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_LPC32XX_SLC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHYLIB=y
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@ -42,6 +42,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -93,6 +93,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -85,6 +85,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -86,6 +86,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_PAGE_COUNT=0x80
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_DM_SPI_FLASH=y
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@ -88,6 +88,7 @@ CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_MTD_UBI_FASTMAP=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_ETH=y
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@ -61,6 +61,7 @@ CONFIG_MTD=y
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CONFIG_SYS_MTDPARTS_RUNTIME=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -79,6 +79,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_MXC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHYLIB=y
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@ -58,6 +58,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -63,6 +63,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -75,6 +75,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -63,6 +63,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -58,6 +58,7 @@ CONFIG_MMC_OMAP36XX_PINS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -64,6 +64,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -66,6 +66,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_DAVINCI=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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@ -67,6 +67,7 @@ CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -67,6 +67,7 @@ CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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@ -85,6 +85,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -85,6 +85,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -85,6 +85,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -70,6 +70,7 @@ CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_ETH=y
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@ -72,6 +72,7 @@ CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -67,6 +67,7 @@ CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_DM_SPI_FLASH=y
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@ -65,6 +65,7 @@ CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_DM_SPI_FLASH=y
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@ -64,6 +64,7 @@ CONFIG_MTD_RAW_NAND=y
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# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
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CONFIG_NAND_ATMEL=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_PHYLIB=y
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@ -80,6 +80,7 @@ CONFIG_MTD_RAW_NAND=y
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# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
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CONFIG_NAND_ATMEL=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -85,6 +85,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_DM_SPI_FLASH=y
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@ -60,6 +60,7 @@ CONFIG_MMC_OMAP_HS=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
|
@ -370,6 +370,13 @@ config SYS_NAND_BLOCK_SIZE
|
||||
board. This is the multiple of NAND_PAGE_SIZE and the number of
|
||||
pages.
|
||||
|
||||
config SYS_NAND_PAGE_COUNT
|
||||
hex "NAND chip page count"
|
||||
depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
|
||||
SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
|
||||
help
|
||||
Number of pages in the NAND chip.
|
||||
|
||||
config SYS_NAND_PAGE_SIZE
|
||||
hex "NAND chip page size"
|
||||
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
|
||||
|
@ -181,8 +181,6 @@
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
|
@ -108,8 +108,6 @@
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
|
||||
|
@ -107,8 +107,6 @@
|
||||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -20,7 +20,6 @@
|
||||
/* Board NAND Info. */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
|
||||
11, 12, 13, 14, 16, 17, 18, 19, 20, \
|
||||
|
@ -157,8 +157,6 @@
|
||||
/* NAND support */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
@ -97,7 +97,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -116,7 +116,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
@ -99,7 +99,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
@ -210,8 +210,6 @@
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -147,8 +147,6 @@ NANDTGTS \
|
||||
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -124,8 +124,6 @@
|
||||
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
|
@ -86,8 +86,6 @@
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -28,8 +28,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
@ -99,8 +99,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -135,7 +135,6 @@
|
||||
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
|
||||
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
|
||||
59, 60, 61, 62, 63 }
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 10
|
||||
|
@ -134,7 +134,6 @@
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
|
@ -80,8 +80,6 @@
|
||||
/* NAND support */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
@ -61,7 +61,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
|
@ -140,8 +140,6 @@
|
||||
#define CONFIG_SPL_STACK 0x70004000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
|
||||
|
@ -23,7 +23,6 @@
|
||||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
|
@ -28,7 +28,6 @@
|
||||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
|
@ -76,7 +76,6 @@
|
||||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -19,7 +19,6 @@
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
|
||||
/* NAND devices */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
|
||||
13, 14, 16, 17, 18, 19, 20, 21, 22, \
|
||||
|
@ -135,7 +135,6 @@
|
||||
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
|
||||
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 10
|
||||
|
@ -86,8 +86,6 @@
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
|
@ -87,7 +87,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -71,7 +71,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
/* Falcon boot support on raw MMC */
|
||||
|
@ -83,7 +83,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
@ -47,7 +47,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
@ -47,7 +47,6 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
@ -74,8 +74,6 @@
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
|
@ -169,8 +169,6 @@
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (SZ_256M)
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -126,7 +126,6 @@
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
|
||||
|
@ -171,8 +171,6 @@
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
|
@ -58,8 +58,6 @@
|
||||
|
||||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
|
@ -2410,7 +2410,6 @@ CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
CONFIG_SYS_NAND_OR_PRELIM
|
||||
CONFIG_SYS_NAND_PAGE_2K
|
||||
CONFIG_SYS_NAND_PAGE_4K
|
||||
CONFIG_SYS_NAND_PAGE_COUNT
|
||||
CONFIG_SYS_NAND_QUIET
|
||||
CONFIG_SYS_NAND_READY_PIN
|
||||
CONFIG_SYS_NAND_REGS_BASE
|
||||
|
Loading…
Reference in New Issue
Block a user