mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-25 05:04:23 +08:00
update/fix AcTux3 board
Signed-off-by: Michael Schwingen <michael@schwingen.org>
This commit is contained in:
Michael Schwingen
Albert ARIBAUD
parent
af0504858c
commit
8b5ab4c1b6
@ -36,72 +36,76 @@
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include "actux3_hw.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init (void)
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int board_early_init_f(void)
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{
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/* CS1: IPAC-X */
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writel(0x94d10013, IXP425_EXP_CS1);
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/* CS5: Debug port */
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writel(0x9d520003, IXP425_EXP_CS5);
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/* CS6: Release/Option register */
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writel(0x81860001, IXP425_EXP_CS6);
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/* CS7: LEDs */
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writel(0x80900003, IXP425_EXP_CS7);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
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/*
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* Setup GPIO's for Interrupt inputs
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*/
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GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
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GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
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/*
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* Setup GPIO's for 33MHz clock output
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*/
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
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*IXP425_GPIO_GPCLKR = 0x011001FF;
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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writel(0x011001FF, IXP425_GPIO_GPCLKR);
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/* CS1: IPAC-X */
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*IXP425_EXP_CS1 = 0x94d10013;
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/* CS5: Debug port */
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*IXP425_EXP_CS5 = 0x9d520003;
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/* CS6: Release/Option register */
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*IXP425_EXP_CS6 = 0x81860001;
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/* CS7: LEDs */
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*IXP425_EXP_CS7 = 0x80900003;
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/* we need a minimum PCI reset pulse width after enabling the clock */
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udelay(533);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
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udelay (533);
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GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
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ACTUX3_LED1_RT (1);
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ACTUX3_LED1_GN (0);
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ACTUX3_LED2_RT (0);
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ACTUX3_LED2_GN (0);
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ACTUX3_LED3_RT (0);
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ACTUX3_LED3_GN (0);
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ACTUX3_LED4_GN (0);
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ACTUX3_LED5_RT (0);
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ACTUX3_LED1_RT(1);
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ACTUX3_LED1_GN(0);
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ACTUX3_LED2_RT(0);
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ACTUX3_LED2_GN(0);
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ACTUX3_LED3_RT(0);
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ACTUX3_LED3_GN(0);
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ACTUX3_LED4_GN(0);
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ACTUX3_LED5_RT(0);
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return 0;
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}
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@ -109,21 +113,21 @@ int board_init (void)
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/*
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* Check Board Identity
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*/
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int checkboard (void)
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts ("Board: AcTux-3 rev.");
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putc (ACTUX3_BOARDREL + 'A' - 1);
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puts("Board: AcTux-3 rev.");
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putc(ACTUX3_BOARDREL + 'A' - 1);
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if (i > 0) {
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puts (", serial# ");
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puts (buf);
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}
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putc ('\n');
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putc('\n');
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return (0);
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return 0;
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}
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/*************************************************************************
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@ -132,34 +136,32 @@ int checkboard (void)
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* 1 = Rev. A
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* 2 = Rev. B
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*************************************************************************/
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u32 get_board_rev (void)
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u32 get_board_rev(void)
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{
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return ACTUX3_BOARDREL;
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}
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int dram_init (void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return (0);
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
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return 0;
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}
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void reset_phy (void)
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void reset_phy(void)
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{
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int i;
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/* initialize the PHY */
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miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
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miiphy_reset("NPE0", CONFIG_PHY_ADDR);
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/* all LED outputs = Link/Act */
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miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
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miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
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/*
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* The Marvell 88E6060 switch comes up with all ports disabled.
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* set all ethernet switch ports to forwarding state
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*/
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for (i = 1; i <= 5; i++)
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miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
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miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
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}
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@ -1,4 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0x00e00000
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# include NPE ethernet driver
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BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
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@ -30,34 +30,29 @@ SECTIONS
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. = ALIGN (4);
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.text : {
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arch/arm/cpu/ixp/start.o (.text)
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lib/string.o (.text)
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lib/vsprintf.o (.text)
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arch/arm/lib/board.o (.text)
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common/dlmalloc.o (.text)
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arch/arm/cpu/ixp/cpu.o (.text)
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arch/arm/cpu/ixp/start.o(.text*)
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net/libnet.o(.text*)
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board/actux3/libactux3.o(.text*)
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arch/arm/cpu/ixp/libixp.o(.text*)
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drivers/serial/libserial.o(.text*)
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. = env_offset;
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common/env_embedded.o (.ppcenv)
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* (.text)
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common/env_embedded.o(.ppcenv)
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*(.text*)
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}
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. = ALIGN (4);
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. = ALIGN(4);
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.rodata : {
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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}
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. = ALIGN (4);
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. = ALIGN(4);
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.data : {
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*(.data)
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*(.data*)
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}
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. = ALIGN (4);
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. = ALIGN(4);
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.got : {
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*(.got)
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}
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. =.;
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__u_boot_cmd_start =.;
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.u_boot_cmd : {
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@ -66,10 +61,27 @@ SECTIONS
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__u_boot_cmd_end =.;
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. = ALIGN (4);
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__bss_start =.;
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.bss (NOLOAD): {
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*(.bss)
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. = ALIGN(4);
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.rel.dyn : {
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__rel_dyn_start = .;
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*(.rel*)
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__rel_dyn_end = .;
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}
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.dynsym : {
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__dynsym_start = .;
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*(.dynsym)
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}
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.bss __rel_dyn_start (OVERLAY) : {
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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_end = .;
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}
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__bss_end__ =.;
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/DISCARD/ : { *(.dynstr*) }
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/DISCARD/ : { *(.dynamic*) }
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/DISCARD/ : { *(.plt*) }
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/DISCARD/ : { *(.interp*) }
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/DISCARD/ : { *(.gnu*) }
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}
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@ -37,12 +37,12 @@
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds"
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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#undef CONFIG_USE_IRQ
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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@ -82,8 +82,9 @@
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#define CONFIG_SYS_MEMTEST_START 0x00400000
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#define CONFIG_SYS_MEMTEST_END 0x00800000
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/* spec says 66.666 MHz, but it appears to be 33 */
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#define CONFIG_SYS_HZ 3333333
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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#define CONFIG_SYS_HZ 1000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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@ -99,10 +100,6 @@
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/* Expansion bus settings */
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#define CONFIG_SYS_EXP_CS0 0xbd113442
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@ -110,7 +107,7 @@
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/* SDRAM settings */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define CONFIG_SYS_DRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/* 16MB SDRAM */
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#define CONFIG_SYS_SDR_CONFIG 0x3A
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@ -120,6 +117,7 @@
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#define CONFIG_SYS_DRAM_SIZE 0x01000000
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/* FLASH organization */
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 140
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@ -129,6 +127,7 @@
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_BOARD_SIZE_LIMIT 262144
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/* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI
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@ -149,6 +148,11 @@
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#define CONFIG_PHY_ADDR 0x10
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/* MII PHY management */
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#define CONFIG_MII 1
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/* fixed-speed switch without standard PHY registers on MII */
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#define CONFIG_MII_NPE0_FIXEDLINK 1
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#define CONFIG_MII_NPE0_SPEED 100
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#define CONFIG_MII_NPE0_FULLDUPLEX 1
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/* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_RESET_PHY_R 1
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@ -183,13 +187,15 @@
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"npe_ucode=50040000\0" \
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"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
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"kerneladdr=50050000\0" \
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"kernelfile=actux3/uImage\0" \
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"rootfile=actux3/rootfs\0" \
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"rootaddr=50170000\0" \
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"loadaddr=10000\0" \
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"updateboot_ser=mw.b 10000 ff 40000;" \
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" loady ${loadaddr};" \
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" run eraseboot writeboot\0" \
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"updateboot_net=mw.b 10000 ff 40000;" \
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" tftp ${loadaddr} u-boot.bin;" \
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" tftp ${loadaddr} actux3/u-boot.bin;" \
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" run eraseboot writeboot\0" \
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"eraseboot=protect off 50000000 50003fff;" \
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" protect off 50006000 5003ffff;" \
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@ -197,8 +203,9 @@
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" erase 50006000 5003ffff\0" \
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"writeboot=cp.b 10000 50000000 4000;" \
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" cp.b 16000 50006000 3a000\0" \
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"eraseenv=protect off 50004000 50005fff;" \
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" erase 50004000 50005fff\0" \
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"updateucode=loady;" \
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" era ${npe_ucode} +${filesize};" \
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" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
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"updateroot=tftp ${loadaddr} ${rootfile};" \
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" era ${rootaddr} +${filesize};" \
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" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
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@ -209,7 +216,7 @@
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
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"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
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"boot_flash=run flashargs addtty addeth;" \
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" bootm ${kerneladdr}\0" \
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@ -217,4 +224,8 @@
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" tftpboot ${loadaddr} ${kernelfile};" \
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" bootm\0"
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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