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clk: actions: Add common clock driver

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This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit is contained in:
Amit Singh Tomar 2020-04-19 19:28:30 +05:30 committed by Tom Rini
parent 5bc4c0bccc
commit 8b520ac153
7 changed files with 119 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -877,6 +877,8 @@ config ARCH_OWL
select DM
select DM_SERIAL
select OWL_SERIAL
select CLK
select CLK_OWL
select OF_CONTROL
imply CMD_DM

56
arch/arm/include/asm/arch-owl/regs_s700.h Normal file
View File

@ -0,0 +1,56 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Actions Semi S700 Register Definitions
*
*/
#ifndef _OWL_REGS_S700_H_
#define _OWL_REGS_S700_H_
#define CMU_COREPLL 0x0000
#define CMU_DEVPLL 0x0004
#define CMU_DDRPLL 0x0008
#define CMU_NANDPLL 0x000C
#define CMU_DISPLAYPLL 0x0010
#define CMU_AUDIOPLL 0x0014
#define CMU_TVOUTPLL 0x0018
#define CMU_BUSCLK 0x001C
#define CMU_SENSORCLK 0x0020
#define CMU_LCDCLK 0x0024
#define CMU_DSIPLLCLK 0x0028
#define CMU_CSICLK 0x002C
#define CMU_DECLK 0x0030
#define CMU_SICLK 0x0034
#define CMU_BUSCLK1 0x0038
#define CMU_HDECLK 0x003C
#define CMU_VDECLK 0x0040
#define CMU_VCECLK 0x0044
#define CMU_NANDCCLK 0x004C
#define CMU_SD0CLK 0x0050
#define CMU_SD1CLK 0x0054
#define CMU_SD2CLK 0x0058
#define CMU_UART0CLK 0x005C
#define CMU_UART1CLK 0x0060
#define CMU_UART2CLK 0x0064
#define CMU_UART3CLK 0x0068
#define CMU_UART4CLK 0x006C
#define CMU_UART5CLK 0x0070
#define CMU_UART6CLK 0x0074
#define CMU_PWM0CLK 0x0078
#define CMU_PWM1CLK 0x007C
#define CMU_PWM2CLK 0x0080
#define CMU_PWM3CLK 0x0084
#define CMU_PWM4CLK 0x0088
#define CMU_PWM5CLK 0x008C
#define CMU_GPU3DCLK 0x0090
#define CMU_CORECTL 0x009C
#define CMU_DEVCLKEN0 0x00A0
#define CMU_DEVCLKEN1 0x00A4
#define CMU_DEVRST0 0x00A8
#define CMU_DEVRST1 0x00AC
#define CMU_USBPLL 0x00B0
#define CMU_ETHERNETPLL 0x00B4
#define CMU_CVBSPLL 0x00B8
#define CMU_SSTSCLK 0x00C0
#endif

3
configs/bubblegum_96_defconfig
View File

@ -17,6 +17,3 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CLK=y
CONFIG_CLK_OWL=y
CONFIG_CLK_S900=y

8
drivers/clk/owl/Kconfig
View File

@ -3,10 +3,6 @@ config CLK_OWL
depends on CLK && ARCH_OWL
help
Enable support for clock managemet unit present in Actions Semi
OWL SoCs.
Owl series S900/S700 SoCs.
config CLK_S900
bool "Actions Semi S900 clock driver"
depends on CLK_OWL && ARM64
help
Enable support for the clocks in Actions Semi S900 SoC.

2
drivers/clk/owl/Makefile
View File

@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_CLK_S900) += clk_s900.o
obj-$(CONFIG_CLK_OWL) += clk_owl.o

72
drivers/clk/owl/clk_s900.c → drivers/clk/owl/clk_owl.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Actions Semi S900 clock driver
* Common clock driver for Actions Semi SoCs.
*
* Copyright (C) 2015 Actions Semi Co., Ltd.
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@ -8,20 +8,25 @@
#include <common.h>
#include <dm.h>
#include <asm/arch-owl/clk_s900.h>
#include <asm/arch-owl/regs_s900.h>
#include "clk_owl.h"
#include <asm/io.h>
#if defined(CONFIG_MACH_S900)
#include <asm/arch-owl/regs_s900.h>
#include <dt-bindings/clock/actions,s900-cmu.h>
#elif defined(CONFIG_MACH_S700)
#include <asm/arch-owl/regs_s700.h>
#include <dt-bindings/clock/actions,s700-cmu.h>
#endif
void owl_clk_init(struct owl_clk_priv *priv)
{
u32 bus_clk = 0, core_pll, dev_pll;
#if defined(CONFIG_MACH_S900)
/* Enable ASSIST_PLL */
setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
udelay(PLL_STABILITY_WAIT_US);
#endif
/* Source HOSC to DEV_CLK */
clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
@ -58,31 +63,30 @@ void owl_clk_init(struct owl_clk_priv *priv)
udelay(PLL_STABILITY_WAIT_US);
}
void owl_uart_clk_enable(struct owl_clk_priv *priv)
{
/* Source HOSC for UART5 interface */
clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
/* Enable UART5 interface clock */
setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
}
void owl_uart_clk_disable(struct owl_clk_priv *priv)
{
/* Disable UART5 interface clock */
clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
}
int owl_clk_enable(struct clk *clk)
{
struct owl_clk_priv *priv = dev_get_priv(clk->dev);
enum owl_soc model = dev_get_driver_data(clk->dev);
switch (clk->id) {
case CLK_UART5:
owl_uart_clk_enable(priv);
if (model != S900)
return -EINVAL;
/* Source HOSC for UART5 interface */
clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
/* Enable UART5 interface clock */
setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
break;
case CLK_UART3:
if (model != S700)
return -EINVAL;
/* Source HOSC for UART3 interface */
clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
/* Enable UART3 interface clock */
setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
break;
default:
return 0;
return -EINVAL;
}
return 0;
@ -91,13 +95,23 @@ int owl_clk_enable(struct clk *clk)
int owl_clk_disable(struct clk *clk)
{
struct owl_clk_priv *priv = dev_get_priv(clk->dev);
enum owl_soc model = dev_get_driver_data(clk->dev);
switch (clk->id) {
case CLK_UART5:
owl_uart_clk_disable(priv);
if (model != S900)
return -EINVAL;
/* Disable UART5 interface clock */
clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
break;
case CLK_UART3:
if (model != S700)
return -EINVAL;
/* Disable UART3 interface clock */
clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
break;
default:
return 0;
return -EINVAL;
}
return 0;
@ -117,18 +131,22 @@ static int owl_clk_probe(struct udevice *dev)
return 0;
}
static struct clk_ops owl_clk_ops = {
static const struct clk_ops owl_clk_ops = {
.enable = owl_clk_enable,
.disable = owl_clk_disable,
};
static const struct udevice_id owl_clk_ids[] = {
{ .compatible = "actions,s900-cmu" },
#if defined(CONFIG_MACH_S900)
{ .compatible = "actions,s900-cmu", .data = S900 },
#elif defined(CONFIG_MACH_S700)
{ .compatible = "actions,s700-cmu", .data = S700 },
#endif
{ }
};
U_BOOT_DRIVER(clk_owl) = {
.name = "clk_s900",
.name = "clk_owl",
.id = UCLASS_CLK,
.of_match = owl_clk_ids,
.ops = &owl_clk_ops,

19
arch/arm/include/asm/arch-owl/clk_s900.h → drivers/clk/owl/clk_owl.h
View File

@ -1,17 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Actions Semi S900 Clock Definitions
* Actions Semi SoCs Clock Definitions
*
* Copyright (C) 2015 Actions Semi Co., Ltd.
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*
*/
#ifndef _OWL_CLK_S900_H_
#define _OWL_CLK_S900_H_
#ifndef _OWL_CLK_H_
#define _OWL_CLK_H_
#include <clk-uclass.h>
enum owl_soc {
S700,
S900,
};
struct owl_clk_priv {
phys_addr_t base;
};
@ -49,9 +54,11 @@ struct owl_clk_priv {
/* UARTCLK register definitions */
#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
/* DEVCLKEN1 register definitions */
#define CMU_DEVCLKEN1_UART5 BIT(21)
#define PLL_STABILITY_WAIT_US 50
#define CMU_DEVCLKEN1_UART5 BIT(21)
#define CMU_DEVCLKEN1_UART3 BIT(11)
#define CMU_DEVCLKEN1_ETH_S700 BIT(23)
#endif