mirror of
https://github.com/u-boot/u-boot.git
synced 2025-01-24 19:53:25 +08:00
Update AR405 board.
This commit is contained in:
stroese
parent
e623a1a394
commit
8b1ccd8693
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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OBJS = $(BOARD).o flash.o ../common/misc.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2001
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -28,6 +28,7 @@
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/*cmd_boot.c*/
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* ------------------------------------------------------------------------- */
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@ -40,6 +41,10 @@ const unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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const unsigned char fpgadata_xl30[] = {
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#include "fpgadata_xl30.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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@ -64,45 +69,52 @@ int board_early_init_f (void)
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/*
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* Boot onboard FPGA
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*/
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/* first try 40er image */
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gd->board_type = 40;
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status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
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if (status != 0) {
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/* booting FPGA failed */
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/* try xl30er image */
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gd->board_type = 30;
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status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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/*
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@ -139,32 +151,44 @@ int board_early_init_f (void)
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int index;
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int len;
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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const unsigned char *fpga;
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puts ("Board: ");
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if (!i || strncmp (str, "AR405", 5)) {
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puts ("### No HW ID - assuming AR405\n");
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return (0);
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if (i == -1) {
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puts ("### No HW ID - assuming AR405");
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} else {
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puts(str);
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}
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puts (str);
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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if (gd->board_type == 30) {
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fpga = fpgadata_xl30;
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} else {
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fpga = fpgadata;
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}
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("%s ", &(fpgadata[index + 1]));
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len = fpga[index];
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printf ("%s ", &(fpga[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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@ -26,4 +26,5 @@
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#
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#TEXT_BASE = 0xFFFE0000
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TEXT_BASE = 0xFFFD0000
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#TEXT_BASE = 0xFFFD0000
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TEXT_BASE = 0xFFFC0000
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@ -33,18 +33,19 @@
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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static ulong flash_get_size (vu_long * addr, flash_info_t * info);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0, size_b1;
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unsigned long size_b0;
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int i;
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uint pbcr;
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unsigned long base_b0, base_b1;
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unsigned long base_b0;
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int size_val = 0;
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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@ -53,74 +54,48 @@ unsigned long flash_init (void)
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/* Static FLASH Bank configuration here - FIXME XXX */
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base_b0 = FLASH_BASE0_PRELIM;
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size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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base_b1 = FLASH_BASE1_PRELIM;
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size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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/* Re-do sizing to get full correct info */
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mtdcr(ebccfga, pb0cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb0cr);
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base_b0 = -size_b0;
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switch (size_b0) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
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mtdcr(ebccfgd, pbcr);
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if (size_b1)
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{
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mtdcr(ebccfga, pb0cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb0cr);
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base_b1 = -size_b1;
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pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
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mtdcr(ebccfgd, pbcr);
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/* printf("pb1cr = %x\n", pbcr); */
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}
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if (size_b0)
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{
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mtdcr(ebccfga, pb1cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb1cr);
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base_b0 = base_b1 - size_b0;
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
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mtdcr(ebccfgd, pbcr);
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/* printf("pb0cr = %x\n", pbcr); */
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}
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size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
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flash_get_offsets (base_b0, &flash_info[0]);
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/* monitor protection ON by default */
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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base_b0+size_b0-monitor_flash_len,
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base_b0+size_b0-1,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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if (size_b1) {
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/* Re-do sizing to get full correct info */
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size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
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flash_get_offsets (base_b1, &flash_info[1]);
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/* monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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base_b1+size_b1-monitor_flash_len,
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base_b1+size_b1-1,
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&flash_info[1]);
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/* monitor protection OFF by default (one is enough) */
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(void)flash_protect(FLAG_PROTECT_CLEAR,
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base_b0+size_b0-monitor_flash_len,
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base_b0+size_b0-1,
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&flash_info[0]);
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} else {
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[1].sector_count = -1;
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}
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flash_info[0].size = size_b0;
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flash_info[1].size = size_b1;
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return (size_b0 + size_b1);
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return (size_b0);
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}
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2285
board/esd/ar405/fpgadata_xl30.c
Normal file
2285
board/esd/ar405/fpgadata_xl30.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2001
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -41,6 +41,8 @@
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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@ -60,16 +62,23 @@
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#endif
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_PCI | \
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CFG_CMD_IRQ | \
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CFG_CMD_ELF )
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CFG_CMD_ELF | \
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CFG_CMD_MII | \
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CFG_CMD_PING | \
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CFG_CMD_BSP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@ -92,8 +101,12 @@
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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@ -143,9 +156,9 @@
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFFD0000
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#define CFG_FLASH_BASE 0xFFFC0000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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@ -157,7 +170,7 @@
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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@ -185,7 +198,8 @@
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
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#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
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/* have only 8kB, 16kB is save here */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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@ -197,8 +211,7 @@
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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